Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 945
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T88 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2424132952 Jun 04 12:52:14 PM PDT 24 Jun 04 12:52:15 PM PDT 24 209875589 ps
T44 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.876064772 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:01 PM PDT 24 129178046 ps
T761 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2438813172 Jun 04 12:52:02 PM PDT 24 Jun 04 12:52:03 PM PDT 24 13023559 ps
T762 /workspace/coverage/cover_reg_top/49.gpio_intr_test.327036583 Jun 04 12:52:30 PM PDT 24 Jun 04 12:52:32 PM PDT 24 67515760 ps
T763 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3132889900 Jun 04 12:52:03 PM PDT 24 Jun 04 12:52:04 PM PDT 24 46400144 ps
T764 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3273548525 Jun 04 12:52:08 PM PDT 24 Jun 04 12:52:10 PM PDT 24 12726859 ps
T765 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3194265059 Jun 04 12:52:23 PM PDT 24 Jun 04 12:52:25 PM PDT 24 24835712 ps
T766 /workspace/coverage/cover_reg_top/7.gpio_intr_test.34862160 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:00 PM PDT 24 48562894 ps
T767 /workspace/coverage/cover_reg_top/36.gpio_intr_test.276028689 Jun 04 12:52:12 PM PDT 24 Jun 04 12:52:14 PM PDT 24 14735844 ps
T768 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2835707078 Jun 04 12:52:14 PM PDT 24 Jun 04 12:52:15 PM PDT 24 15457075 ps
T769 /workspace/coverage/cover_reg_top/9.gpio_intr_test.4255715822 Jun 04 12:52:00 PM PDT 24 Jun 04 12:52:02 PM PDT 24 10488486 ps
T89 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3484457291 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:01 PM PDT 24 92620763 ps
T770 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1796659968 Jun 04 12:52:05 PM PDT 24 Jun 04 12:52:07 PM PDT 24 99825081 ps
T771 /workspace/coverage/cover_reg_top/21.gpio_intr_test.513273466 Jun 04 12:52:29 PM PDT 24 Jun 04 12:52:31 PM PDT 24 15226660 ps
T772 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2191654135 Jun 04 12:52:13 PM PDT 24 Jun 04 12:52:15 PM PDT 24 54030483 ps
T773 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1846796962 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:00 PM PDT 24 41953579 ps
T774 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1813942696 Jun 04 12:52:12 PM PDT 24 Jun 04 12:52:13 PM PDT 24 14127461 ps
T775 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.91159613 Jun 04 12:52:01 PM PDT 24 Jun 04 12:52:03 PM PDT 24 35618228 ps
T776 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2392321302 Jun 04 12:51:53 PM PDT 24 Jun 04 12:51:55 PM PDT 24 13530682 ps
T777 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4011802827 Jun 04 12:52:03 PM PDT 24 Jun 04 12:52:05 PM PDT 24 111097848 ps
T778 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3708324225 Jun 04 12:52:04 PM PDT 24 Jun 04 12:52:06 PM PDT 24 31237233 ps
T779 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4293643318 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:01 PM PDT 24 112754372 ps
T780 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.801243067 Jun 04 12:52:06 PM PDT 24 Jun 04 12:52:07 PM PDT 24 40954464 ps
T781 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1605417203 Jun 04 12:52:18 PM PDT 24 Jun 04 12:52:19 PM PDT 24 14464232 ps
T782 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3753263215 Jun 04 12:51:52 PM PDT 24 Jun 04 12:51:55 PM PDT 24 19766035 ps
T783 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2286753962 Jun 04 12:52:11 PM PDT 24 Jun 04 12:52:13 PM PDT 24 18739174 ps
T784 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2254189713 Jun 04 12:52:14 PM PDT 24 Jun 04 12:52:15 PM PDT 24 43268992 ps
T785 /workspace/coverage/cover_reg_top/17.gpio_intr_test.479518468 Jun 04 12:52:05 PM PDT 24 Jun 04 12:52:07 PM PDT 24 45586397 ps
T786 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.101362403 Jun 04 12:51:49 PM PDT 24 Jun 04 12:51:51 PM PDT 24 71282402 ps
T79 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3620228805 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:01 PM PDT 24 87007297 ps
T787 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1959432061 Jun 04 12:52:05 PM PDT 24 Jun 04 12:52:06 PM PDT 24 15258525 ps
T788 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3975660237 Jun 04 12:52:11 PM PDT 24 Jun 04 12:52:13 PM PDT 24 37134401 ps
T789 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2256109423 Jun 04 12:51:50 PM PDT 24 Jun 04 12:51:52 PM PDT 24 178783865 ps
T790 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3318854657 Jun 04 12:51:56 PM PDT 24 Jun 04 12:51:58 PM PDT 24 13969400 ps
T791 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1759460645 Jun 04 12:51:47 PM PDT 24 Jun 04 12:51:49 PM PDT 24 11308011 ps
T792 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3852775316 Jun 04 12:51:49 PM PDT 24 Jun 04 12:51:51 PM PDT 24 36707668 ps
T793 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3180884963 Jun 04 12:52:07 PM PDT 24 Jun 04 12:52:10 PM PDT 24 48547455 ps
T794 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1351326010 Jun 04 12:51:43 PM PDT 24 Jun 04 12:51:44 PM PDT 24 77667787 ps
T795 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4275877472 Jun 04 12:51:48 PM PDT 24 Jun 04 12:51:51 PM PDT 24 79108501 ps
T796 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3896520809 Jun 04 12:52:00 PM PDT 24 Jun 04 12:52:02 PM PDT 24 21672407 ps
T797 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2788045465 Jun 04 12:51:56 PM PDT 24 Jun 04 12:52:00 PM PDT 24 359867133 ps
T104 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.489841888 Jun 04 12:52:08 PM PDT 24 Jun 04 12:52:10 PM PDT 24 462611470 ps
T798 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3634606491 Jun 04 12:51:57 PM PDT 24 Jun 04 12:51:59 PM PDT 24 35055920 ps
T799 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.742680517 Jun 04 12:51:56 PM PDT 24 Jun 04 12:51:59 PM PDT 24 420781180 ps
T800 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3475062985 Jun 04 12:52:03 PM PDT 24 Jun 04 12:52:05 PM PDT 24 57421390 ps
T801 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3850346685 Jun 04 12:52:10 PM PDT 24 Jun 04 12:52:13 PM PDT 24 38745492 ps
T802 /workspace/coverage/cover_reg_top/22.gpio_intr_test.94915851 Jun 04 12:52:14 PM PDT 24 Jun 04 12:52:16 PM PDT 24 35102545 ps
T803 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.193040966 Jun 04 12:51:57 PM PDT 24 Jun 04 12:52:00 PM PDT 24 143835890 ps
T804 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2965833670 Jun 04 12:52:21 PM PDT 24 Jun 04 12:52:22 PM PDT 24 17885868 ps
T805 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3204284890 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:00 PM PDT 24 165172529 ps
T80 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2611977952 Jun 04 12:51:51 PM PDT 24 Jun 04 12:51:54 PM PDT 24 59729479 ps
T806 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1727958024 Jun 04 12:52:07 PM PDT 24 Jun 04 12:52:08 PM PDT 24 62589685 ps
T105 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1109227686 Jun 04 12:51:50 PM PDT 24 Jun 04 12:51:52 PM PDT 24 150173650 ps
T807 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1214000841 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:01 PM PDT 24 25698101 ps
T808 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3360752107 Jun 04 12:52:00 PM PDT 24 Jun 04 12:52:03 PM PDT 24 505011208 ps
T809 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1284052148 Jun 04 12:52:01 PM PDT 24 Jun 04 12:52:03 PM PDT 24 404288879 ps
T810 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2103804568 Jun 04 12:52:04 PM PDT 24 Jun 04 12:52:06 PM PDT 24 54829633 ps
T811 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3214683000 Jun 04 12:52:03 PM PDT 24 Jun 04 12:52:05 PM PDT 24 21831985 ps
T812 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1640597043 Jun 04 12:52:04 PM PDT 24 Jun 04 12:52:07 PM PDT 24 105637633 ps
T813 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3544988467 Jun 04 12:52:16 PM PDT 24 Jun 04 12:52:17 PM PDT 24 13869522 ps
T814 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2550871587 Jun 04 12:51:57 PM PDT 24 Jun 04 12:51:59 PM PDT 24 32895142 ps
T815 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1678021367 Jun 04 12:52:07 PM PDT 24 Jun 04 12:52:12 PM PDT 24 234936406 ps
T816 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.532506004 Jun 04 12:51:52 PM PDT 24 Jun 04 12:52:00 PM PDT 24 510961603 ps
T817 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3450553772 Jun 04 12:51:51 PM PDT 24 Jun 04 12:51:53 PM PDT 24 35501611 ps
T818 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1205481139 Jun 04 12:52:01 PM PDT 24 Jun 04 12:52:03 PM PDT 24 32379047 ps
T819 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2085321348 Jun 04 12:52:03 PM PDT 24 Jun 04 12:52:06 PM PDT 24 227001223 ps
T820 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2799226143 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:03 PM PDT 24 531054792 ps
T821 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1670296728 Jun 04 12:52:08 PM PDT 24 Jun 04 12:52:10 PM PDT 24 20188743 ps
T822 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.627629092 Jun 04 12:52:00 PM PDT 24 Jun 04 12:52:02 PM PDT 24 179947349 ps
T823 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3927414245 Jun 04 12:51:59 PM PDT 24 Jun 04 12:52:01 PM PDT 24 18659912 ps
T824 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2501858925 Jun 04 12:52:13 PM PDT 24 Jun 04 12:52:14 PM PDT 24 27694112 ps
T825 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.22346886 Jun 04 12:52:23 PM PDT 24 Jun 04 12:52:30 PM PDT 24 18167058 ps
T826 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3370154047 Jun 04 12:51:56 PM PDT 24 Jun 04 12:51:59 PM PDT 24 91451267 ps
T827 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3004049579 Jun 04 12:51:52 PM PDT 24 Jun 04 12:51:55 PM PDT 24 93053422 ps
T828 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2951975358 Jun 04 12:52:01 PM PDT 24 Jun 04 12:52:05 PM PDT 24 384436535 ps
T829 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3810666935 Jun 04 12:52:07 PM PDT 24 Jun 04 12:52:08 PM PDT 24 157850323 ps
T830 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3333529945 Jun 04 12:52:26 PM PDT 24 Jun 04 12:52:29 PM PDT 24 43333845 ps
T81 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2536692724 Jun 04 12:52:23 PM PDT 24 Jun 04 12:52:24 PM PDT 24 13734818 ps
T831 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3005531116 Jun 04 12:52:25 PM PDT 24 Jun 04 12:52:27 PM PDT 24 55461444 ps
T832 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.25841729 Jun 04 12:52:08 PM PDT 24 Jun 04 12:52:10 PM PDT 24 46638766 ps
T833 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.932605719 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:01 PM PDT 24 47999685 ps
T834 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3457224631 Jun 04 12:51:59 PM PDT 24 Jun 04 12:52:02 PM PDT 24 140807874 ps
T42 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2466729162 Jun 04 12:51:49 PM PDT 24 Jun 04 12:51:51 PM PDT 24 442517546 ps
T835 /workspace/coverage/cover_reg_top/16.gpio_intr_test.890326734 Jun 04 12:52:06 PM PDT 24 Jun 04 12:52:07 PM PDT 24 19696388 ps
T82 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3505754292 Jun 04 12:52:08 PM PDT 24 Jun 04 12:52:10 PM PDT 24 12064414 ps
T836 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1150233109 Jun 04 12:52:26 PM PDT 24 Jun 04 12:52:29 PM PDT 24 122562712 ps
T837 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2170912216 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:00 PM PDT 24 14052597 ps
T838 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.286424481 Jun 04 12:51:56 PM PDT 24 Jun 04 12:51:58 PM PDT 24 43977462 ps
T839 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.712415208 Jun 04 12:52:05 PM PDT 24 Jun 04 12:52:07 PM PDT 24 22955579 ps
T840 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3814689773 Jun 04 12:51:57 PM PDT 24 Jun 04 12:52:00 PM PDT 24 37492040 ps
T841 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2873206470 Jun 04 12:51:55 PM PDT 24 Jun 04 12:51:57 PM PDT 24 807109891 ps
T842 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3074834058 Jun 04 12:51:49 PM PDT 24 Jun 04 12:51:51 PM PDT 24 14665295 ps
T843 /workspace/coverage/cover_reg_top/42.gpio_intr_test.639211642 Jun 04 12:52:26 PM PDT 24 Jun 04 12:52:28 PM PDT 24 13258557 ps
T844 /workspace/coverage/cover_reg_top/13.gpio_intr_test.960694446 Jun 04 12:52:03 PM PDT 24 Jun 04 12:52:04 PM PDT 24 34361050 ps
T845 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2049385072 Jun 04 12:51:54 PM PDT 24 Jun 04 12:51:57 PM PDT 24 235245780 ps
T846 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.44878453 Jun 04 12:23:20 PM PDT 24 Jun 04 12:23:23 PM PDT 24 297520500 ps
T847 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3714369117 Jun 04 12:23:54 PM PDT 24 Jun 04 12:23:57 PM PDT 24 99471444 ps
T848 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3572179755 Jun 04 12:23:33 PM PDT 24 Jun 04 12:23:36 PM PDT 24 82600932 ps
T849 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2834549391 Jun 04 12:23:32 PM PDT 24 Jun 04 12:23:35 PM PDT 24 211636754 ps
T850 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1514800870 Jun 04 12:23:13 PM PDT 24 Jun 04 12:23:16 PM PDT 24 412788800 ps
T851 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2261628848 Jun 04 12:23:27 PM PDT 24 Jun 04 12:23:29 PM PDT 24 50758273 ps
T852 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3302332104 Jun 04 12:21:03 PM PDT 24 Jun 04 12:21:05 PM PDT 24 38345456 ps
T853 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2175127967 Jun 04 12:23:07 PM PDT 24 Jun 04 12:23:10 PM PDT 24 99483273 ps
T854 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3164919147 Jun 04 12:23:46 PM PDT 24 Jun 04 12:23:48 PM PDT 24 147487595 ps
T855 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3676487958 Jun 04 12:23:42 PM PDT 24 Jun 04 12:23:45 PM PDT 24 80807470 ps
T856 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2564046938 Jun 04 12:23:31 PM PDT 24 Jun 04 12:23:36 PM PDT 24 464865438 ps
T857 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2224862794 Jun 04 12:23:05 PM PDT 24 Jun 04 12:23:08 PM PDT 24 47729974 ps
T858 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1045604886 Jun 04 12:22:16 PM PDT 24 Jun 04 12:22:18 PM PDT 24 157971326 ps
T859 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3378942207 Jun 04 12:23:05 PM PDT 24 Jun 04 12:23:08 PM PDT 24 230815873 ps
T860 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2851352182 Jun 04 12:23:56 PM PDT 24 Jun 04 12:23:58 PM PDT 24 119566792 ps
T861 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2390063386 Jun 04 12:20:21 PM PDT 24 Jun 04 12:20:22 PM PDT 24 196295895 ps
T862 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1213744827 Jun 04 12:23:05 PM PDT 24 Jun 04 12:23:08 PM PDT 24 188647076 ps
T863 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1996523987 Jun 04 12:22:24 PM PDT 24 Jun 04 12:22:26 PM PDT 24 38971032 ps
T864 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3611101263 Jun 04 12:19:44 PM PDT 24 Jun 04 12:19:46 PM PDT 24 50638424 ps
T865 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2399952423 Jun 04 12:22:00 PM PDT 24 Jun 04 12:22:02 PM PDT 24 79884826 ps
T866 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2526245169 Jun 04 12:23:32 PM PDT 24 Jun 04 12:23:36 PM PDT 24 415581592 ps
T867 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2496660314 Jun 04 12:18:52 PM PDT 24 Jun 04 12:18:54 PM PDT 24 86615304 ps
T868 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1503251661 Jun 04 12:20:23 PM PDT 24 Jun 04 12:20:24 PM PDT 24 114663258 ps
T869 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1295181722 Jun 04 12:23:22 PM PDT 24 Jun 04 12:23:24 PM PDT 24 77533261 ps
T870 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3447373361 Jun 04 12:23:59 PM PDT 24 Jun 04 12:24:01 PM PDT 24 139374106 ps
T871 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2224940171 Jun 04 12:18:01 PM PDT 24 Jun 04 12:18:02 PM PDT 24 86146829 ps
T872 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.523716938 Jun 04 12:17:55 PM PDT 24 Jun 04 12:17:57 PM PDT 24 95067119 ps
T873 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2784977968 Jun 04 12:20:22 PM PDT 24 Jun 04 12:20:24 PM PDT 24 581696841 ps
T874 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1617796999 Jun 04 12:22:24 PM PDT 24 Jun 04 12:22:26 PM PDT 24 53044300 ps
T875 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2759058008 Jun 04 12:23:14 PM PDT 24 Jun 04 12:23:17 PM PDT 24 31782215 ps
T876 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1705392266 Jun 04 12:22:15 PM PDT 24 Jun 04 12:22:17 PM PDT 24 66531363 ps
T877 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1262768048 Jun 04 12:23:34 PM PDT 24 Jun 04 12:23:37 PM PDT 24 88375719 ps
T878 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3360229776 Jun 04 12:22:25 PM PDT 24 Jun 04 12:22:27 PM PDT 24 261525918 ps
T879 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1179817534 Jun 04 12:23:17 PM PDT 24 Jun 04 12:23:20 PM PDT 24 228478356 ps
T880 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2301128596 Jun 04 12:23:43 PM PDT 24 Jun 04 12:23:45 PM PDT 24 73062863 ps
T881 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4179217809 Jun 04 12:24:03 PM PDT 24 Jun 04 12:24:06 PM PDT 24 368450906 ps
T882 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3820991675 Jun 04 12:23:12 PM PDT 24 Jun 04 12:23:14 PM PDT 24 91235045 ps
T883 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1982690139 Jun 04 12:20:39 PM PDT 24 Jun 04 12:20:41 PM PDT 24 192379521 ps
T884 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2679284200 Jun 04 12:18:52 PM PDT 24 Jun 04 12:18:54 PM PDT 24 97219494 ps
T885 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1291052802 Jun 04 12:18:54 PM PDT 24 Jun 04 12:18:56 PM PDT 24 193475116 ps
T886 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2721644708 Jun 04 12:23:04 PM PDT 24 Jun 04 12:23:07 PM PDT 24 35220365 ps
T887 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.682064175 Jun 04 12:22:24 PM PDT 24 Jun 04 12:22:26 PM PDT 24 39281216 ps
T888 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3649138387 Jun 04 12:23:06 PM PDT 24 Jun 04 12:23:09 PM PDT 24 39196886 ps
T889 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2617082502 Jun 04 12:23:29 PM PDT 24 Jun 04 12:23:32 PM PDT 24 104459345 ps
T890 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1748306810 Jun 04 12:18:10 PM PDT 24 Jun 04 12:18:12 PM PDT 24 131937414 ps
T891 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3977870811 Jun 04 12:23:04 PM PDT 24 Jun 04 12:23:07 PM PDT 24 194505264 ps
T892 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3492994147 Jun 04 12:19:21 PM PDT 24 Jun 04 12:19:23 PM PDT 24 80193017 ps
T893 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1186998259 Jun 04 12:23:35 PM PDT 24 Jun 04 12:23:38 PM PDT 24 233322792 ps
T894 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2166194392 Jun 04 12:23:56 PM PDT 24 Jun 04 12:23:59 PM PDT 24 60260726 ps
T895 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.619469067 Jun 04 12:22:48 PM PDT 24 Jun 04 12:22:50 PM PDT 24 205322062 ps
T896 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.944321579 Jun 04 12:23:07 PM PDT 24 Jun 04 12:23:10 PM PDT 24 77267075 ps
T897 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1296148043 Jun 04 12:19:26 PM PDT 24 Jun 04 12:19:27 PM PDT 24 33273264 ps
T898 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.916927914 Jun 04 12:23:14 PM PDT 24 Jun 04 12:23:17 PM PDT 24 165020191 ps
T899 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1991279620 Jun 04 12:23:57 PM PDT 24 Jun 04 12:24:00 PM PDT 24 205522622 ps
T900 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.872917874 Jun 04 12:23:14 PM PDT 24 Jun 04 12:23:16 PM PDT 24 155168390 ps
T901 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2818820883 Jun 04 12:23:15 PM PDT 24 Jun 04 12:23:17 PM PDT 24 47632389 ps
T902 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2944303927 Jun 04 12:24:04 PM PDT 24 Jun 04 12:24:07 PM PDT 24 42114776 ps
T903 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1474878876 Jun 04 12:23:29 PM PDT 24 Jun 04 12:23:32 PM PDT 24 130200633 ps
T904 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.919490952 Jun 04 12:21:30 PM PDT 24 Jun 04 12:21:32 PM PDT 24 71654730 ps
T905 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2301013808 Jun 04 12:23:29 PM PDT 24 Jun 04 12:23:32 PM PDT 24 44959736 ps
T906 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.7510897 Jun 04 12:23:59 PM PDT 24 Jun 04 12:24:01 PM PDT 24 90362518 ps
T907 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.773665656 Jun 04 12:23:33 PM PDT 24 Jun 04 12:23:36 PM PDT 24 53217549 ps
T908 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1783662872 Jun 04 12:23:55 PM PDT 24 Jun 04 12:23:59 PM PDT 24 82038866 ps
T909 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1414186732 Jun 04 12:21:55 PM PDT 24 Jun 04 12:21:57 PM PDT 24 418472601 ps
T910 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3830508009 Jun 04 12:23:44 PM PDT 24 Jun 04 12:23:46 PM PDT 24 43120041 ps
T911 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1941338315 Jun 04 12:23:14 PM PDT 24 Jun 04 12:23:16 PM PDT 24 248399249 ps
T912 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.137296424 Jun 04 12:21:30 PM PDT 24 Jun 04 12:21:32 PM PDT 24 41291133 ps
T913 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1323844261 Jun 04 12:21:28 PM PDT 24 Jun 04 12:21:30 PM PDT 24 112109183 ps
T914 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2269505231 Jun 04 12:23:45 PM PDT 24 Jun 04 12:23:48 PM PDT 24 102867879 ps
T915 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2155607421 Jun 04 12:19:43 PM PDT 24 Jun 04 12:19:45 PM PDT 24 41818771 ps
T916 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1961770807 Jun 04 12:23:56 PM PDT 24 Jun 04 12:23:59 PM PDT 24 1324980652 ps
T917 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3793178419 Jun 04 12:24:03 PM PDT 24 Jun 04 12:24:06 PM PDT 24 153086129 ps
T918 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2486306897 Jun 04 12:23:29 PM PDT 24 Jun 04 12:23:33 PM PDT 24 34173084 ps
T919 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2553888812 Jun 04 12:24:03 PM PDT 24 Jun 04 12:24:06 PM PDT 24 83844598 ps
T920 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.421260159 Jun 04 12:23:07 PM PDT 24 Jun 04 12:23:10 PM PDT 24 199182272 ps
T921 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.382242328 Jun 04 12:23:56 PM PDT 24 Jun 04 12:23:59 PM PDT 24 85019077 ps
T922 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4045879441 Jun 04 12:23:29 PM PDT 24 Jun 04 12:23:32 PM PDT 24 66664628 ps
T923 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1096375980 Jun 04 12:23:59 PM PDT 24 Jun 04 12:24:01 PM PDT 24 51881265 ps
T924 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.71348676 Jun 04 12:20:21 PM PDT 24 Jun 04 12:20:22 PM PDT 24 62929156 ps
T925 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2315629138 Jun 04 12:23:54 PM PDT 24 Jun 04 12:23:55 PM PDT 24 21768261 ps
T926 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3102196085 Jun 04 12:24:03 PM PDT 24 Jun 04 12:24:06 PM PDT 24 309268437 ps
T927 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3661356200 Jun 04 12:23:59 PM PDT 24 Jun 04 12:24:00 PM PDT 24 79637451 ps
T928 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2482833149 Jun 04 12:23:11 PM PDT 24 Jun 04 12:23:13 PM PDT 24 409440494 ps
T929 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1917371172 Jun 04 12:23:13 PM PDT 24 Jun 04 12:23:16 PM PDT 24 203415771 ps
T930 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3621262369 Jun 04 12:20:05 PM PDT 24 Jun 04 12:20:07 PM PDT 24 48531564 ps
T931 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2647955236 Jun 04 12:19:45 PM PDT 24 Jun 04 12:19:46 PM PDT 24 179274604 ps
T932 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2035257390 Jun 04 12:18:53 PM PDT 24 Jun 04 12:18:54 PM PDT 24 300667855 ps
T933 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.950456621 Jun 04 12:23:35 PM PDT 24 Jun 04 12:23:38 PM PDT 24 154102065 ps
T934 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3008275000 Jun 04 12:23:29 PM PDT 24 Jun 04 12:23:31 PM PDT 24 71115231 ps
T935 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1743906359 Jun 04 12:23:11 PM PDT 24 Jun 04 12:23:13 PM PDT 24 79822554 ps
T936 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1883113451 Jun 04 12:21:09 PM PDT 24 Jun 04 12:21:10 PM PDT 24 29411454 ps
T937 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3773449756 Jun 04 12:23:29 PM PDT 24 Jun 04 12:23:32 PM PDT 24 34822069 ps
T938 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3376558868 Jun 04 12:23:29 PM PDT 24 Jun 04 12:23:32 PM PDT 24 38813904 ps
T939 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3975249008 Jun 04 12:23:59 PM PDT 24 Jun 04 12:24:01 PM PDT 24 52166826 ps
T940 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.559673757 Jun 04 12:19:20 PM PDT 24 Jun 04 12:19:22 PM PDT 24 42661616 ps
T941 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.98114297 Jun 04 12:18:44 PM PDT 24 Jun 04 12:18:46 PM PDT 24 53416510 ps
T942 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3013668913 Jun 04 12:23:59 PM PDT 24 Jun 04 12:24:02 PM PDT 24 495983888 ps
T943 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2410183314 Jun 04 12:18:40 PM PDT 24 Jun 04 12:18:42 PM PDT 24 1693187363 ps
T944 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3074727548 Jun 04 12:23:42 PM PDT 24 Jun 04 12:23:44 PM PDT 24 100012652 ps
T945 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.406605544 Jun 04 12:23:32 PM PDT 24 Jun 04 12:23:35 PM PDT 24 192637452 ps

Test location /workspace/coverage/default/3.gpio_stress_all.4265404846
Short name T22
Test name
Test status
Simulation time 17914821817 ps
CPU time 94.91 seconds
Started Jun 04 12:24:48 PM PDT 24
Finished Jun 04 12:26:24 PM PDT 24
Peak memory 198008 kb
Host smart-7b0e4add-2db4-4793-b154-63264f422709
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265404846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4265404846
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1689326690
Short name T23
Test name
Test status
Simulation time 216236150 ps
CPU time 2.35 seconds
Started Jun 04 12:26:58 PM PDT 24
Finished Jun 04 12:27:03 PM PDT 24
Peak memory 197852 kb
Host smart-42ee7e72-8a59-434f-8c8a-56ed9a6e0786
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689326690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1689326690
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.4091093631
Short name T14
Test name
Test status
Simulation time 5411576104 ps
CPU time 159.33 seconds
Started Jun 04 12:25:26 PM PDT 24
Finished Jun 04 12:28:06 PM PDT 24
Peak memory 198128 kb
Host smart-5a993a6b-39cb-4a1d-b8e2-5a555216011c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4091093631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.4091093631
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3301842912
Short name T71
Test name
Test status
Simulation time 16534448 ps
CPU time 0.62 seconds
Started Jun 04 12:52:03 PM PDT 24
Finished Jun 04 12:52:05 PM PDT 24
Peak memory 194520 kb
Host smart-d8bebb2e-ecbc-46bd-b21c-d3e275dcc8be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301842912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3301842912
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4096314271
Short name T41
Test name
Test status
Simulation time 131310476 ps
CPU time 1.38 seconds
Started Jun 04 12:51:54 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 197968 kb
Host smart-1881bab9-c9b3-4532-b13f-f6aaf6bf461f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096314271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.4096314271
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1647103248
Short name T3
Test name
Test status
Simulation time 861109614 ps
CPU time 5.06 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:26:02 PM PDT 24
Peak memory 197892 kb
Host smart-3cea8b41-dc7e-4eff-99d7-5fb956bf8304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647103248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1647103248
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1106323741
Short name T39
Test name
Test status
Simulation time 28276544 ps
CPU time 0.55 seconds
Started Jun 04 12:25:19 PM PDT 24
Finished Jun 04 12:25:20 PM PDT 24
Peak memory 193928 kb
Host smart-11743ba8-16bc-4c62-ad5c-16aaa96a7bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106323741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1106323741
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2050649530
Short name T35
Test name
Test status
Simulation time 40278634 ps
CPU time 0.75 seconds
Started Jun 04 12:24:43 PM PDT 24
Finished Jun 04 12:24:46 PM PDT 24
Peak memory 213512 kb
Host smart-faa2f732-b6b8-43ab-9946-2364588f5fad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050649530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2050649530
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2873206470
Short name T841
Test name
Test status
Simulation time 807109891 ps
CPU time 1.07 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 198008 kb
Host smart-abb2f25d-b694-42f5-9fcf-f77b21fee2ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873206470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2873206470
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1421994136
Short name T86
Test name
Test status
Simulation time 25543867 ps
CPU time 0.75 seconds
Started Jun 04 12:51:57 PM PDT 24
Finished Jun 04 12:51:59 PM PDT 24
Peak memory 196896 kb
Host smart-cc329104-70fa-4fe8-b8fd-456fa68342e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421994136 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1421994136
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3620228805
Short name T79
Test name
Test status
Simulation time 87007297 ps
CPU time 0.82 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:01 PM PDT 24
Peak memory 195744 kb
Host smart-09d720c8-5ce3-4faa-a68c-0cf3a7d4b793
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620228805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3620228805
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2611977952
Short name T80
Test name
Test status
Simulation time 59729479 ps
CPU time 2.24 seconds
Started Jun 04 12:51:51 PM PDT 24
Finished Jun 04 12:51:54 PM PDT 24
Peak memory 196776 kb
Host smart-33ff059d-4a27-49e7-b781-9579dbf56524
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611977952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2611977952
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1247434377
Short name T734
Test name
Test status
Simulation time 99125359 ps
CPU time 0.67 seconds
Started Jun 04 12:51:47 PM PDT 24
Finished Jun 04 12:51:50 PM PDT 24
Peak memory 194736 kb
Host smart-9602bed2-6f1b-4009-b8a6-abe34926c106
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247434377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1247434377
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.101362403
Short name T786
Test name
Test status
Simulation time 71282402 ps
CPU time 0.74 seconds
Started Jun 04 12:51:49 PM PDT 24
Finished Jun 04 12:51:51 PM PDT 24
Peak memory 197816 kb
Host smart-5f2c903f-b3bc-45a4-a776-d1bbde557cee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101362403 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.101362403
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1895772475
Short name T752
Test name
Test status
Simulation time 15948122 ps
CPU time 0.62 seconds
Started Jun 04 12:51:48 PM PDT 24
Finished Jun 04 12:51:50 PM PDT 24
Peak memory 195280 kb
Host smart-c54074cd-5bb2-4038-9ca2-3d814fe1a0d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895772475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1895772475
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3074834058
Short name T842
Test name
Test status
Simulation time 14665295 ps
CPU time 0.59 seconds
Started Jun 04 12:51:49 PM PDT 24
Finished Jun 04 12:51:51 PM PDT 24
Peak memory 193544 kb
Host smart-674ba020-e086-4393-844d-95c8eefacaf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074834058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3074834058
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.932605719
Short name T833
Test name
Test status
Simulation time 47999685 ps
CPU time 0.71 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:01 PM PDT 24
Peak memory 194752 kb
Host smart-f3df3e38-7a96-4205-8892-37ac50abb6b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932605719 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.932605719
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4275877472
Short name T795
Test name
Test status
Simulation time 79108501 ps
CPU time 1.93 seconds
Started Jun 04 12:51:48 PM PDT 24
Finished Jun 04 12:51:51 PM PDT 24
Peak memory 198008 kb
Host smart-4e614b18-1ed6-4285-9872-dffc5f087796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275877472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.4275877472
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1109227686
Short name T105
Test name
Test status
Simulation time 150173650 ps
CPU time 0.86 seconds
Started Jun 04 12:51:50 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 197184 kb
Host smart-97682187-1670-429c-b42e-36292e68148d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109227686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1109227686
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4098715358
Short name T101
Test name
Test status
Simulation time 36352481 ps
CPU time 0.67 seconds
Started Jun 04 12:51:48 PM PDT 24
Finished Jun 04 12:51:50 PM PDT 24
Peak memory 194708 kb
Host smart-750b5087-f738-4328-a803-c19dd8e0567f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098715358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.4098715358
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4249279592
Short name T730
Test name
Test status
Simulation time 35386657 ps
CPU time 1.38 seconds
Started Jun 04 12:51:53 PM PDT 24
Finished Jun 04 12:51:55 PM PDT 24
Peak memory 196316 kb
Host smart-3d84b881-754c-407d-9851-2c24abc31cae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249279592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.4249279592
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.765922267
Short name T103
Test name
Test status
Simulation time 54780877 ps
CPU time 0.62 seconds
Started Jun 04 12:51:52 PM PDT 24
Finished Jun 04 12:51:54 PM PDT 24
Peak memory 194444 kb
Host smart-2dcfdea9-4310-4fc1-85b8-f52875a62cc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765922267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.765922267
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1147876938
Short name T727
Test name
Test status
Simulation time 689261895 ps
CPU time 0.9 seconds
Started Jun 04 12:51:54 PM PDT 24
Finished Jun 04 12:51:56 PM PDT 24
Peak memory 197868 kb
Host smart-f1accc95-b7cb-4c81-9160-698940bbd765
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147876938 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1147876938
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3877748718
Short name T78
Test name
Test status
Simulation time 12577745 ps
CPU time 0.6 seconds
Started Jun 04 12:51:49 PM PDT 24
Finished Jun 04 12:51:51 PM PDT 24
Peak memory 194964 kb
Host smart-dbed400f-ea6e-46b9-87f5-cbad90180bb5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877748718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3877748718
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3852775316
Short name T792
Test name
Test status
Simulation time 36707668 ps
CPU time 0.61 seconds
Started Jun 04 12:51:49 PM PDT 24
Finished Jun 04 12:51:51 PM PDT 24
Peak memory 193588 kb
Host smart-a6f389f4-e0ab-496a-823c-ba7a38da1b17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852775316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3852775316
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4293643318
Short name T779
Test name
Test status
Simulation time 112754372 ps
CPU time 0.64 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:01 PM PDT 24
Peak memory 195476 kb
Host smart-1c552e4c-8133-4c02-87b8-c5c0fd2566ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293643318 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.4293643318
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.532506004
Short name T816
Test name
Test status
Simulation time 510961603 ps
CPU time 2.21 seconds
Started Jun 04 12:51:52 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 197880 kb
Host smart-b0593dd3-de9e-4e79-b9d4-286848ccf936
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532506004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.532506004
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2466729162
Short name T42
Test name
Test status
Simulation time 442517546 ps
CPU time 1.42 seconds
Started Jun 04 12:51:49 PM PDT 24
Finished Jun 04 12:51:51 PM PDT 24
Peak memory 197936 kb
Host smart-e4e7e516-d386-439d-9b9e-488802723126
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466729162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2466729162
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3896520809
Short name T796
Test name
Test status
Simulation time 21672407 ps
CPU time 0.96 seconds
Started Jun 04 12:52:00 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 197908 kb
Host smart-4a2a5107-a4b9-4f27-8fde-475211d05c20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896520809 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3896520809
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2609032636
Short name T737
Test name
Test status
Simulation time 16633406 ps
CPU time 0.6 seconds
Started Jun 04 12:52:00 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 194744 kb
Host smart-92ee898b-8b8b-4ad3-bb55-d5f6882c213c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609032636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2609032636
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3634606491
Short name T798
Test name
Test status
Simulation time 35055920 ps
CPU time 0.59 seconds
Started Jun 04 12:51:57 PM PDT 24
Finished Jun 04 12:51:59 PM PDT 24
Peak memory 193644 kb
Host smart-260b65f4-d3ba-43b7-b2b8-34410ff546e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634606491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3634606491
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2788045465
Short name T797
Test name
Test status
Simulation time 359867133 ps
CPU time 1.7 seconds
Started Jun 04 12:51:56 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 197972 kb
Host smart-c7057cc0-3d75-4659-9453-c1013a9a516e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788045465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2788045465
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4011802827
Short name T777
Test name
Test status
Simulation time 111097848 ps
CPU time 1.51 seconds
Started Jun 04 12:52:03 PM PDT 24
Finished Jun 04 12:52:05 PM PDT 24
Peak memory 197904 kb
Host smart-e136a728-9394-4de3-95f4-2d1e705dfc9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011802827 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.4011802827
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2536692724
Short name T81
Test name
Test status
Simulation time 13734818 ps
CPU time 0.6 seconds
Started Jun 04 12:52:23 PM PDT 24
Finished Jun 04 12:52:24 PM PDT 24
Peak memory 194696 kb
Host smart-58dbb8ab-f048-4349-b4f3-11285f9aa009
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536692724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2536692724
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1959432061
Short name T787
Test name
Test status
Simulation time 15258525 ps
CPU time 0.58 seconds
Started Jun 04 12:52:05 PM PDT 24
Finished Jun 04 12:52:06 PM PDT 24
Peak memory 194284 kb
Host smart-25628b4b-992c-4a22-8834-5ec005c42fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959432061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1959432061
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3475062985
Short name T800
Test name
Test status
Simulation time 57421390 ps
CPU time 0.79 seconds
Started Jun 04 12:52:03 PM PDT 24
Finished Jun 04 12:52:05 PM PDT 24
Peak memory 196272 kb
Host smart-d7a3a424-d718-43ed-8516-f37aa7f843ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475062985 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3475062985
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3180884963
Short name T793
Test name
Test status
Simulation time 48547455 ps
CPU time 2.53 seconds
Started Jun 04 12:52:07 PM PDT 24
Finished Jun 04 12:52:10 PM PDT 24
Peak memory 197972 kb
Host smart-747d67b1-86aa-4203-a579-a7737f763576
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180884963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3180884963
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1744504256
Short name T33
Test name
Test status
Simulation time 335191193 ps
CPU time 1.27 seconds
Started Jun 04 12:52:02 PM PDT 24
Finished Jun 04 12:52:04 PM PDT 24
Peak memory 197728 kb
Host smart-3ed35c16-2864-4e59-985a-7d27fbcc3098
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744504256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1744504256
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3496082303
Short name T717
Test name
Test status
Simulation time 20251207 ps
CPU time 0.73 seconds
Started Jun 04 12:52:05 PM PDT 24
Finished Jun 04 12:52:06 PM PDT 24
Peak memory 196832 kb
Host smart-e1f8388d-0ff6-4a98-b696-6cd3b05e35d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496082303 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3496082303
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3194265059
Short name T765
Test name
Test status
Simulation time 24835712 ps
CPU time 0.56 seconds
Started Jun 04 12:52:23 PM PDT 24
Finished Jun 04 12:52:25 PM PDT 24
Peak memory 193176 kb
Host smart-49964079-cf57-4860-bdd5-413176ab6f39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194265059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3194265059
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.874170622
Short name T757
Test name
Test status
Simulation time 20309565 ps
CPU time 0.59 seconds
Started Jun 04 12:52:08 PM PDT 24
Finished Jun 04 12:52:09 PM PDT 24
Peak memory 193496 kb
Host smart-aa788fba-dae4-45ed-bfef-21c856749bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874170622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.874170622
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2103804568
Short name T810
Test name
Test status
Simulation time 54829633 ps
CPU time 0.77 seconds
Started Jun 04 12:52:04 PM PDT 24
Finished Jun 04 12:52:06 PM PDT 24
Peak memory 196144 kb
Host smart-28780dac-422f-4893-b750-2096ae6cf6c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103804568 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2103804568
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2085321348
Short name T819
Test name
Test status
Simulation time 227001223 ps
CPU time 1.56 seconds
Started Jun 04 12:52:03 PM PDT 24
Finished Jun 04 12:52:06 PM PDT 24
Peak memory 197940 kb
Host smart-cb49740b-25ac-4f4c-a8a7-a7d45315dbd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085321348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2085321348
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.25841729
Short name T832
Test name
Test status
Simulation time 46638766 ps
CPU time 0.95 seconds
Started Jun 04 12:52:08 PM PDT 24
Finished Jun 04 12:52:10 PM PDT 24
Peak memory 196972 kb
Host smart-a147c28c-b35c-4daa-a93c-394e939a645f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25841729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.gpio_tl_intg_err.25841729
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1670296728
Short name T821
Test name
Test status
Simulation time 20188743 ps
CPU time 0.77 seconds
Started Jun 04 12:52:08 PM PDT 24
Finished Jun 04 12:52:10 PM PDT 24
Peak memory 197820 kb
Host smart-1bbd3864-c18a-49df-a485-6d0136132ec8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670296728 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1670296728
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3505754292
Short name T82
Test name
Test status
Simulation time 12064414 ps
CPU time 0.64 seconds
Started Jun 04 12:52:08 PM PDT 24
Finished Jun 04 12:52:10 PM PDT 24
Peak memory 194992 kb
Host smart-6e493722-4266-4d17-96dd-8206e8d8e9c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505754292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3505754292
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.960694446
Short name T844
Test name
Test status
Simulation time 34361050 ps
CPU time 0.61 seconds
Started Jun 04 12:52:03 PM PDT 24
Finished Jun 04 12:52:04 PM PDT 24
Peak memory 193668 kb
Host smart-778fb115-c166-48e7-b33e-02af2c253ba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960694446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.960694446
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.22346886
Short name T825
Test name
Test status
Simulation time 18167058 ps
CPU time 0.84 seconds
Started Jun 04 12:52:23 PM PDT 24
Finished Jun 04 12:52:30 PM PDT 24
Peak memory 196420 kb
Host smart-20d92276-0fbc-446c-8f84-776040a5526e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22346886 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.gpio_same_csr_outstanding.22346886
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1678021367
Short name T815
Test name
Test status
Simulation time 234936406 ps
CPU time 3.72 seconds
Started Jun 04 12:52:07 PM PDT 24
Finished Jun 04 12:52:12 PM PDT 24
Peak memory 197872 kb
Host smart-411b368f-fe4c-4252-af65-654535b85523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678021367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1678021367
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3132889900
Short name T763
Test name
Test status
Simulation time 46400144 ps
CPU time 0.81 seconds
Started Jun 04 12:52:03 PM PDT 24
Finished Jun 04 12:52:04 PM PDT 24
Peak memory 197240 kb
Host smart-4725c56f-ac67-4ab0-9c24-d21058903f8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132889900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3132889900
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2191654135
Short name T772
Test name
Test status
Simulation time 54030483 ps
CPU time 1.19 seconds
Started Jun 04 12:52:13 PM PDT 24
Finished Jun 04 12:52:15 PM PDT 24
Peak memory 198000 kb
Host smart-9bd936bc-347d-4e84-baf5-94deb4777fd8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191654135 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2191654135
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2438813172
Short name T761
Test name
Test status
Simulation time 13023559 ps
CPU time 0.61 seconds
Started Jun 04 12:52:02 PM PDT 24
Finished Jun 04 12:52:03 PM PDT 24
Peak memory 194372 kb
Host smart-ac7152e0-abfc-4244-a3c5-b93fb5b51aa2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438813172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2438813172
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3708324225
Short name T778
Test name
Test status
Simulation time 31237233 ps
CPU time 0.63 seconds
Started Jun 04 12:52:04 PM PDT 24
Finished Jun 04 12:52:06 PM PDT 24
Peak memory 194264 kb
Host smart-af41ad4a-8145-4d7c-a82a-233d7cbed885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708324225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3708324225
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1942401043
Short name T85
Test name
Test status
Simulation time 116195839 ps
CPU time 0.83 seconds
Started Jun 04 12:52:09 PM PDT 24
Finished Jun 04 12:52:10 PM PDT 24
Peak memory 195948 kb
Host smart-ff160b93-5fe8-4e05-93e4-7dc26ac469ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942401043 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1942401043
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3850346685
Short name T801
Test name
Test status
Simulation time 38745492 ps
CPU time 2.15 seconds
Started Jun 04 12:52:10 PM PDT 24
Finished Jun 04 12:52:13 PM PDT 24
Peak memory 197952 kb
Host smart-134bdc85-454e-4517-bebb-aa90ef4661d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850346685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3850346685
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2591222735
Short name T32
Test name
Test status
Simulation time 101599804 ps
CPU time 1.41 seconds
Started Jun 04 12:52:13 PM PDT 24
Finished Jun 04 12:52:15 PM PDT 24
Peak memory 197964 kb
Host smart-fa6ad9d5-a621-42c5-9cf4-ecc59051c946
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591222735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2591222735
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1727958024
Short name T806
Test name
Test status
Simulation time 62589685 ps
CPU time 0.92 seconds
Started Jun 04 12:52:07 PM PDT 24
Finished Jun 04 12:52:08 PM PDT 24
Peak memory 197912 kb
Host smart-5eda6b66-18b3-456d-842f-7f7bded52795
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727958024 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1727958024
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1605417203
Short name T781
Test name
Test status
Simulation time 14464232 ps
CPU time 0.6 seconds
Started Jun 04 12:52:18 PM PDT 24
Finished Jun 04 12:52:19 PM PDT 24
Peak memory 193592 kb
Host smart-2658268d-14cd-4757-8a07-ea032ecfc55f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605417203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1605417203
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1900849137
Short name T76
Test name
Test status
Simulation time 148963958 ps
CPU time 0.71 seconds
Started Jun 04 12:52:07 PM PDT 24
Finished Jun 04 12:52:09 PM PDT 24
Peak memory 194908 kb
Host smart-1d9ccf1a-87d8-4b9c-b227-0dc4d913dd67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900849137 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1900849137
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3810666935
Short name T829
Test name
Test status
Simulation time 157850323 ps
CPU time 1.03 seconds
Started Jun 04 12:52:07 PM PDT 24
Finished Jun 04 12:52:08 PM PDT 24
Peak memory 197880 kb
Host smart-985b0396-cb53-47f4-81ad-1c5ba41de824
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810666935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3810666935
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2810159864
Short name T46
Test name
Test status
Simulation time 104222438 ps
CPU time 0.88 seconds
Started Jun 04 12:52:04 PM PDT 24
Finished Jun 04 12:52:06 PM PDT 24
Peak memory 197752 kb
Host smart-e406d3aa-e95a-4921-829b-2446b6a1a6d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810159864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2810159864
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.712415208
Short name T839
Test name
Test status
Simulation time 22955579 ps
CPU time 1.08 seconds
Started Jun 04 12:52:05 PM PDT 24
Finished Jun 04 12:52:07 PM PDT 24
Peak memory 197948 kb
Host smart-f6853cf6-acd5-4041-a1b5-80994d910588
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712415208 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.712415208
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.801243067
Short name T780
Test name
Test status
Simulation time 40954464 ps
CPU time 0.55 seconds
Started Jun 04 12:52:06 PM PDT 24
Finished Jun 04 12:52:07 PM PDT 24
Peak memory 193904 kb
Host smart-e82fd67d-e9bf-42a7-a551-a8d2e80e662c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801243067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.801243067
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.890326734
Short name T835
Test name
Test status
Simulation time 19696388 ps
CPU time 0.6 seconds
Started Jun 04 12:52:06 PM PDT 24
Finished Jun 04 12:52:07 PM PDT 24
Peak memory 193660 kb
Host smart-9579f78c-d4a8-4875-bb1d-36c9055c3a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890326734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.890326734
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2424132952
Short name T88
Test name
Test status
Simulation time 209875589 ps
CPU time 0.72 seconds
Started Jun 04 12:52:14 PM PDT 24
Finished Jun 04 12:52:15 PM PDT 24
Peak memory 196772 kb
Host smart-3c6f6b52-8b93-4c7c-92ce-a7774aa0074f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424132952 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2424132952
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3214683000
Short name T811
Test name
Test status
Simulation time 21831985 ps
CPU time 1.09 seconds
Started Jun 04 12:52:03 PM PDT 24
Finished Jun 04 12:52:05 PM PDT 24
Peak memory 197896 kb
Host smart-1fe1e3c3-1c9f-44e4-ad16-733b19dd4ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214683000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3214683000
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2089235618
Short name T733
Test name
Test status
Simulation time 72822714 ps
CPU time 1.11 seconds
Started Jun 04 12:52:12 PM PDT 24
Finished Jun 04 12:52:14 PM PDT 24
Peak memory 197968 kb
Host smart-bf5e9ccc-7823-4900-a541-59d50dfe5c2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089235618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2089235618
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3936981966
Short name T754
Test name
Test status
Simulation time 36782250 ps
CPU time 1.78 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:30 PM PDT 24
Peak memory 198032 kb
Host smart-2748cc33-18a2-43ac-a259-336facccf94a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936981966 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3936981966
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3273548525
Short name T764
Test name
Test status
Simulation time 12726859 ps
CPU time 0.61 seconds
Started Jun 04 12:52:08 PM PDT 24
Finished Jun 04 12:52:10 PM PDT 24
Peak memory 194336 kb
Host smart-0d47d47e-1225-484c-9cbe-21ddfda16e73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273548525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3273548525
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.479518468
Short name T785
Test name
Test status
Simulation time 45586397 ps
CPU time 0.6 seconds
Started Jun 04 12:52:05 PM PDT 24
Finished Jun 04 12:52:07 PM PDT 24
Peak memory 193564 kb
Host smart-1f572e28-3340-4d54-b2b2-4d297ce140ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479518468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.479518468
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3448148066
Short name T72
Test name
Test status
Simulation time 64403145 ps
CPU time 0.86 seconds
Started Jun 04 12:52:05 PM PDT 24
Finished Jun 04 12:52:07 PM PDT 24
Peak memory 197596 kb
Host smart-7ce1e266-1969-472e-a286-1b97fa45e3c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448148066 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3448148066
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1640597043
Short name T812
Test name
Test status
Simulation time 105637633 ps
CPU time 2.4 seconds
Started Jun 04 12:52:04 PM PDT 24
Finished Jun 04 12:52:07 PM PDT 24
Peak memory 197908 kb
Host smart-194f66a6-949f-415c-a89a-89bbb326d85b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640597043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1640597043
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2497886549
Short name T748
Test name
Test status
Simulation time 106690561 ps
CPU time 0.91 seconds
Started Jun 04 12:52:11 PM PDT 24
Finished Jun 04 12:52:13 PM PDT 24
Peak memory 197504 kb
Host smart-4fea6abd-66e6-4d2b-8f29-788e1a6546f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497886549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2497886549
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1796659968
Short name T770
Test name
Test status
Simulation time 99825081 ps
CPU time 1.34 seconds
Started Jun 04 12:52:05 PM PDT 24
Finished Jun 04 12:52:07 PM PDT 24
Peak memory 197908 kb
Host smart-0914dbb4-4992-4345-b7dc-58bae2553271
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796659968 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1796659968
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4279771506
Short name T745
Test name
Test status
Simulation time 33661752 ps
CPU time 0.62 seconds
Started Jun 04 12:52:02 PM PDT 24
Finished Jun 04 12:52:03 PM PDT 24
Peak memory 195312 kb
Host smart-af3ea2bb-dde6-49fa-be8e-4dde2f6439e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279771506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.4279771506
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.322832658
Short name T760
Test name
Test status
Simulation time 12128530 ps
CPU time 0.58 seconds
Started Jun 04 12:52:10 PM PDT 24
Finished Jun 04 12:52:11 PM PDT 24
Peak memory 193612 kb
Host smart-535d8194-59d1-4105-8d63-e96b9553678e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322832658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.322832658
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1150233109
Short name T836
Test name
Test status
Simulation time 122562712 ps
CPU time 0.85 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:29 PM PDT 24
Peak memory 196164 kb
Host smart-5720ac38-f7ea-4645-a386-e43b98ee900b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150233109 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1150233109
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.4250659759
Short name T744
Test name
Test status
Simulation time 27814185 ps
CPU time 1.31 seconds
Started Jun 04 12:52:13 PM PDT 24
Finished Jun 04 12:52:15 PM PDT 24
Peak memory 197972 kb
Host smart-3d9d23ae-3ae6-40c5-ba75-c8c7a91b3f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250659759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.4250659759
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.489841888
Short name T104
Test name
Test status
Simulation time 462611470 ps
CPU time 1.22 seconds
Started Jun 04 12:52:08 PM PDT 24
Finished Jun 04 12:52:10 PM PDT 24
Peak memory 197840 kb
Host smart-12ffc82c-adad-4be3-a975-d55ca8a991b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489841888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.489841888
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.24523684
Short name T751
Test name
Test status
Simulation time 24837362 ps
CPU time 0.73 seconds
Started Jun 04 12:52:12 PM PDT 24
Finished Jun 04 12:52:14 PM PDT 24
Peak memory 197604 kb
Host smart-b03610e2-dd88-4537-8447-da3f4a4c90b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24523684 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.24523684
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1203703476
Short name T725
Test name
Test status
Simulation time 16636253 ps
CPU time 0.56 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:52:31 PM PDT 24
Peak memory 194524 kb
Host smart-59eeabfe-6137-4817-9ce0-5d5a1cc97a0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203703476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1203703476
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2064635844
Short name T728
Test name
Test status
Simulation time 45834138 ps
CPU time 0.63 seconds
Started Jun 04 12:52:15 PM PDT 24
Finished Jun 04 12:52:16 PM PDT 24
Peak memory 193580 kb
Host smart-fc4177c1-c32e-416d-9fde-c72bafd851e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064635844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2064635844
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2286753962
Short name T783
Test name
Test status
Simulation time 18739174 ps
CPU time 0.73 seconds
Started Jun 04 12:52:11 PM PDT 24
Finished Jun 04 12:52:13 PM PDT 24
Peak memory 196928 kb
Host smart-e2fc4c39-7cc8-4545-bd6f-9b7041ae6b38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286753962 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2286753962
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2758820618
Short name T735
Test name
Test status
Simulation time 96189108 ps
CPU time 1.89 seconds
Started Jun 04 12:52:12 PM PDT 24
Finished Jun 04 12:52:14 PM PDT 24
Peak memory 197844 kb
Host smart-399730f9-f36e-4a22-826f-978a0a80fc82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758820618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2758820618
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3903117177
Short name T43
Test name
Test status
Simulation time 83556377 ps
CPU time 1.16 seconds
Started Jun 04 12:52:16 PM PDT 24
Finished Jun 04 12:52:18 PM PDT 24
Peak memory 197968 kb
Host smart-ad0a74a0-4a8c-44d3-b1fa-9fd98d04fc3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903117177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3903117177
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2256109423
Short name T789
Test name
Test status
Simulation time 178783865 ps
CPU time 0.65 seconds
Started Jun 04 12:51:50 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 194648 kb
Host smart-b582aa8f-1fb0-4b59-9245-acbff4989b7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256109423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2256109423
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3004049579
Short name T827
Test name
Test status
Simulation time 93053422 ps
CPU time 1.43 seconds
Started Jun 04 12:51:52 PM PDT 24
Finished Jun 04 12:51:55 PM PDT 24
Peak memory 196248 kb
Host smart-2a5fd588-e738-4968-9e97-5c715771cb77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004049579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3004049579
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1351326010
Short name T794
Test name
Test status
Simulation time 77667787 ps
CPU time 0.57 seconds
Started Jun 04 12:51:43 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 194496 kb
Host smart-4c157ba5-3441-4c8c-9b6e-d42897bb8398
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351326010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1351326010
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1214000841
Short name T807
Test name
Test status
Simulation time 25698101 ps
CPU time 0.73 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:01 PM PDT 24
Peak memory 197716 kb
Host smart-bb59728d-329d-4aa1-9428-a3675064d881
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214000841 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1214000841
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1759460645
Short name T791
Test name
Test status
Simulation time 11308011 ps
CPU time 0.6 seconds
Started Jun 04 12:51:47 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 193232 kb
Host smart-2bbeff7c-aa07-4328-b305-53909d0ed5c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759460645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1759460645
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.107814
Short name T720
Test name
Test status
Simulation time 13275611 ps
CPU time 0.6 seconds
Started Jun 04 12:51:51 PM PDT 24
Finished Jun 04 12:51:53 PM PDT 24
Peak memory 194292 kb
Host smart-53e72344-097c-409f-948a-9124a8c0af63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.107814
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1354380187
Short name T87
Test name
Test status
Simulation time 402697371 ps
CPU time 0.91 seconds
Started Jun 04 12:51:49 PM PDT 24
Finished Jun 04 12:51:51 PM PDT 24
Peak memory 196276 kb
Host smart-6aa27676-58a2-4d37-817a-4fb2ac10229f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354380187 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1354380187
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.521364013
Short name T724
Test name
Test status
Simulation time 142506422 ps
CPU time 1.9 seconds
Started Jun 04 12:51:57 PM PDT 24
Finished Jun 04 12:52:01 PM PDT 24
Peak memory 197936 kb
Host smart-0e51014c-0c35-48b0-842f-5536f4dbcfbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521364013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.521364013
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1784715744
Short name T45
Test name
Test status
Simulation time 146155719 ps
CPU time 0.83 seconds
Started Jun 04 12:51:51 PM PDT 24
Finished Jun 04 12:51:53 PM PDT 24
Peak memory 197216 kb
Host smart-0792c0b3-9e4a-490f-b6c7-92d46b9778c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784715744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1784715744
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3975660237
Short name T788
Test name
Test status
Simulation time 37134401 ps
CPU time 0.59 seconds
Started Jun 04 12:52:11 PM PDT 24
Finished Jun 04 12:52:13 PM PDT 24
Peak memory 193536 kb
Host smart-d624127e-b69b-4171-a57d-b3858b8810ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975660237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3975660237
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.513273466
Short name T771
Test name
Test status
Simulation time 15226660 ps
CPU time 0.63 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:52:31 PM PDT 24
Peak memory 194280 kb
Host smart-fb93e9a3-9fa0-4eb9-ab5f-d5eccc88891a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513273466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.513273466
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.94915851
Short name T802
Test name
Test status
Simulation time 35102545 ps
CPU time 0.61 seconds
Started Jun 04 12:52:14 PM PDT 24
Finished Jun 04 12:52:16 PM PDT 24
Peak memory 194244 kb
Host smart-db04d002-a5c6-4a8a-92fa-f8ebb9aedd51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94915851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.94915851
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2965833670
Short name T804
Test name
Test status
Simulation time 17885868 ps
CPU time 0.6 seconds
Started Jun 04 12:52:21 PM PDT 24
Finished Jun 04 12:52:22 PM PDT 24
Peak memory 193528 kb
Host smart-9b908be8-feab-45c1-b954-70de09baa777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965833670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2965833670
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.4192987069
Short name T721
Test name
Test status
Simulation time 14972424 ps
CPU time 0.63 seconds
Started Jun 04 12:52:22 PM PDT 24
Finished Jun 04 12:52:24 PM PDT 24
Peak memory 194228 kb
Host smart-933801e8-f70e-4c94-a2f1-7c7ac800fc29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192987069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.4192987069
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.74443626
Short name T738
Test name
Test status
Simulation time 13271220 ps
CPU time 0.56 seconds
Started Jun 04 12:52:12 PM PDT 24
Finished Jun 04 12:52:14 PM PDT 24
Peak memory 193592 kb
Host smart-83d9eea8-4e20-476f-8f04-c52c11865d1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74443626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.74443626
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3333529945
Short name T830
Test name
Test status
Simulation time 43333845 ps
CPU time 0.61 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:29 PM PDT 24
Peak memory 193544 kb
Host smart-8419b980-8d50-4f9b-8841-e3e796eefae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333529945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3333529945
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3044830598
Short name T739
Test name
Test status
Simulation time 11021452 ps
CPU time 0.56 seconds
Started Jun 04 12:52:13 PM PDT 24
Finished Jun 04 12:52:15 PM PDT 24
Peak memory 193528 kb
Host smart-5610a145-1bd5-48a1-89a1-18b208bd94cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044830598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3044830598
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1188634460
Short name T755
Test name
Test status
Simulation time 53076682 ps
CPU time 0.62 seconds
Started Jun 04 12:52:18 PM PDT 24
Finished Jun 04 12:52:20 PM PDT 24
Peak memory 193528 kb
Host smart-9d585af8-245f-4da9-99ed-a7cc6d2ab3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188634460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1188634460
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3535793991
Short name T749
Test name
Test status
Simulation time 19762029 ps
CPU time 0.64 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:52:32 PM PDT 24
Peak memory 193644 kb
Host smart-dd07da1c-f58c-4b85-9e14-458108f54818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535793991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3535793991
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.449672061
Short name T68
Test name
Test status
Simulation time 15010668 ps
CPU time 0.67 seconds
Started Jun 04 12:51:53 PM PDT 24
Finished Jun 04 12:51:54 PM PDT 24
Peak memory 194736 kb
Host smart-021b3e61-160b-468e-a166-3d5f32bdbf5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449672061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.449672061
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3285796510
Short name T83
Test name
Test status
Simulation time 742506895 ps
CPU time 3.37 seconds
Started Jun 04 12:51:54 PM PDT 24
Finished Jun 04 12:51:59 PM PDT 24
Peak memory 197816 kb
Host smart-275fb48e-b573-4631-958d-b53a2c4fabbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285796510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3285796510
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3626549081
Short name T73
Test name
Test status
Simulation time 42972723 ps
CPU time 0.63 seconds
Started Jun 04 12:51:57 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 194640 kb
Host smart-1dd99987-2b3f-40b0-b229-320cef3f8cf6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626549081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3626549081
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3450553772
Short name T817
Test name
Test status
Simulation time 35501611 ps
CPU time 0.91 seconds
Started Jun 04 12:51:51 PM PDT 24
Finished Jun 04 12:51:53 PM PDT 24
Peak memory 197768 kb
Host smart-f437f0b6-ac6f-4c4b-aa80-83206d34b2c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450553772 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3450553772
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3479823728
Short name T69
Test name
Test status
Simulation time 24597915 ps
CPU time 0.64 seconds
Started Jun 04 12:51:50 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 195360 kb
Host smart-d64084d0-54e6-4127-b88f-c6e33c4421ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479823728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3479823728
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1205481139
Short name T818
Test name
Test status
Simulation time 32379047 ps
CPU time 0.63 seconds
Started Jun 04 12:52:01 PM PDT 24
Finished Jun 04 12:52:03 PM PDT 24
Peak memory 193540 kb
Host smart-653fc6c6-61fe-4704-8f34-9c8767e3edfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205481139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1205481139
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3753263215
Short name T782
Test name
Test status
Simulation time 19766035 ps
CPU time 0.87 seconds
Started Jun 04 12:51:52 PM PDT 24
Finished Jun 04 12:51:55 PM PDT 24
Peak memory 196096 kb
Host smart-124c5121-6638-4eb1-9262-c18d5afaca80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753263215 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3753263215
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3457224631
Short name T834
Test name
Test status
Simulation time 140807874 ps
CPU time 1.76 seconds
Started Jun 04 12:51:59 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 197908 kb
Host smart-60937cd2-17f4-4fb2-b3c7-6f2fd15d69a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457224631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3457224631
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.876064772
Short name T44
Test name
Test status
Simulation time 129178046 ps
CPU time 1.39 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:01 PM PDT 24
Peak memory 197904 kb
Host smart-1b446b5b-ec98-439d-9466-7148a4b3deeb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876064772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.876064772
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2489356966
Short name T732
Test name
Test status
Simulation time 63408974 ps
CPU time 0.6 seconds
Started Jun 04 12:52:14 PM PDT 24
Finished Jun 04 12:52:16 PM PDT 24
Peak memory 193584 kb
Host smart-3e1599e1-4eef-4025-996d-a51b67f6c46f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489356966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2489356966
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.4044990135
Short name T718
Test name
Test status
Simulation time 43862872 ps
CPU time 0.56 seconds
Started Jun 04 12:52:13 PM PDT 24
Finished Jun 04 12:52:15 PM PDT 24
Peak memory 193556 kb
Host smart-ee2472f9-67e5-42bf-a287-e730d0529c6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044990135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.4044990135
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2254189713
Short name T784
Test name
Test status
Simulation time 43268992 ps
CPU time 0.65 seconds
Started Jun 04 12:52:14 PM PDT 24
Finished Jun 04 12:52:15 PM PDT 24
Peak memory 193636 kb
Host smart-0b5d2928-48a6-4c9d-9f63-b5a9873f7070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254189713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2254189713
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.237972202
Short name T719
Test name
Test status
Simulation time 13224847 ps
CPU time 0.71 seconds
Started Jun 04 12:52:19 PM PDT 24
Finished Jun 04 12:52:20 PM PDT 24
Peak memory 194208 kb
Host smart-095eee9f-a118-4a77-a4d5-835c153fb42b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237972202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.237972202
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3416415534
Short name T722
Test name
Test status
Simulation time 37196367 ps
CPU time 0.69 seconds
Started Jun 04 12:52:18 PM PDT 24
Finished Jun 04 12:52:19 PM PDT 24
Peak memory 193684 kb
Host smart-374a93f8-b114-4950-9665-9a1dbea8c192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416415534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3416415534
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2835707078
Short name T768
Test name
Test status
Simulation time 15457075 ps
CPU time 0.55 seconds
Started Jun 04 12:52:14 PM PDT 24
Finished Jun 04 12:52:15 PM PDT 24
Peak memory 193564 kb
Host smart-af0350e7-7dae-4af0-8792-9487e4d41fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835707078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2835707078
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.276028689
Short name T767
Test name
Test status
Simulation time 14735844 ps
CPU time 0.57 seconds
Started Jun 04 12:52:12 PM PDT 24
Finished Jun 04 12:52:14 PM PDT 24
Peak memory 193552 kb
Host smart-20505756-adef-45da-b4b0-a4ba4c5c9aff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276028689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.276028689
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1813942696
Short name T774
Test name
Test status
Simulation time 14127461 ps
CPU time 0.6 seconds
Started Jun 04 12:52:12 PM PDT 24
Finished Jun 04 12:52:13 PM PDT 24
Peak memory 194264 kb
Host smart-7168d3cb-c102-4cf9-b5ca-d8f73ca4047b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813942696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1813942696
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1595299760
Short name T729
Test name
Test status
Simulation time 13855649 ps
CPU time 0.57 seconds
Started Jun 04 12:52:28 PM PDT 24
Finished Jun 04 12:52:30 PM PDT 24
Peak memory 194232 kb
Host smart-eab973dd-08b3-42ab-93f2-e933c8570223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595299760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1595299760
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2501858925
Short name T824
Test name
Test status
Simulation time 27694112 ps
CPU time 0.57 seconds
Started Jun 04 12:52:13 PM PDT 24
Finished Jun 04 12:52:14 PM PDT 24
Peak memory 193508 kb
Host smart-49c7f1a0-7f94-425f-bf21-76f51319bf43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501858925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2501858925
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3204284890
Short name T805
Test name
Test status
Simulation time 165172529 ps
CPU time 0.78 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 196172 kb
Host smart-4f30ab7c-74fd-42b1-b910-068515e813d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204284890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3204284890
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2951975358
Short name T828
Test name
Test status
Simulation time 384436535 ps
CPU time 3.35 seconds
Started Jun 04 12:52:01 PM PDT 24
Finished Jun 04 12:52:05 PM PDT 24
Peak memory 196560 kb
Host smart-d65ec85e-4ca5-4652-b8c5-1722b6cda161
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951975358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2951975358
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2893428829
Short name T74
Test name
Test status
Simulation time 152510396 ps
CPU time 0.64 seconds
Started Jun 04 12:52:02 PM PDT 24
Finished Jun 04 12:52:03 PM PDT 24
Peak memory 194888 kb
Host smart-a95947e4-31d2-4bf6-a430-18298b245f38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893428829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2893428829
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3377673816
Short name T753
Test name
Test status
Simulation time 180347658 ps
CPU time 1.22 seconds
Started Jun 04 12:51:57 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 197892 kb
Host smart-111e3c53-83eb-45dc-a599-8f3ffac8adda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377673816 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3377673816
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3318854657
Short name T790
Test name
Test status
Simulation time 13969400 ps
CPU time 0.55 seconds
Started Jun 04 12:51:56 PM PDT 24
Finished Jun 04 12:51:58 PM PDT 24
Peak memory 193204 kb
Host smart-916acea1-696f-4bf9-a4c2-339990dff63b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318854657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3318854657
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.938240084
Short name T759
Test name
Test status
Simulation time 15498852 ps
CPU time 0.56 seconds
Started Jun 04 12:51:56 PM PDT 24
Finished Jun 04 12:51:59 PM PDT 24
Peak memory 194284 kb
Host smart-9cdc2f8c-1a1e-426c-9d0d-d0925e6ca72b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938240084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.938240084
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3484457291
Short name T89
Test name
Test status
Simulation time 92620763 ps
CPU time 0.72 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:01 PM PDT 24
Peak memory 195952 kb
Host smart-70b0fa0b-6510-4dda-8a1b-3d798b999e81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484457291 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3484457291
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.536902902
Short name T743
Test name
Test status
Simulation time 324847887 ps
CPU time 2.73 seconds
Started Jun 04 12:51:56 PM PDT 24
Finished Jun 04 12:52:01 PM PDT 24
Peak memory 197952 kb
Host smart-c344f780-ecbb-4c05-9372-c94c41ea019a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536902902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.536902902
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.286424481
Short name T838
Test name
Test status
Simulation time 43977462 ps
CPU time 0.83 seconds
Started Jun 04 12:51:56 PM PDT 24
Finished Jun 04 12:51:58 PM PDT 24
Peak memory 196844 kb
Host smart-6b09d5ac-a07f-4a0b-bed5-b2ff46f8f672
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286424481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.286424481
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3572640631
Short name T746
Test name
Test status
Simulation time 12683832 ps
CPU time 0.61 seconds
Started Jun 04 12:52:15 PM PDT 24
Finished Jun 04 12:52:16 PM PDT 24
Peak memory 193620 kb
Host smart-1a6b9d6e-f1ea-4e3e-aff4-8b07d34d9cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572640631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3572640631
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1020843465
Short name T742
Test name
Test status
Simulation time 44652151 ps
CPU time 0.59 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:52:34 PM PDT 24
Peak memory 193572 kb
Host smart-9dcf1f28-6896-4b99-aada-11c01979cbfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020843465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1020843465
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.639211642
Short name T843
Test name
Test status
Simulation time 13258557 ps
CPU time 0.61 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:28 PM PDT 24
Peak memory 193652 kb
Host smart-fc8e01d8-e922-473d-8586-deaa7e5f9035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639211642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.639211642
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.439714350
Short name T758
Test name
Test status
Simulation time 18482471 ps
CPU time 0.61 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:29 PM PDT 24
Peak memory 193512 kb
Host smart-1bbaf94e-04ae-4194-90ec-ffb910aee9ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439714350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.439714350
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3005531116
Short name T831
Test name
Test status
Simulation time 55461444 ps
CPU time 0.58 seconds
Started Jun 04 12:52:25 PM PDT 24
Finished Jun 04 12:52:27 PM PDT 24
Peak memory 193568 kb
Host smart-9f3758fc-8769-48a1-b031-b17e9a07d4ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005531116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3005531116
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1879191099
Short name T723
Test name
Test status
Simulation time 14777268 ps
CPU time 0.59 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:52:31 PM PDT 24
Peak memory 193560 kb
Host smart-43a8210c-3b6b-47e7-9827-82a5ee3dd52a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879191099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1879191099
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2229984884
Short name T750
Test name
Test status
Simulation time 29477362 ps
CPU time 0.57 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:52:33 PM PDT 24
Peak memory 193608 kb
Host smart-6b64c340-6ce8-4f5d-a26a-03017105b323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229984884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2229984884
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3059414735
Short name T740
Test name
Test status
Simulation time 13873779 ps
CPU time 0.6 seconds
Started Jun 04 12:52:16 PM PDT 24
Finished Jun 04 12:52:17 PM PDT 24
Peak memory 193432 kb
Host smart-135e7986-0f63-42c1-a82b-bd9a93707919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059414735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3059414735
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3544988467
Short name T813
Test name
Test status
Simulation time 13869522 ps
CPU time 0.6 seconds
Started Jun 04 12:52:16 PM PDT 24
Finished Jun 04 12:52:17 PM PDT 24
Peak memory 193536 kb
Host smart-1ce2d7a6-435f-4062-97cb-247b5470ad34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544988467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3544988467
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.327036583
Short name T762
Test name
Test status
Simulation time 67515760 ps
CPU time 0.62 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:52:32 PM PDT 24
Peak memory 193572 kb
Host smart-9430dbc6-2023-49b2-8a46-6f8fdb002eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327036583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.327036583
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3814689773
Short name T840
Test name
Test status
Simulation time 37492040 ps
CPU time 1 seconds
Started Jun 04 12:51:57 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 197904 kb
Host smart-9215052e-3f75-4ff7-a926-7f0be9065630
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814689773 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3814689773
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1413691605
Short name T102
Test name
Test status
Simulation time 14198076 ps
CPU time 0.63 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:51:56 PM PDT 24
Peak memory 194636 kb
Host smart-b7863599-887b-40b7-9795-08202727721c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413691605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1413691605
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3927414245
Short name T823
Test name
Test status
Simulation time 18659912 ps
CPU time 0.64 seconds
Started Jun 04 12:51:59 PM PDT 24
Finished Jun 04 12:52:01 PM PDT 24
Peak memory 194308 kb
Host smart-f343c4b1-61ee-44bb-8f90-cb9134aa6e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927414245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3927414245
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.193040966
Short name T803
Test name
Test status
Simulation time 143835890 ps
CPU time 0.92 seconds
Started Jun 04 12:51:57 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 197856 kb
Host smart-f782d333-9981-4651-9081-3818ac9c36dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193040966 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.193040966
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2402296279
Short name T741
Test name
Test status
Simulation time 346400343 ps
CPU time 2.07 seconds
Started Jun 04 12:52:00 PM PDT 24
Finished Jun 04 12:52:03 PM PDT 24
Peak memory 197924 kb
Host smart-b13c3221-3088-4822-aab5-b65f84ae3751
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402296279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2402296279
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.742680517
Short name T799
Test name
Test status
Simulation time 420781180 ps
CPU time 1.56 seconds
Started Jun 04 12:51:56 PM PDT 24
Finished Jun 04 12:51:59 PM PDT 24
Peak memory 197772 kb
Host smart-3bc0b7da-1ebc-40ce-8291-3299d101a8ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742680517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.742680517
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1284052148
Short name T809
Test name
Test status
Simulation time 404288879 ps
CPU time 0.89 seconds
Started Jun 04 12:52:01 PM PDT 24
Finished Jun 04 12:52:03 PM PDT 24
Peak memory 197880 kb
Host smart-eccbc194-07e2-4b14-a344-f2308c193c08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284052148 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1284052148
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2392321302
Short name T776
Test name
Test status
Simulation time 13530682 ps
CPU time 0.6 seconds
Started Jun 04 12:51:53 PM PDT 24
Finished Jun 04 12:51:55 PM PDT 24
Peak memory 194600 kb
Host smart-db146191-7b7c-4b8b-883e-baaa65e757e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392321302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2392321302
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.637099616
Short name T747
Test name
Test status
Simulation time 29494328 ps
CPU time 0.6 seconds
Started Jun 04 12:51:54 PM PDT 24
Finished Jun 04 12:51:56 PM PDT 24
Peak memory 193588 kb
Host smart-5e8cbbfd-1429-4034-8393-6421d029ec5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637099616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.637099616
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.91159613
Short name T775
Test name
Test status
Simulation time 35618228 ps
CPU time 0.87 seconds
Started Jun 04 12:52:01 PM PDT 24
Finished Jun 04 12:52:03 PM PDT 24
Peak memory 196820 kb
Host smart-2d503a5e-2ca5-4a96-a5c7-c53a8eb99689
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91159613 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.gpio_same_csr_outstanding.91159613
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3370154047
Short name T826
Test name
Test status
Simulation time 91451267 ps
CPU time 1.79 seconds
Started Jun 04 12:51:56 PM PDT 24
Finished Jun 04 12:51:59 PM PDT 24
Peak memory 197980 kb
Host smart-b5bf12a2-c43b-42dc-b1a0-99e73c195883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370154047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3370154047
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2550871587
Short name T814
Test name
Test status
Simulation time 32895142 ps
CPU time 0.93 seconds
Started Jun 04 12:51:57 PM PDT 24
Finished Jun 04 12:51:59 PM PDT 24
Peak memory 197776 kb
Host smart-029dfd5a-f6aa-464c-958b-b67dc0b6983b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550871587 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2550871587
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1846796962
Short name T773
Test name
Test status
Simulation time 41953579 ps
CPU time 0.55 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 193116 kb
Host smart-b13a0ca3-a163-476d-ac85-8557c7ecdb65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846796962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1846796962
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.34862160
Short name T766
Test name
Test status
Simulation time 48562894 ps
CPU time 0.58 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 193584 kb
Host smart-85041328-68ed-439f-a320-8b1a9a70e7ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34862160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.34862160
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2151111922
Short name T77
Test name
Test status
Simulation time 122233446 ps
CPU time 0.65 seconds
Started Jun 04 12:52:00 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 194856 kb
Host smart-3d617489-6afa-438b-bda6-c32f5abdb4e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151111922 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2151111922
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2799226143
Short name T820
Test name
Test status
Simulation time 531054792 ps
CPU time 2.69 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:03 PM PDT 24
Peak memory 197996 kb
Host smart-52e8c5a1-2629-42c3-969f-94a68730731b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799226143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2799226143
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2049385072
Short name T845
Test name
Test status
Simulation time 235245780 ps
CPU time 1.4 seconds
Started Jun 04 12:51:54 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 197944 kb
Host smart-3f0d0a69-0d94-4574-bd79-b520a4f46d05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049385072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2049385072
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.627629092
Short name T822
Test name
Test status
Simulation time 179947349 ps
CPU time 1.05 seconds
Started Jun 04 12:52:00 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 197852 kb
Host smart-da310326-2054-480a-8f0b-c916f6431aac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627629092 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.627629092
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2290163301
Short name T75
Test name
Test status
Simulation time 42519299 ps
CPU time 0.59 seconds
Started Jun 04 12:52:01 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 193808 kb
Host smart-b45a6978-edd8-4f73-9e5c-31ff893db76f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290163301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2290163301
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2170912216
Short name T837
Test name
Test status
Simulation time 14052597 ps
CPU time 0.59 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 193528 kb
Host smart-06ee0f1c-999c-4eeb-b875-63f8e8604778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170912216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2170912216
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3627878114
Short name T70
Test name
Test status
Simulation time 43283795 ps
CPU time 0.75 seconds
Started Jun 04 12:51:57 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 196464 kb
Host smart-f0a15062-2504-417a-bc13-06af02f4776b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627878114 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3627878114
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3030278966
Short name T756
Test name
Test status
Simulation time 43627429 ps
CPU time 2.15 seconds
Started Jun 04 12:51:57 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 197928 kb
Host smart-06264682-26fd-4a7e-8669-a00c5c5cdc15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030278966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3030278966
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1090571643
Short name T34
Test name
Test status
Simulation time 259400917 ps
CPU time 1.16 seconds
Started Jun 04 12:51:56 PM PDT 24
Finished Jun 04 12:51:58 PM PDT 24
Peak memory 197848 kb
Host smart-1862069f-24db-4a77-afb9-32400fbbe5f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090571643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1090571643
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2642382844
Short name T726
Test name
Test status
Simulation time 34899310 ps
CPU time 0.76 seconds
Started Jun 04 12:52:00 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 197492 kb
Host smart-5fc5cf0a-e413-491b-974b-5367868d634a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642382844 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2642382844
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3196951800
Short name T736
Test name
Test status
Simulation time 33832428 ps
CPU time 0.61 seconds
Started Jun 04 12:52:00 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 194472 kb
Host smart-7750689f-0d5d-4017-9f34-b7de7786dea6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196951800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3196951800
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.4255715822
Short name T769
Test name
Test status
Simulation time 10488486 ps
CPU time 0.6 seconds
Started Jun 04 12:52:00 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 193560 kb
Host smart-92929c39-2fea-4dfd-9aac-3fdbacc50c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255715822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.4255715822
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3607877663
Short name T84
Test name
Test status
Simulation time 30955347 ps
CPU time 0.81 seconds
Started Jun 04 12:52:00 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 196740 kb
Host smart-4b68c866-4244-48c0-bee4-e2f93a6dea66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607877663 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3607877663
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.901725623
Short name T731
Test name
Test status
Simulation time 119555595 ps
CPU time 1.48 seconds
Started Jun 04 12:51:56 PM PDT 24
Finished Jun 04 12:51:59 PM PDT 24
Peak memory 197936 kb
Host smart-55631509-22e3-4d61-b3e0-dd4b720024b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901725623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.901725623
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3360752107
Short name T808
Test name
Test status
Simulation time 505011208 ps
CPU time 1.52 seconds
Started Jun 04 12:52:00 PM PDT 24
Finished Jun 04 12:52:03 PM PDT 24
Peak memory 197896 kb
Host smart-ebd91c5c-6bcd-4bbf-934f-c44f1471a1e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360752107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3360752107
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1211437390
Short name T252
Test name
Test status
Simulation time 12383958 ps
CPU time 0.55 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:24:44 PM PDT 24
Peak memory 193728 kb
Host smart-a98c5f4d-b4d5-4702-86ff-250f5000d5fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211437390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1211437390
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1601594656
Short name T148
Test name
Test status
Simulation time 14219482 ps
CPU time 0.62 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:24:41 PM PDT 24
Peak memory 193772 kb
Host smart-7f81973c-3e5b-4e9e-a1fd-5acd86398d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601594656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1601594656
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3405116390
Short name T487
Test name
Test status
Simulation time 211682964 ps
CPU time 6.22 seconds
Started Jun 04 12:24:44 PM PDT 24
Finished Jun 04 12:24:52 PM PDT 24
Peak memory 196100 kb
Host smart-cc334320-3927-4f60-86b6-b797a1ca633a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405116390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3405116390
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3326356248
Short name T622
Test name
Test status
Simulation time 70392207 ps
CPU time 0.87 seconds
Started Jun 04 12:24:41 PM PDT 24
Finished Jun 04 12:24:45 PM PDT 24
Peak memory 197228 kb
Host smart-c752bd9a-8a6c-46e9-b48a-371052dcd300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326356248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3326356248
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2712916070
Short name T231
Test name
Test status
Simulation time 62813147 ps
CPU time 0.73 seconds
Started Jun 04 12:25:46 PM PDT 24
Finished Jun 04 12:25:49 PM PDT 24
Peak memory 194884 kb
Host smart-6bd49048-a616-4eb5-8815-b182590566ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712916070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2712916070
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2306969591
Short name T250
Test name
Test status
Simulation time 238663474 ps
CPU time 2.28 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:24:45 PM PDT 24
Peak memory 197880 kb
Host smart-bef3ee83-36c0-4ad9-89aa-e18068e9b237
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306969591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2306969591
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.268013709
Short name T300
Test name
Test status
Simulation time 202048698 ps
CPU time 1.67 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:24:44 PM PDT 24
Peak memory 196096 kb
Host smart-0a197afa-5d2b-481b-9092-c24959c8f2a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268013709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.268013709
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.720465760
Short name T257
Test name
Test status
Simulation time 106143082 ps
CPU time 1.1 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:24:50 PM PDT 24
Peak memory 196748 kb
Host smart-a313ddd5-98d8-4413-af3d-be73fee6a547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720465760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.720465760
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.5451005
Short name T605
Test name
Test status
Simulation time 118122285 ps
CPU time 1.06 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:24:41 PM PDT 24
Peak memory 195636 kb
Host smart-ee33937a-db2c-4400-8883-2740f0279659
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5451005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_pu
lldown.5451005
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2080829590
Short name T427
Test name
Test status
Simulation time 447275406 ps
CPU time 5.03 seconds
Started Jun 04 12:25:46 PM PDT 24
Finished Jun 04 12:25:53 PM PDT 24
Peak memory 196264 kb
Host smart-48ea6b46-8195-4174-ab59-4cfd839bcf73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080829590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2080829590
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1730202683
Short name T275
Test name
Test status
Simulation time 330410824 ps
CPU time 1.1 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:24:43 PM PDT 24
Peak memory 195408 kb
Host smart-79dec68d-c3fb-4de4-bb77-20c2a6c00f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730202683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1730202683
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.532796528
Short name T424
Test name
Test status
Simulation time 75651043 ps
CPU time 0.93 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:24:42 PM PDT 24
Peak memory 195400 kb
Host smart-f28fd146-a374-414f-8705-48078ef2265f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532796528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.532796528
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1576632246
Short name T628
Test name
Test status
Simulation time 18718121937 ps
CPU time 29.41 seconds
Started Jun 04 12:24:44 PM PDT 24
Finished Jun 04 12:25:15 PM PDT 24
Peak memory 197948 kb
Host smart-a3dd0bd1-e4d8-412c-a059-be094a937fa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576632246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1576632246
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3807534044
Short name T100
Test name
Test status
Simulation time 251926644984 ps
CPU time 1585.21 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:51:05 PM PDT 24
Peak memory 198036 kb
Host smart-c839ba60-67f1-434a-8d6f-11180f410e89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3807534044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3807534044
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2989373363
Short name T693
Test name
Test status
Simulation time 15797065 ps
CPU time 0.57 seconds
Started Jun 04 12:24:43 PM PDT 24
Finished Jun 04 12:24:46 PM PDT 24
Peak memory 192600 kb
Host smart-5581c938-e7b9-4903-9cde-c35d475bda57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989373363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2989373363
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2711286901
Short name T501
Test name
Test status
Simulation time 51426805 ps
CPU time 0.62 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:24:39 PM PDT 24
Peak memory 193960 kb
Host smart-c6514406-a4d2-4fb9-9318-7fe714d2cc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711286901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2711286901
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1263744392
Short name T439
Test name
Test status
Simulation time 567402012 ps
CPU time 7.74 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:24:50 PM PDT 24
Peak memory 195976 kb
Host smart-565452aa-5047-4621-963f-c2901050e89d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263744392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1263744392
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3321539574
Short name T683
Test name
Test status
Simulation time 32588371 ps
CPU time 0.66 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:24:44 PM PDT 24
Peak memory 194584 kb
Host smart-2fd62f32-cdac-4cd4-be5a-5b430f474868
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321539574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3321539574
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1288460019
Short name T640
Test name
Test status
Simulation time 66508195 ps
CPU time 0.96 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:24:37 PM PDT 24
Peak memory 195860 kb
Host smart-95caff84-b4ea-4a16-b629-a17716d4d1ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288460019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1288460019
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1061222208
Short name T134
Test name
Test status
Simulation time 121486112 ps
CPU time 2.14 seconds
Started Jun 04 12:26:00 PM PDT 24
Finished Jun 04 12:26:04 PM PDT 24
Peak memory 196256 kb
Host smart-e1bdf25e-702e-4473-95fe-71ab83f9ca22
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061222208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1061222208
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2224276000
Short name T188
Test name
Test status
Simulation time 204406983 ps
CPU time 1.37 seconds
Started Jun 04 12:25:46 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 195116 kb
Host smart-df45c908-4ef8-4ad9-a1cc-3afbc9eaf738
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224276000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2224276000
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2732854408
Short name T221
Test name
Test status
Simulation time 142837450 ps
CPU time 1.14 seconds
Started Jun 04 12:24:43 PM PDT 24
Finished Jun 04 12:24:46 PM PDT 24
Peak memory 195712 kb
Host smart-2d89a82d-f121-49e9-8a42-1afb776e47ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732854408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2732854408
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.353246025
Short name T667
Test name
Test status
Simulation time 22061422 ps
CPU time 0.77 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:24:40 PM PDT 24
Peak memory 196420 kb
Host smart-87404836-a541-4eaf-97c0-6d746e7cd9b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353246025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.353246025
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3854683011
Short name T572
Test name
Test status
Simulation time 344109895 ps
CPU time 3.83 seconds
Started Jun 04 12:26:00 PM PDT 24
Finished Jun 04 12:26:06 PM PDT 24
Peak memory 197772 kb
Host smart-64875ca8-8697-492e-a5db-53d7f0c31b9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854683011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3854683011
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3905913950
Short name T37
Test name
Test status
Simulation time 64456283 ps
CPU time 0.74 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:24:44 PM PDT 24
Peak memory 213456 kb
Host smart-40c2cc03-ca2b-4f6f-9438-eafc09eb6a53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905913950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3905913950
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.82704155
Short name T93
Test name
Test status
Simulation time 44789284 ps
CPU time 1.21 seconds
Started Jun 04 12:24:47 PM PDT 24
Finished Jun 04 12:24:50 PM PDT 24
Peak memory 196568 kb
Host smart-0c58e657-8f15-4c39-8df7-a35e3832783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82704155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.82704155
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2531907009
Short name T532
Test name
Test status
Simulation time 146985314 ps
CPU time 1.31 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:24:43 PM PDT 24
Peak memory 196540 kb
Host smart-fa744df1-fefe-4c63-b53d-4af439cd85c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531907009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2531907009
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2237622717
Short name T371
Test name
Test status
Simulation time 6532462107 ps
CPU time 159.9 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:27:22 PM PDT 24
Peak memory 197988 kb
Host smart-a0c3d0f8-21f4-4da7-b695-7a81c2d9ae80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237622717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2237622717
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2759339838
Short name T323
Test name
Test status
Simulation time 42507895 ps
CPU time 0.57 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 194568 kb
Host smart-0a45956b-0e13-4c98-9456-0db1eade9c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759339838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2759339838
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.743067002
Short name T510
Test name
Test status
Simulation time 24760375 ps
CPU time 0.73 seconds
Started Jun 04 12:25:03 PM PDT 24
Finished Jun 04 12:25:05 PM PDT 24
Peak memory 196012 kb
Host smart-d3912ffa-37e4-443d-b3af-9dfe685c5185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743067002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.743067002
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1501645305
Short name T359
Test name
Test status
Simulation time 962370160 ps
CPU time 6.79 seconds
Started Jun 04 12:26:07 PM PDT 24
Finished Jun 04 12:26:16 PM PDT 24
Peak memory 197760 kb
Host smart-efc785a0-7801-4f86-bbb0-e4f0c6d2e461
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501645305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1501645305
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3177030066
Short name T241
Test name
Test status
Simulation time 22993340 ps
CPU time 0.6 seconds
Started Jun 04 12:25:05 PM PDT 24
Finished Jun 04 12:25:07 PM PDT 24
Peak memory 194508 kb
Host smart-9ecf9ea0-c91c-4901-af25-b6a3326e7c5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177030066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3177030066
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2457530807
Short name T133
Test name
Test status
Simulation time 228717583 ps
CPU time 1.01 seconds
Started Jun 04 12:25:00 PM PDT 24
Finished Jun 04 12:25:01 PM PDT 24
Peak memory 195812 kb
Host smart-8b6e15ca-c30f-4e42-bf04-b3c6f2e54bb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457530807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2457530807
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1269293842
Short name T594
Test name
Test status
Simulation time 73261862 ps
CPU time 1.4 seconds
Started Jun 04 12:24:55 PM PDT 24
Finished Jun 04 12:24:57 PM PDT 24
Peak memory 196716 kb
Host smart-9b0c13fb-351c-4c7a-b4ea-35d5b46ebed3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269293842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1269293842
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3813222
Short name T398
Test name
Test status
Simulation time 577719691 ps
CPU time 2.94 seconds
Started Jun 04 12:25:00 PM PDT 24
Finished Jun 04 12:25:03 PM PDT 24
Peak memory 196888 kb
Host smart-e0ff6d39-5e7f-4f82-8d98-6cbde48c54bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.3813222
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3436436384
Short name T362
Test name
Test status
Simulation time 79057400 ps
CPU time 0.83 seconds
Started Jun 04 12:25:04 PM PDT 24
Finished Jun 04 12:25:07 PM PDT 24
Peak memory 195664 kb
Host smart-44f0b3cf-6d56-4a81-aeeb-5e091b40b58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436436384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3436436384
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3651838518
Short name T363
Test name
Test status
Simulation time 210238559 ps
CPU time 0.83 seconds
Started Jun 04 12:26:07 PM PDT 24
Finished Jun 04 12:26:10 PM PDT 24
Peak memory 196372 kb
Host smart-178adc55-8c51-4af3-8c24-fc9fed16cb0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651838518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3651838518
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1827420189
Short name T417
Test name
Test status
Simulation time 116495334 ps
CPU time 4.66 seconds
Started Jun 04 12:24:57 PM PDT 24
Finished Jun 04 12:25:03 PM PDT 24
Peak memory 197684 kb
Host smart-2960d171-07ee-4039-99d6-ec60a1e2ae40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827420189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1827420189
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1292047943
Short name T688
Test name
Test status
Simulation time 45216204 ps
CPU time 0.74 seconds
Started Jun 04 12:26:07 PM PDT 24
Finished Jun 04 12:26:10 PM PDT 24
Peak memory 195732 kb
Host smart-60c59605-91fb-434c-aeaa-8fba83b0aeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292047943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1292047943
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3727833837
Short name T479
Test name
Test status
Simulation time 87746273 ps
CPU time 1.13 seconds
Started Jun 04 12:25:01 PM PDT 24
Finished Jun 04 12:25:03 PM PDT 24
Peak memory 195576 kb
Host smart-d68028ef-6932-4ad3-83f6-d99cc92353eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727833837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3727833837
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1899752361
Short name T98
Test name
Test status
Simulation time 8093053582 ps
CPU time 95.25 seconds
Started Jun 04 12:24:47 PM PDT 24
Finished Jun 04 12:26:24 PM PDT 24
Peak memory 198008 kb
Host smart-8a465af4-3664-4650-8398-31681dd88a95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899752361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1899752361
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3819798956
Short name T304
Test name
Test status
Simulation time 12992529 ps
CPU time 0.55 seconds
Started Jun 04 12:25:02 PM PDT 24
Finished Jun 04 12:25:04 PM PDT 24
Peak memory 193752 kb
Host smart-8b72f9ea-668e-4faa-8a64-bc176090bff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819798956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3819798956
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3503127729
Short name T598
Test name
Test status
Simulation time 33932063 ps
CPU time 0.78 seconds
Started Jun 04 12:25:05 PM PDT 24
Finished Jun 04 12:25:07 PM PDT 24
Peak memory 196032 kb
Host smart-e64cabea-5af9-44fd-8cb8-222cbbc69d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503127729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3503127729
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3017427458
Short name T230
Test name
Test status
Simulation time 1578540236 ps
CPU time 20.01 seconds
Started Jun 04 12:24:56 PM PDT 24
Finished Jun 04 12:25:17 PM PDT 24
Peak memory 196664 kb
Host smart-eaf3fbfe-cc73-4e7d-9320-345f9be25c21
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017427458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3017427458
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1705123894
Short name T528
Test name
Test status
Simulation time 56665943 ps
CPU time 0.68 seconds
Started Jun 04 12:25:06 PM PDT 24
Finished Jun 04 12:25:08 PM PDT 24
Peak memory 194680 kb
Host smart-72c9ee76-cb73-4816-ab22-41d630b7da8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705123894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1705123894
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.953891075
Short name T716
Test name
Test status
Simulation time 486343943 ps
CPU time 1.16 seconds
Started Jun 04 12:25:01 PM PDT 24
Finished Jun 04 12:25:03 PM PDT 24
Peak memory 196688 kb
Host smart-f9f1aeb4-73b5-47c6-a217-ad0708c78112
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953891075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.953891075
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2483297118
Short name T152
Test name
Test status
Simulation time 62815222 ps
CPU time 2.33 seconds
Started Jun 04 12:24:58 PM PDT 24
Finished Jun 04 12:25:01 PM PDT 24
Peak memory 197860 kb
Host smart-015ea227-b521-4fcf-9e32-8ecc6d4ef766
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483297118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2483297118
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1328786021
Short name T426
Test name
Test status
Simulation time 123327726 ps
CPU time 3.28 seconds
Started Jun 04 12:25:05 PM PDT 24
Finished Jun 04 12:25:10 PM PDT 24
Peak memory 196388 kb
Host smart-b29cc85d-d136-494d-a7fe-708276b99895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328786021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1328786021
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4003162136
Short name T249
Test name
Test status
Simulation time 39380726 ps
CPU time 0.69 seconds
Started Jun 04 12:24:47 PM PDT 24
Finished Jun 04 12:24:50 PM PDT 24
Peak memory 195280 kb
Host smart-bcdd0c14-2b5d-4ae0-840f-f3e9d4d7cc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003162136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4003162136
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2692449227
Short name T522
Test name
Test status
Simulation time 176842392 ps
CPU time 0.67 seconds
Started Jun 04 12:24:58 PM PDT 24
Finished Jun 04 12:25:00 PM PDT 24
Peak memory 195172 kb
Host smart-ca73cc87-39f2-4403-8835-077dd882c57d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692449227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2692449227
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2444954220
Short name T305
Test name
Test status
Simulation time 1368092169 ps
CPU time 4.11 seconds
Started Jun 04 12:25:05 PM PDT 24
Finished Jun 04 12:25:11 PM PDT 24
Peak memory 197112 kb
Host smart-80fc26f1-b61c-4685-9296-6568b0f03020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444954220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2444954220
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.531352559
Short name T233
Test name
Test status
Simulation time 61419634 ps
CPU time 1.24 seconds
Started Jun 04 12:24:54 PM PDT 24
Finished Jun 04 12:24:56 PM PDT 24
Peak memory 197808 kb
Host smart-dfdd090c-f754-40d4-b33f-8491b52cdc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531352559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.531352559
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.907308808
Short name T547
Test name
Test status
Simulation time 81783749 ps
CPU time 1.31 seconds
Started Jun 04 12:25:01 PM PDT 24
Finished Jun 04 12:25:03 PM PDT 24
Peak memory 196572 kb
Host smart-c1455083-0a4c-4322-8dc8-8a38a48a4bbc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907308808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.907308808
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.132028942
Short name T452
Test name
Test status
Simulation time 6901369786 ps
CPU time 170.84 seconds
Started Jun 04 12:24:58 PM PDT 24
Finished Jun 04 12:27:50 PM PDT 24
Peak memory 198020 kb
Host smart-6a46c0f8-7634-4491-82d7-db9afed54a1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132028942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.132028942
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3506525433
Short name T392
Test name
Test status
Simulation time 15984181 ps
CPU time 0.55 seconds
Started Jun 04 12:25:07 PM PDT 24
Finished Jun 04 12:25:09 PM PDT 24
Peak memory 194436 kb
Host smart-72387e47-c3d1-4dca-8fcd-99c3a755a9c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506525433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3506525433
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.415281579
Short name T502
Test name
Test status
Simulation time 54744939 ps
CPU time 0.69 seconds
Started Jun 04 12:25:06 PM PDT 24
Finished Jun 04 12:25:08 PM PDT 24
Peak memory 194860 kb
Host smart-116dc251-cfac-4fb2-81e4-e353b7fe7e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415281579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.415281579
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2697870382
Short name T499
Test name
Test status
Simulation time 1207047266 ps
CPU time 10.37 seconds
Started Jun 04 12:25:11 PM PDT 24
Finished Jun 04 12:25:23 PM PDT 24
Peak memory 196876 kb
Host smart-d192efca-9b7b-4d87-ad31-caadf1fa8385
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697870382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2697870382
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3231030902
Short name T1
Test name
Test status
Simulation time 42739239 ps
CPU time 0.69 seconds
Started Jun 04 12:25:06 PM PDT 24
Finished Jun 04 12:25:08 PM PDT 24
Peak memory 194664 kb
Host smart-9bb8cdf9-1da1-4581-b4ef-48500158e99c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231030902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3231030902
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.4090844741
Short name T137
Test name
Test status
Simulation time 123980298 ps
CPU time 1.16 seconds
Started Jun 04 12:25:05 PM PDT 24
Finished Jun 04 12:25:08 PM PDT 24
Peak memory 196112 kb
Host smart-80209374-4cbf-49ef-bd34-1306b03aac38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090844741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.4090844741
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.189759328
Short name T258
Test name
Test status
Simulation time 93109300 ps
CPU time 1.83 seconds
Started Jun 04 12:25:00 PM PDT 24
Finished Jun 04 12:25:03 PM PDT 24
Peak memory 197852 kb
Host smart-877f74e1-8d44-4ee0-a752-10b269405e2c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189759328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.189759328
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.243821064
Short name T360
Test name
Test status
Simulation time 384220086 ps
CPU time 2.76 seconds
Started Jun 04 12:25:01 PM PDT 24
Finished Jun 04 12:25:05 PM PDT 24
Peak memory 197864 kb
Host smart-e151a191-d414-4a15-9683-9fc0f1eff842
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243821064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
243821064
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2006001848
Short name T262
Test name
Test status
Simulation time 19861241 ps
CPU time 0.68 seconds
Started Jun 04 12:24:59 PM PDT 24
Finished Jun 04 12:25:01 PM PDT 24
Peak memory 194124 kb
Host smart-e202dd14-b48b-4ab3-a382-9b2e340122a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006001848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2006001848
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2785495694
Short name T203
Test name
Test status
Simulation time 56908798 ps
CPU time 1.12 seconds
Started Jun 04 12:25:05 PM PDT 24
Finished Jun 04 12:25:08 PM PDT 24
Peak memory 196892 kb
Host smart-b016d308-db2b-471e-9136-4df9a7bbc853
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785495694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2785495694
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3502538483
Short name T680
Test name
Test status
Simulation time 337429676 ps
CPU time 3.97 seconds
Started Jun 04 12:25:09 PM PDT 24
Finished Jun 04 12:25:13 PM PDT 24
Peak memory 197720 kb
Host smart-e3d770dc-14a3-4935-b885-9895a0a6b579
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502538483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3502538483
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.91771631
Short name T555
Test name
Test status
Simulation time 78699320 ps
CPU time 0.89 seconds
Started Jun 04 12:25:01 PM PDT 24
Finished Jun 04 12:25:03 PM PDT 24
Peak memory 195868 kb
Host smart-086dfcd1-2bbc-4ad0-863f-5c0707c16eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91771631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.91771631
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.4018291939
Short name T235
Test name
Test status
Simulation time 46038097 ps
CPU time 1.26 seconds
Started Jun 04 12:25:06 PM PDT 24
Finished Jun 04 12:25:09 PM PDT 24
Peak memory 196688 kb
Host smart-21c21fa9-b663-4d85-9548-bd06e26e87c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018291939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.4018291939
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1529971719
Short name T118
Test name
Test status
Simulation time 14305537505 ps
CPU time 184.71 seconds
Started Jun 04 12:26:26 PM PDT 24
Finished Jun 04 12:29:33 PM PDT 24
Peak memory 197972 kb
Host smart-7238b5d7-bca7-4423-921b-023ffb782aa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529971719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1529971719
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.4076053281
Short name T399
Test name
Test status
Simulation time 82326725092 ps
CPU time 705.92 seconds
Started Jun 04 12:26:26 PM PDT 24
Finished Jun 04 12:38:14 PM PDT 24
Peak memory 198076 kb
Host smart-84f55109-802f-43cb-8f4c-f83ae3b51cfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4076053281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.4076053281
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3608123098
Short name T16
Test name
Test status
Simulation time 84199256 ps
CPU time 0.76 seconds
Started Jun 04 12:26:27 PM PDT 24
Finished Jun 04 12:26:30 PM PDT 24
Peak memory 195264 kb
Host smart-1b425113-6c21-4558-a151-564492f2f80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608123098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3608123098
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.452924721
Short name T418
Test name
Test status
Simulation time 3333740459 ps
CPU time 20.46 seconds
Started Jun 04 12:25:05 PM PDT 24
Finished Jun 04 12:25:28 PM PDT 24
Peak memory 196548 kb
Host smart-98de9b04-deba-4e66-8e6d-2e038a693f92
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452924721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.452924721
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.4222656776
Short name T238
Test name
Test status
Simulation time 120641779 ps
CPU time 0.72 seconds
Started Jun 04 12:25:16 PM PDT 24
Finished Jun 04 12:25:17 PM PDT 24
Peak memory 195544 kb
Host smart-0fc2c44c-ecd4-42b3-9534-e9d0d6fc4838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222656776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.4222656776
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1624856821
Short name T127
Test name
Test status
Simulation time 119088438 ps
CPU time 1.01 seconds
Started Jun 04 12:25:05 PM PDT 24
Finished Jun 04 12:25:08 PM PDT 24
Peak memory 195600 kb
Host smart-17ff3a39-f586-4874-85b5-655bd7e4d761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624856821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1624856821
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1535959223
Short name T312
Test name
Test status
Simulation time 376185630 ps
CPU time 3.71 seconds
Started Jun 04 12:25:06 PM PDT 24
Finished Jun 04 12:25:11 PM PDT 24
Peak memory 197864 kb
Host smart-435160e3-132d-4139-862e-075d4dc88f37
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535959223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1535959223
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2835446030
Short name T578
Test name
Test status
Simulation time 67453938 ps
CPU time 1.63 seconds
Started Jun 04 12:25:07 PM PDT 24
Finished Jun 04 12:25:10 PM PDT 24
Peak memory 195888 kb
Host smart-f80dd127-55e2-41d8-9137-400d80d18f2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835446030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2835446030
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.157140131
Short name T389
Test name
Test status
Simulation time 587390186 ps
CPU time 1.16 seconds
Started Jun 04 12:25:11 PM PDT 24
Finished Jun 04 12:25:13 PM PDT 24
Peak memory 196448 kb
Host smart-be1e1e21-db25-43ef-87a4-0f84c7397c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157140131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.157140131
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2540040717
Short name T30
Test name
Test status
Simulation time 88976200 ps
CPU time 0.96 seconds
Started Jun 04 12:25:06 PM PDT 24
Finished Jun 04 12:25:09 PM PDT 24
Peak memory 195768 kb
Host smart-b17bf24a-65f6-4766-9e7e-57ff09299f05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540040717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2540040717
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1215859594
Short name T562
Test name
Test status
Simulation time 1348236963 ps
CPU time 4.34 seconds
Started Jun 04 12:25:17 PM PDT 24
Finished Jun 04 12:25:22 PM PDT 24
Peak memory 197776 kb
Host smart-65f9887a-e03d-438c-963f-79fcc376c5e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215859594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1215859594
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3847621142
Short name T234
Test name
Test status
Simulation time 104909742 ps
CPU time 0.94 seconds
Started Jun 04 12:25:11 PM PDT 24
Finished Jun 04 12:25:13 PM PDT 24
Peak memory 195492 kb
Host smart-762500bb-040f-4599-8209-2f60efd15f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847621142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3847621142
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2081410829
Short name T584
Test name
Test status
Simulation time 348048407 ps
CPU time 1.07 seconds
Started Jun 04 12:25:04 PM PDT 24
Finished Jun 04 12:25:06 PM PDT 24
Peak memory 196216 kb
Host smart-3a4536d1-8adc-4d6b-bb77-15c6d20eaeed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081410829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2081410829
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3087840098
Short name T469
Test name
Test status
Simulation time 3836297751 ps
CPU time 29.11 seconds
Started Jun 04 12:25:17 PM PDT 24
Finished Jun 04 12:25:47 PM PDT 24
Peak memory 198024 kb
Host smart-f4af2e98-0b7c-47d8-94c2-b1c104e33121
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087840098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3087840098
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2368059429
Short name T619
Test name
Test status
Simulation time 41255493 ps
CPU time 0.56 seconds
Started Jun 04 12:25:31 PM PDT 24
Finished Jun 04 12:25:33 PM PDT 24
Peak memory 193976 kb
Host smart-346a9a8d-1677-4a6f-8fa6-822ccc2cb961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368059429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2368059429
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1515523568
Short name T155
Test name
Test status
Simulation time 42210684 ps
CPU time 0.8 seconds
Started Jun 04 12:25:16 PM PDT 24
Finished Jun 04 12:25:17 PM PDT 24
Peak memory 195328 kb
Host smart-bbbc2def-4666-4ee6-8bd9-711c3a1b40ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515523568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1515523568
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.91977886
Short name T518
Test name
Test status
Simulation time 218148221 ps
CPU time 9.16 seconds
Started Jun 04 12:25:32 PM PDT 24
Finished Jun 04 12:25:42 PM PDT 24
Peak memory 197840 kb
Host smart-9a24b163-9aaa-4c00-a01f-b56e58e4f6ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91977886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stress
.91977886
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3972692301
Short name T222
Test name
Test status
Simulation time 211397291 ps
CPU time 1.12 seconds
Started Jun 04 12:25:25 PM PDT 24
Finished Jun 04 12:25:27 PM PDT 24
Peak memory 196448 kb
Host smart-9315d0b1-3323-402f-8570-961ecc0e2ae6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972692301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3972692301
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1502674738
Short name T349
Test name
Test status
Simulation time 86069038 ps
CPU time 0.72 seconds
Started Jun 04 12:25:26 PM PDT 24
Finished Jun 04 12:25:28 PM PDT 24
Peak memory 194120 kb
Host smart-3905ab9d-62c2-45d2-a21c-b2029bf2d034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502674738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1502674738
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.642621807
Short name T566
Test name
Test status
Simulation time 95880464 ps
CPU time 1.7 seconds
Started Jun 04 12:25:31 PM PDT 24
Finished Jun 04 12:25:34 PM PDT 24
Peak memory 196664 kb
Host smart-1f871925-67b9-4d3c-9418-195f7e6983d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642621807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.642621807
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2546180316
Short name T236
Test name
Test status
Simulation time 288860948 ps
CPU time 3.02 seconds
Started Jun 04 12:25:23 PM PDT 24
Finished Jun 04 12:25:27 PM PDT 24
Peak memory 197876 kb
Host smart-a0088567-a417-4586-ba52-c6ceeffdbee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546180316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2546180316
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3137391711
Short name T244
Test name
Test status
Simulation time 106579035 ps
CPU time 1.18 seconds
Started Jun 04 12:25:15 PM PDT 24
Finished Jun 04 12:25:17 PM PDT 24
Peak memory 196848 kb
Host smart-3a73ac91-a890-4320-acf3-94c58ec35b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137391711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3137391711
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2993064510
Short name T702
Test name
Test status
Simulation time 25488025 ps
CPU time 0.89 seconds
Started Jun 04 12:25:19 PM PDT 24
Finished Jun 04 12:25:21 PM PDT 24
Peak memory 195872 kb
Host smart-34900818-f035-49c7-9d1f-8d7feffbbaf0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993064510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2993064510
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1047536320
Short name T509
Test name
Test status
Simulation time 158686512 ps
CPU time 3.33 seconds
Started Jun 04 12:25:29 PM PDT 24
Finished Jun 04 12:25:33 PM PDT 24
Peak memory 197808 kb
Host smart-47487a75-aa52-43b6-9e78-d5a454c975a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047536320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1047536320
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2190405594
Short name T162
Test name
Test status
Simulation time 292609307 ps
CPU time 1.24 seconds
Started Jun 04 12:25:17 PM PDT 24
Finished Jun 04 12:25:19 PM PDT 24
Peak memory 196060 kb
Host smart-540dc09f-bcae-4a33-a12f-1ba4af0874b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190405594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2190405594
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3884055583
Short name T715
Test name
Test status
Simulation time 60998342 ps
CPU time 1.09 seconds
Started Jun 04 12:25:19 PM PDT 24
Finished Jun 04 12:25:20 PM PDT 24
Peak memory 195640 kb
Host smart-93387f12-2971-4704-8f8c-1fa80ca8428e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884055583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3884055583
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2697431672
Short name T587
Test name
Test status
Simulation time 7909692660 ps
CPU time 190.63 seconds
Started Jun 04 12:25:26 PM PDT 24
Finished Jun 04 12:28:37 PM PDT 24
Peak memory 197996 kb
Host smart-03a6ed0b-ada8-4418-8045-df927aa73752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697431672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2697431672
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1138847499
Short name T561
Test name
Test status
Simulation time 26592555 ps
CPU time 0.56 seconds
Started Jun 04 12:25:30 PM PDT 24
Finished Jun 04 12:25:32 PM PDT 24
Peak memory 193748 kb
Host smart-8b3d995b-d646-45d6-9952-41beedaf301e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138847499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1138847499
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3161431618
Short name T53
Test name
Test status
Simulation time 94595279 ps
CPU time 0.79 seconds
Started Jun 04 12:25:22 PM PDT 24
Finished Jun 04 12:25:24 PM PDT 24
Peak memory 196204 kb
Host smart-86c0d779-9a22-4023-a06f-f7c978bb971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161431618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3161431618
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1546414429
Short name T219
Test name
Test status
Simulation time 207186526 ps
CPU time 6.78 seconds
Started Jun 04 12:25:24 PM PDT 24
Finished Jun 04 12:25:32 PM PDT 24
Peak memory 196856 kb
Host smart-bb76d524-d10b-46fb-8674-cfffce46f225
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546414429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1546414429
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1989969329
Short name T552
Test name
Test status
Simulation time 56669634 ps
CPU time 0.86 seconds
Started Jun 04 12:25:27 PM PDT 24
Finished Jun 04 12:25:29 PM PDT 24
Peak memory 195840 kb
Host smart-db2ab214-1a3b-44e6-a4e7-f19331fc7ce9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989969329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1989969329
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3844758689
Short name T280
Test name
Test status
Simulation time 83762010 ps
CPU time 1.25 seconds
Started Jun 04 12:25:30 PM PDT 24
Finished Jun 04 12:25:33 PM PDT 24
Peak memory 195964 kb
Host smart-857da4f7-a08a-422b-a42e-11b63db88337
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844758689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3844758689
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.891115998
Short name T650
Test name
Test status
Simulation time 72321568 ps
CPU time 2.53 seconds
Started Jun 04 12:25:30 PM PDT 24
Finished Jun 04 12:25:33 PM PDT 24
Peak memory 198040 kb
Host smart-b1bce99a-26a8-424b-aeb4-1dabfe03ed59
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891115998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.891115998
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2219209564
Short name T448
Test name
Test status
Simulation time 254348017 ps
CPU time 1.29 seconds
Started Jun 04 12:25:23 PM PDT 24
Finished Jun 04 12:25:25 PM PDT 24
Peak memory 196612 kb
Host smart-61b81239-d81b-4d5e-9a63-5778bb0e205a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219209564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2219209564
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1341443584
Short name T284
Test name
Test status
Simulation time 288023725 ps
CPU time 1.22 seconds
Started Jun 04 12:25:24 PM PDT 24
Finished Jun 04 12:25:27 PM PDT 24
Peak memory 196848 kb
Host smart-ad48d0ac-2bd5-4cf1-80c7-7903c5859c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341443584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1341443584
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.4280036271
Short name T376
Test name
Test status
Simulation time 30830301 ps
CPU time 0.96 seconds
Started Jun 04 12:25:22 PM PDT 24
Finished Jun 04 12:25:24 PM PDT 24
Peak memory 195948 kb
Host smart-6cd56047-1744-4bef-96f3-6da7d77d920e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280036271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.4280036271
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2264139468
Short name T156
Test name
Test status
Simulation time 80583906 ps
CPU time 3.43 seconds
Started Jun 04 12:25:32 PM PDT 24
Finished Jun 04 12:25:36 PM PDT 24
Peak memory 197684 kb
Host smart-7aa0ecff-d001-4ad5-9812-37e6336e39ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264139468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2264139468
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.4254290700
Short name T543
Test name
Test status
Simulation time 35419729 ps
CPU time 0.93 seconds
Started Jun 04 12:25:31 PM PDT 24
Finished Jun 04 12:25:33 PM PDT 24
Peak memory 195304 kb
Host smart-d9c65560-3bac-4d4b-9bef-e6e4351eb7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254290700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.4254290700
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3420999447
Short name T526
Test name
Test status
Simulation time 516154249 ps
CPU time 1.17 seconds
Started Jun 04 12:25:27 PM PDT 24
Finished Jun 04 12:25:30 PM PDT 24
Peak memory 195516 kb
Host smart-25a4f157-151e-47dd-b425-6f558117fdec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420999447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3420999447
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2465753531
Short name T489
Test name
Test status
Simulation time 9444178202 ps
CPU time 113.33 seconds
Started Jun 04 12:25:23 PM PDT 24
Finished Jun 04 12:27:17 PM PDT 24
Peak memory 197980 kb
Host smart-fe453021-8ff8-4097-aa0d-2883500341d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465753531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2465753531
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3219931272
Short name T462
Test name
Test status
Simulation time 923963511432 ps
CPU time 1686.5 seconds
Started Jun 04 12:25:31 PM PDT 24
Finished Jun 04 12:53:39 PM PDT 24
Peak memory 198128 kb
Host smart-49822075-7757-4fa7-a851-ededc2f975e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3219931272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3219931272
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.287459245
Short name T455
Test name
Test status
Simulation time 63114662 ps
CPU time 0.59 seconds
Started Jun 04 12:25:30 PM PDT 24
Finished Jun 04 12:25:32 PM PDT 24
Peak memory 193976 kb
Host smart-c2e42070-db94-4a07-9f46-d8ab5ca69f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287459245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.287459245
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3046721039
Short name T670
Test name
Test status
Simulation time 24842401 ps
CPU time 0.81 seconds
Started Jun 04 12:25:28 PM PDT 24
Finished Jun 04 12:25:30 PM PDT 24
Peak memory 196172 kb
Host smart-479cfb38-7e77-488b-b8ea-7a0c37571f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046721039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3046721039
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.4110091085
Short name T26
Test name
Test status
Simulation time 462403313 ps
CPU time 5.54 seconds
Started Jun 04 12:25:23 PM PDT 24
Finished Jun 04 12:25:30 PM PDT 24
Peak memory 195416 kb
Host smart-a4de1113-5387-4e22-a249-8a2919774571
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110091085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.4110091085
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4062298653
Short name T503
Test name
Test status
Simulation time 81176817 ps
CPU time 0.61 seconds
Started Jun 04 12:25:30 PM PDT 24
Finished Jun 04 12:25:32 PM PDT 24
Peak memory 194408 kb
Host smart-2b76329d-ed59-4bcb-a1ca-5a56d13f91d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062298653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4062298653
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.364948442
Short name T709
Test name
Test status
Simulation time 73734208 ps
CPU time 1.21 seconds
Started Jun 04 12:25:30 PM PDT 24
Finished Jun 04 12:25:32 PM PDT 24
Peak memory 196524 kb
Host smart-ddc17543-78a0-40d3-a574-45f33fd76914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364948442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.364948442
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1904441684
Short name T560
Test name
Test status
Simulation time 123754214 ps
CPU time 1.17 seconds
Started Jun 04 12:25:30 PM PDT 24
Finished Jun 04 12:25:32 PM PDT 24
Peak memory 197752 kb
Host smart-19c8d5ca-6ebf-4ba0-b441-2cc62fce0092
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904441684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1904441684
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.644141387
Short name T463
Test name
Test status
Simulation time 482520605 ps
CPU time 2.7 seconds
Started Jun 04 12:25:30 PM PDT 24
Finished Jun 04 12:25:34 PM PDT 24
Peak memory 197172 kb
Host smart-cf43d045-1487-4ce5-99c0-c86425fb28fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644141387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
644141387
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3775559259
Short name T163
Test name
Test status
Simulation time 194262255 ps
CPU time 0.96 seconds
Started Jun 04 12:25:22 PM PDT 24
Finished Jun 04 12:25:23 PM PDT 24
Peak memory 195908 kb
Host smart-9c33ef27-c03d-486a-a5f2-b101dff580b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775559259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3775559259
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2702427904
Short name T17
Test name
Test status
Simulation time 50140439 ps
CPU time 1.03 seconds
Started Jun 04 12:25:25 PM PDT 24
Finished Jun 04 12:25:27 PM PDT 24
Peak memory 196340 kb
Host smart-89314d8b-7010-4649-a47a-553f49caffc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702427904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2702427904
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.754530783
Short name T494
Test name
Test status
Simulation time 111558563 ps
CPU time 2.67 seconds
Started Jun 04 12:25:31 PM PDT 24
Finished Jun 04 12:25:35 PM PDT 24
Peak memory 197704 kb
Host smart-ca653846-c0e6-4bcf-a8a4-f8cb2256f346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754530783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.754530783
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1579131945
Short name T310
Test name
Test status
Simulation time 61117743 ps
CPU time 1.11 seconds
Started Jun 04 12:25:23 PM PDT 24
Finished Jun 04 12:25:25 PM PDT 24
Peak memory 195568 kb
Host smart-d07d0254-6058-4aee-b554-9c908865917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579131945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1579131945
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1782337687
Short name T669
Test name
Test status
Simulation time 41229788 ps
CPU time 1.18 seconds
Started Jun 04 12:25:30 PM PDT 24
Finished Jun 04 12:25:33 PM PDT 24
Peak memory 196068 kb
Host smart-342d3645-249c-405e-bc8d-bddbb3b7f458
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782337687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1782337687
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.339371054
Short name T710
Test name
Test status
Simulation time 70658764984 ps
CPU time 201.99 seconds
Started Jun 04 12:25:28 PM PDT 24
Finished Jun 04 12:28:51 PM PDT 24
Peak memory 198112 kb
Host smart-0fd7692e-e69f-42a4-9351-b2fe48154a2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339371054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.339371054
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1569515576
Short name T444
Test name
Test status
Simulation time 57947020142 ps
CPU time 341.92 seconds
Started Jun 04 12:25:24 PM PDT 24
Finished Jun 04 12:31:06 PM PDT 24
Peak memory 198112 kb
Host smart-3fb252c2-0b01-4864-875c-47ed387564dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1569515576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1569515576
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2422661691
Short name T678
Test name
Test status
Simulation time 16518065 ps
CPU time 0.56 seconds
Started Jun 04 12:25:41 PM PDT 24
Finished Jun 04 12:25:42 PM PDT 24
Peak memory 193900 kb
Host smart-9e4bc1d7-10c6-44a5-a9b0-369f70c8f75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422661691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2422661691
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.739302811
Short name T694
Test name
Test status
Simulation time 339893830 ps
CPU time 0.76 seconds
Started Jun 04 12:25:33 PM PDT 24
Finished Jun 04 12:25:35 PM PDT 24
Peak memory 195948 kb
Host smart-888d27bb-b7ee-4a7a-86a9-ca9657636379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739302811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.739302811
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4140546915
Short name T159
Test name
Test status
Simulation time 1203289276 ps
CPU time 20.18 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 196848 kb
Host smart-c6cb46dc-267b-4483-bae9-d050ada78672
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140546915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4140546915
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2756226309
Short name T307
Test name
Test status
Simulation time 65550000 ps
CPU time 0.65 seconds
Started Jun 04 12:26:01 PM PDT 24
Finished Jun 04 12:26:03 PM PDT 24
Peak memory 195088 kb
Host smart-8dad7670-e838-4e55-834a-815734224f7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756226309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2756226309
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1972205823
Short name T651
Test name
Test status
Simulation time 116135730 ps
CPU time 0.93 seconds
Started Jun 04 12:25:35 PM PDT 24
Finished Jun 04 12:25:37 PM PDT 24
Peak memory 195920 kb
Host smart-bae9ecff-6be4-4499-b238-a38372d50d9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972205823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1972205823
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.711080313
Short name T270
Test name
Test status
Simulation time 138753464 ps
CPU time 1.52 seconds
Started Jun 04 12:25:41 PM PDT 24
Finished Jun 04 12:25:44 PM PDT 24
Peak memory 196280 kb
Host smart-40155738-1a66-4d77-9385-476195da8025
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711080313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.711080313
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.26707632
Short name T684
Test name
Test status
Simulation time 31114183 ps
CPU time 0.83 seconds
Started Jun 04 12:25:35 PM PDT 24
Finished Jun 04 12:25:37 PM PDT 24
Peak memory 194216 kb
Host smart-a5c4cf1a-a1b8-4e68-84c0-3a061f43ef7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26707632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.26707632
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3539611212
Short name T450
Test name
Test status
Simulation time 17359018 ps
CPU time 0.68 seconds
Started Jun 04 12:25:24 PM PDT 24
Finished Jun 04 12:25:26 PM PDT 24
Peak memory 194108 kb
Host smart-a65e61eb-4af0-4143-b47b-d53d2b01a9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539611212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3539611212
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3291157710
Short name T319
Test name
Test status
Simulation time 30886261 ps
CPU time 0.8 seconds
Started Jun 04 12:25:29 PM PDT 24
Finished Jun 04 12:25:30 PM PDT 24
Peak memory 197196 kb
Host smart-3e1b419d-1f68-47bd-8814-62c8da84d78a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291157710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3291157710
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.576022409
Short name T485
Test name
Test status
Simulation time 55714692 ps
CPU time 2.37 seconds
Started Jun 04 12:25:38 PM PDT 24
Finished Jun 04 12:25:41 PM PDT 24
Peak memory 197800 kb
Host smart-0e145059-1b66-4682-b997-cbe9c7307aa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576022409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.576022409
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3903481392
Short name T538
Test name
Test status
Simulation time 345789532 ps
CPU time 0.87 seconds
Started Jun 04 12:25:30 PM PDT 24
Finished Jun 04 12:25:32 PM PDT 24
Peak memory 195780 kb
Host smart-f4e88148-066b-4a14-8b86-b51a8732dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903481392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3903481392
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1896925267
Short name T172
Test name
Test status
Simulation time 112893092 ps
CPU time 0.93 seconds
Started Jun 04 12:25:28 PM PDT 24
Finished Jun 04 12:25:30 PM PDT 24
Peak memory 195660 kb
Host smart-79c07b4c-7a67-42f4-b478-58cf460a61c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896925267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1896925267
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1041435173
Short name T495
Test name
Test status
Simulation time 2016502894 ps
CPU time 18.27 seconds
Started Jun 04 12:25:35 PM PDT 24
Finished Jun 04 12:25:54 PM PDT 24
Peak memory 197904 kb
Host smart-70002a9a-b69c-4ab9-95b6-7383c116a3d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041435173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1041435173
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.644392341
Short name T706
Test name
Test status
Simulation time 48440698 ps
CPU time 0.56 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:25:39 PM PDT 24
Peak memory 194420 kb
Host smart-49f3d874-391b-4292-b46f-26ffa3d9f481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644392341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.644392341
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2414292417
Short name T425
Test name
Test status
Simulation time 63068169 ps
CPU time 0.87 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:25:40 PM PDT 24
Peak memory 195536 kb
Host smart-08f74dcf-2c89-49ad-b7bb-ad94daed9ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414292417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2414292417
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3269349710
Short name T316
Test name
Test status
Simulation time 368951816 ps
CPU time 17.78 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:25:56 PM PDT 24
Peak memory 196476 kb
Host smart-01f3a536-8ad7-49b1-b728-5732dffe285e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269349710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3269349710
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.930062392
Short name T65
Test name
Test status
Simulation time 372366315 ps
CPU time 1.02 seconds
Started Jun 04 12:25:35 PM PDT 24
Finished Jun 04 12:25:37 PM PDT 24
Peak memory 196508 kb
Host smart-5da93022-2cec-49b7-b2d1-3079f2487029
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930062392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.930062392
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.370203688
Short name T447
Test name
Test status
Simulation time 66853448 ps
CPU time 1.54 seconds
Started Jun 04 12:25:41 PM PDT 24
Finished Jun 04 12:25:44 PM PDT 24
Peak memory 195696 kb
Host smart-f54ee508-c3e3-42a9-9570-2ff8fee512c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370203688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.370203688
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.723387360
Short name T617
Test name
Test status
Simulation time 433019083 ps
CPU time 2.81 seconds
Started Jun 04 12:25:38 PM PDT 24
Finished Jun 04 12:25:42 PM PDT 24
Peak memory 197864 kb
Host smart-0490f419-148f-4920-94d1-7b86e85287fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723387360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.723387360
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3696408550
Short name T557
Test name
Test status
Simulation time 339900494 ps
CPU time 2.23 seconds
Started Jun 04 12:25:44 PM PDT 24
Finished Jun 04 12:25:47 PM PDT 24
Peak memory 196388 kb
Host smart-f1a3812b-a534-4b90-85c1-3bbae5cc83ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696408550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3696408550
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.4061808541
Short name T256
Test name
Test status
Simulation time 139257103 ps
CPU time 0.83 seconds
Started Jun 04 12:25:36 PM PDT 24
Finished Jun 04 12:25:38 PM PDT 24
Peak memory 196536 kb
Host smart-47ff91ac-3d6d-4294-84e1-96396d75c4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061808541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.4061808541
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.612352752
Short name T255
Test name
Test status
Simulation time 115571511 ps
CPU time 1.06 seconds
Started Jun 04 12:25:36 PM PDT 24
Finished Jun 04 12:25:38 PM PDT 24
Peak memory 196380 kb
Host smart-a9c75716-e133-44bc-b6f0-2a88afdd3db5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612352752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.612352752
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1349949879
Short name T285
Test name
Test status
Simulation time 955919686 ps
CPU time 3.82 seconds
Started Jun 04 12:25:42 PM PDT 24
Finished Jun 04 12:25:46 PM PDT 24
Peak memory 197592 kb
Host smart-5997b154-b0be-4334-9335-0ed2691f722a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349949879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1349949879
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1298554940
Short name T49
Test name
Test status
Simulation time 72382504 ps
CPU time 0.77 seconds
Started Jun 04 12:25:41 PM PDT 24
Finished Jun 04 12:25:43 PM PDT 24
Peak memory 195308 kb
Host smart-b74054f5-dbdb-43bf-9d75-e70d25d0344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298554940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1298554940
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3932562708
Short name T271
Test name
Test status
Simulation time 42035277 ps
CPU time 1.22 seconds
Started Jun 04 12:25:39 PM PDT 24
Finished Jun 04 12:25:41 PM PDT 24
Peak memory 197948 kb
Host smart-34b93939-238b-411b-a9a8-69818f506542
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932562708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3932562708
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2407535635
Short name T318
Test name
Test status
Simulation time 13095428750 ps
CPU time 143.21 seconds
Started Jun 04 12:25:41 PM PDT 24
Finished Jun 04 12:28:06 PM PDT 24
Peak memory 198072 kb
Host smart-0c3c5d7b-0397-4549-8d09-614c423256d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407535635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2407535635
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1276194859
Short name T59
Test name
Test status
Simulation time 26540867575 ps
CPU time 406 seconds
Started Jun 04 12:25:41 PM PDT 24
Finished Jun 04 12:32:28 PM PDT 24
Peak memory 198044 kb
Host smart-2e97ca8d-be20-4bee-ac9e-c5c24413867b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1276194859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1276194859
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3603129046
Short name T381
Test name
Test status
Simulation time 11134420 ps
CPU time 0.54 seconds
Started Jun 04 12:25:39 PM PDT 24
Finished Jun 04 12:25:40 PM PDT 24
Peak memory 193764 kb
Host smart-9078a32b-76c7-44cf-86f3-28b360b346e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603129046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3603129046
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2185627137
Short name T707
Test name
Test status
Simulation time 56437258 ps
CPU time 0.72 seconds
Started Jun 04 12:25:47 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 195884 kb
Host smart-fcd6b07d-ff00-49a9-85e7-680a4850005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185627137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2185627137
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1745848729
Short name T251
Test name
Test status
Simulation time 4504010455 ps
CPU time 26.96 seconds
Started Jun 04 12:25:44 PM PDT 24
Finished Jun 04 12:26:12 PM PDT 24
Peak memory 196948 kb
Host smart-9c5f7207-0b13-4044-8d17-efa8957261a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745848729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1745848729
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1335680639
Short name T51
Test name
Test status
Simulation time 39363540 ps
CPU time 0.74 seconds
Started Jun 04 12:25:51 PM PDT 24
Finished Jun 04 12:25:53 PM PDT 24
Peak memory 195616 kb
Host smart-ca469d66-4aea-4648-90be-8be9d2b965f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335680639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1335680639
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2949783157
Short name T453
Test name
Test status
Simulation time 197964574 ps
CPU time 0.93 seconds
Started Jun 04 12:25:36 PM PDT 24
Finished Jun 04 12:25:38 PM PDT 24
Peak memory 195812 kb
Host smart-943fe8c4-e09a-4e1f-ad40-4c9e06cdbe87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949783157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2949783157
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1966658886
Short name T240
Test name
Test status
Simulation time 103147429 ps
CPU time 1.12 seconds
Started Jun 04 12:25:47 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 197272 kb
Host smart-5702c9e3-128b-43ae-ae07-2d5cf1820c58
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966658886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1966658886
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3226775866
Short name T434
Test name
Test status
Simulation time 175200986 ps
CPU time 1.7 seconds
Started Jun 04 12:25:47 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 195988 kb
Host smart-9adc8f3f-27fe-4e7e-b4f8-a6d16e857e82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226775866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3226775866
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2574539258
Short name T457
Test name
Test status
Simulation time 13403019 ps
CPU time 0.62 seconds
Started Jun 04 12:25:44 PM PDT 24
Finished Jun 04 12:25:45 PM PDT 24
Peak memory 194860 kb
Host smart-a4455f9b-a2c3-4cea-8064-09bd10ffa55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574539258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2574539258
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.4208630338
Short name T629
Test name
Test status
Simulation time 53638276 ps
CPU time 0.66 seconds
Started Jun 04 12:25:44 PM PDT 24
Finished Jun 04 12:25:46 PM PDT 24
Peak memory 195092 kb
Host smart-71c7212a-cab3-4669-b99b-06b4dfab171d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208630338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.4208630338
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.710392227
Short name T7
Test name
Test status
Simulation time 1419360012 ps
CPU time 4 seconds
Started Jun 04 12:25:51 PM PDT 24
Finished Jun 04 12:25:56 PM PDT 24
Peak memory 197808 kb
Host smart-a3e9a999-47c4-472f-99f2-20e28fd5faf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710392227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.710392227
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2572255363
Short name T28
Test name
Test status
Simulation time 62973409 ps
CPU time 0.76 seconds
Started Jun 04 12:25:45 PM PDT 24
Finished Jun 04 12:25:47 PM PDT 24
Peak memory 195128 kb
Host smart-c7ae14d5-6c67-4977-b184-9afe234237de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572255363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2572255363
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1207298449
Short name T504
Test name
Test status
Simulation time 211986746 ps
CPU time 0.99 seconds
Started Jun 04 12:25:45 PM PDT 24
Finished Jun 04 12:25:47 PM PDT 24
Peak memory 195424 kb
Host smart-0f450807-4574-41ae-aedc-1c9a91d3a465
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207298449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1207298449
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3071283951
Short name T92
Test name
Test status
Simulation time 11224260261 ps
CPU time 150.4 seconds
Started Jun 04 12:25:47 PM PDT 24
Finished Jun 04 12:28:19 PM PDT 24
Peak memory 198064 kb
Host smart-c7daf481-ef63-4970-8154-5ad426e1b333
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071283951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3071283951
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2968220746
Short name T276
Test name
Test status
Simulation time 30069127 ps
CPU time 0.59 seconds
Started Jun 04 12:24:43 PM PDT 24
Finished Jun 04 12:24:46 PM PDT 24
Peak memory 193700 kb
Host smart-9b622ae8-4e89-457e-a498-17a5448ea875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968220746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2968220746
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.639665844
Short name T574
Test name
Test status
Simulation time 33755599 ps
CPU time 0.75 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:24:44 PM PDT 24
Peak memory 195108 kb
Host smart-27b00165-c324-4d8c-9cdc-56613e07eea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639665844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.639665844
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1908099201
Short name T575
Test name
Test status
Simulation time 840521555 ps
CPU time 21.57 seconds
Started Jun 04 12:24:32 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 196296 kb
Host smart-4decc274-da99-438b-8de7-e3cf72c58684
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908099201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1908099201
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2002600615
Short name T633
Test name
Test status
Simulation time 34192044 ps
CPU time 0.74 seconds
Started Jun 04 12:25:46 PM PDT 24
Finished Jun 04 12:25:49 PM PDT 24
Peak memory 195232 kb
Host smart-ad83c140-2189-40a5-88c0-e3508371c1d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002600615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2002600615
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2780471899
Short name T185
Test name
Test status
Simulation time 74177508 ps
CPU time 1.23 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:24:49 PM PDT 24
Peak memory 197988 kb
Host smart-c5aad5ad-03b1-4c39-9ee4-f101cf1c8d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780471899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2780471899
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2570989396
Short name T491
Test name
Test status
Simulation time 49164014 ps
CPU time 1.23 seconds
Started Jun 04 12:25:46 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 196916 kb
Host smart-334b5e5f-9a77-46fc-9b80-50e44f584d6a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570989396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2570989396
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.714569688
Short name T607
Test name
Test status
Simulation time 95077891 ps
CPU time 0.87 seconds
Started Jun 04 12:24:42 PM PDT 24
Finished Jun 04 12:24:45 PM PDT 24
Peak memory 194216 kb
Host smart-feae0742-7a82-4347-940c-26f28d38c6e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714569688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.714569688
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.28021263
Short name T114
Test name
Test status
Simulation time 42815074 ps
CPU time 1.01 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:24:40 PM PDT 24
Peak memory 195716 kb
Host smart-6cc6d2ac-3140-4b80-a56f-973ae2c8b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28021263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.28021263
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.817573880
Short name T642
Test name
Test status
Simulation time 82657274 ps
CPU time 1.37 seconds
Started Jun 04 12:25:46 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 195400 kb
Host smart-9d4a9523-d248-44d5-ad6e-8d75bb42657f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817573880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.817573880
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.558529605
Short name T187
Test name
Test status
Simulation time 113825233 ps
CPU time 1.51 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:24:43 PM PDT 24
Peak memory 197688 kb
Host smart-4508ac7d-6219-4930-86a0-7c0ad99e196d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558529605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.558529605
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1302097308
Short name T47
Test name
Test status
Simulation time 320387100 ps
CPU time 0.92 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:24:49 PM PDT 24
Peak memory 214904 kb
Host smart-cf727bec-1b77-4a8b-a895-cf69a7fc9fb4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302097308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1302097308
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1043711304
Short name T476
Test name
Test status
Simulation time 82647536 ps
CPU time 1.25 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:24:43 PM PDT 24
Peak memory 196700 kb
Host smart-fd0aa7f5-9d7c-480a-905f-e5ba0b1e731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043711304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1043711304
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3651394609
Short name T704
Test name
Test status
Simulation time 52543243 ps
CPU time 1.22 seconds
Started Jun 04 12:24:45 PM PDT 24
Finished Jun 04 12:24:48 PM PDT 24
Peak memory 196696 kb
Host smart-3ff00207-d8cc-403e-8542-02843736ee1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651394609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3651394609
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2284518810
Short name T20
Test name
Test status
Simulation time 48161923528 ps
CPU time 185.13 seconds
Started Jun 04 12:25:47 PM PDT 24
Finished Jun 04 12:28:54 PM PDT 24
Peak memory 197728 kb
Host smart-202b1437-95ee-407c-b9a7-436fe5852c26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284518810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2284518810
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.348678681
Short name T590
Test name
Test status
Simulation time 22894005 ps
CPU time 0.65 seconds
Started Jun 04 12:25:41 PM PDT 24
Finished Jun 04 12:25:43 PM PDT 24
Peak memory 193676 kb
Host smart-cd88644a-61e6-4b24-ba44-2d65d517db34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348678681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.348678681
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2042847716
Short name T180
Test name
Test status
Simulation time 206973997 ps
CPU time 0.92 seconds
Started Jun 04 12:25:47 PM PDT 24
Finished Jun 04 12:25:49 PM PDT 24
Peak memory 195600 kb
Host smart-c4160a6d-9021-47f2-8aee-16b035e70373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042847716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2042847716
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1137973806
Short name T297
Test name
Test status
Simulation time 394145241 ps
CPU time 11.22 seconds
Started Jun 04 12:25:38 PM PDT 24
Finished Jun 04 12:25:51 PM PDT 24
Peak memory 197816 kb
Host smart-9d34fcdf-d0cb-4d1b-b698-a94ff2309df7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137973806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1137973806
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1213833646
Short name T269
Test name
Test status
Simulation time 656342604 ps
CPU time 1.02 seconds
Started Jun 04 12:25:43 PM PDT 24
Finished Jun 04 12:25:45 PM PDT 24
Peak memory 196476 kb
Host smart-75e0abf5-bac4-4f9d-91f6-8a5b58cc98d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213833646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1213833646
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1699418793
Short name T571
Test name
Test status
Simulation time 28839390 ps
CPU time 0.66 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:25:39 PM PDT 24
Peak memory 194948 kb
Host smart-be52feb3-e31a-4860-b7ca-a02b6798db19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699418793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1699418793
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.4109928576
Short name T662
Test name
Test status
Simulation time 158448124 ps
CPU time 3.18 seconds
Started Jun 04 12:25:43 PM PDT 24
Finished Jun 04 12:25:47 PM PDT 24
Peak memory 197944 kb
Host smart-dc5806c6-b632-4d08-8fc3-0cebc9898886
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109928576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.4109928576
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1999790547
Short name T402
Test name
Test status
Simulation time 389776053 ps
CPU time 2.78 seconds
Started Jun 04 12:25:57 PM PDT 24
Finished Jun 04 12:26:01 PM PDT 24
Peak memory 196320 kb
Host smart-394958f5-f27f-4452-9327-e9a7301175a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999790547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1999790547
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.943758340
Short name T212
Test name
Test status
Simulation time 28219492 ps
CPU time 0.79 seconds
Started Jun 04 12:25:45 PM PDT 24
Finished Jun 04 12:25:47 PM PDT 24
Peak memory 195996 kb
Host smart-dafcaf34-407b-483b-b845-13bf55ddb592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943758340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.943758340
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1649819647
Short name T366
Test name
Test status
Simulation time 177532368 ps
CPU time 0.99 seconds
Started Jun 04 12:25:38 PM PDT 24
Finished Jun 04 12:25:40 PM PDT 24
Peak memory 195568 kb
Host smart-2fb7542b-7660-4bc4-b914-ddd634b4a900
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649819647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1649819647
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.778815321
Short name T348
Test name
Test status
Simulation time 933584837 ps
CPU time 5.39 seconds
Started Jun 04 12:25:57 PM PDT 24
Finished Jun 04 12:26:04 PM PDT 24
Peak memory 197776 kb
Host smart-2f155141-db67-4f83-a3f6-93dac409b82c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778815321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.778815321
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.268123149
Short name T515
Test name
Test status
Simulation time 195716381 ps
CPU time 1.33 seconds
Started Jun 04 12:25:40 PM PDT 24
Finished Jun 04 12:25:42 PM PDT 24
Peak memory 196612 kb
Host smart-e34a7980-d060-432e-8cec-9a76345deb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268123149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.268123149
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3489079685
Short name T545
Test name
Test status
Simulation time 57199172 ps
CPU time 0.87 seconds
Started Jun 04 12:25:51 PM PDT 24
Finished Jun 04 12:25:54 PM PDT 24
Peak memory 195124 kb
Host smart-95fdc221-fb96-4425-b409-ba4313362b1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489079685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3489079685
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2720694020
Short name T306
Test name
Test status
Simulation time 6385379156 ps
CPU time 146.46 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:28:05 PM PDT 24
Peak memory 197992 kb
Host smart-2571cd02-4ee6-49b3-a58d-01f2e34f9ce5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720694020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2720694020
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3662962978
Short name T553
Test name
Test status
Simulation time 209072524535 ps
CPU time 1212.71 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:45:51 PM PDT 24
Peak memory 198068 kb
Host smart-dcd3e1d3-c75a-48e1-b2ec-5d9472fba5c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3662962978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.3662962978
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.827209007
Short name T656
Test name
Test status
Simulation time 121744190 ps
CPU time 0.55 seconds
Started Jun 04 12:25:45 PM PDT 24
Finished Jun 04 12:25:47 PM PDT 24
Peak memory 194440 kb
Host smart-0fc96ac8-8e13-4580-9c6b-7b9f6415f551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827209007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.827209007
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3694795347
Short name T147
Test name
Test status
Simulation time 25465076 ps
CPU time 0.69 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:25:39 PM PDT 24
Peak memory 195108 kb
Host smart-bd43cc64-2fec-47cf-8917-f3b46a406a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694795347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3694795347
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3757256224
Short name T461
Test name
Test status
Simulation time 830164783 ps
CPU time 13.86 seconds
Started Jun 04 12:25:35 PM PDT 24
Finished Jun 04 12:25:49 PM PDT 24
Peak memory 196684 kb
Host smart-4147d0a3-c785-4d36-851a-ad0ce58877ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757256224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3757256224
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2939314986
Short name T475
Test name
Test status
Simulation time 60336462 ps
CPU time 0.84 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:25:55 PM PDT 24
Peak memory 195872 kb
Host smart-ab705f79-3360-4c2b-b23b-ca918185cd91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939314986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2939314986
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1143421555
Short name T665
Test name
Test status
Simulation time 314302654 ps
CPU time 1.26 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:25:39 PM PDT 24
Peak memory 196980 kb
Host smart-02119f10-d052-4ddd-a99c-e2c1622c5227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143421555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1143421555
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.953258853
Short name T620
Test name
Test status
Simulation time 232040708 ps
CPU time 1.32 seconds
Started Jun 04 12:25:33 PM PDT 24
Finished Jun 04 12:25:36 PM PDT 24
Peak memory 196492 kb
Host smart-d0db4ad8-6830-42a2-9f23-1e4cd89b104f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953258853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.953258853
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.4205684685
Short name T27
Test name
Test status
Simulation time 32825011 ps
CPU time 0.95 seconds
Started Jun 04 12:25:36 PM PDT 24
Finished Jun 04 12:25:38 PM PDT 24
Peak memory 195488 kb
Host smart-370f02a2-1e89-4a2a-ab4d-d89215be26b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205684685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.4205684685
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2008458633
Short name T265
Test name
Test status
Simulation time 30547462 ps
CPU time 0.77 seconds
Started Jun 04 12:25:38 PM PDT 24
Finished Jun 04 12:25:40 PM PDT 24
Peak memory 195416 kb
Host smart-3e70c67f-d20b-4e3e-9ea9-7c7cb1fca5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008458633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2008458633
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.849565534
Short name T570
Test name
Test status
Simulation time 173447542 ps
CPU time 0.99 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:25:39 PM PDT 24
Peak memory 195940 kb
Host smart-a43f5a67-fd73-4092-aa92-955ca41ede53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849565534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.849565534
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1574623675
Short name T302
Test name
Test status
Simulation time 465018418 ps
CPU time 5.34 seconds
Started Jun 04 12:25:48 PM PDT 24
Finished Jun 04 12:25:55 PM PDT 24
Peak memory 197868 kb
Host smart-12b3f328-a6d0-4b60-8cd4-2e6206312657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574623675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1574623675
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2239041335
Short name T445
Test name
Test status
Simulation time 173429576 ps
CPU time 0.9 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:25:39 PM PDT 24
Peak memory 196860 kb
Host smart-5d339b34-682d-4922-baf3-84ecda2598e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239041335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2239041335
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3938438940
Short name T700
Test name
Test status
Simulation time 188680483 ps
CPU time 1.23 seconds
Started Jun 04 12:25:37 PM PDT 24
Finished Jun 04 12:25:39 PM PDT 24
Peak memory 196760 kb
Host smart-0e1bbd8e-bd9f-4a99-a086-45a038cf8ff2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938438940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3938438940
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4097125974
Short name T384
Test name
Test status
Simulation time 6589366465 ps
CPU time 88.51 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:27:22 PM PDT 24
Peak memory 197972 kb
Host smart-9c19e2cd-d463-41b7-8130-4472371ab3ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097125974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4097125974
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2888947748
Short name T31
Test name
Test status
Simulation time 525347690840 ps
CPU time 1296.78 seconds
Started Jun 04 12:25:50 PM PDT 24
Finished Jun 04 12:47:29 PM PDT 24
Peak memory 198128 kb
Host smart-26e5f776-d756-4a0e-a5f3-7216fc341286
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2888947748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2888947748
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3106166901
Short name T218
Test name
Test status
Simulation time 12774980 ps
CPU time 0.56 seconds
Started Jun 04 12:25:59 PM PDT 24
Finished Jun 04 12:26:01 PM PDT 24
Peak memory 193744 kb
Host smart-f1490576-2524-4340-8778-4e75d1cba8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106166901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3106166901
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1591923027
Short name T643
Test name
Test status
Simulation time 52097725 ps
CPU time 0.86 seconds
Started Jun 04 12:25:49 PM PDT 24
Finished Jun 04 12:25:51 PM PDT 24
Peak memory 196244 kb
Host smart-2295b215-9885-456f-9c5b-4c01d2848911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591923027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1591923027
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2999484813
Short name T370
Test name
Test status
Simulation time 126689986 ps
CPU time 3.88 seconds
Started Jun 04 12:25:47 PM PDT 24
Finished Jun 04 12:25:53 PM PDT 24
Peak memory 195736 kb
Host smart-6ba045f7-6012-485f-aa80-b7200c1b9244
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999484813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2999484813
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2018584270
Short name T228
Test name
Test status
Simulation time 68532103 ps
CPU time 0.95 seconds
Started Jun 04 12:25:46 PM PDT 24
Finished Jun 04 12:25:48 PM PDT 24
Peak memory 197728 kb
Host smart-44047aa1-359a-4e9c-bc6b-ba7062faf530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018584270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2018584270
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2467141850
Short name T511
Test name
Test status
Simulation time 1195256975 ps
CPU time 1.3 seconds
Started Jun 04 12:25:49 PM PDT 24
Finished Jun 04 12:25:52 PM PDT 24
Peak memory 197860 kb
Host smart-e22bb996-ed91-4c92-9cf8-f91df4853e8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467141850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2467141850
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3062499560
Short name T429
Test name
Test status
Simulation time 35499599 ps
CPU time 1.53 seconds
Started Jun 04 12:25:54 PM PDT 24
Finished Jun 04 12:25:57 PM PDT 24
Peak memory 196728 kb
Host smart-b045c3ee-6dbc-480d-b74b-9e7c8a037228
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062499560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3062499560
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3267444571
Short name T119
Test name
Test status
Simulation time 284238013 ps
CPU time 1.59 seconds
Started Jun 04 12:25:54 PM PDT 24
Finished Jun 04 12:25:57 PM PDT 24
Peak memory 196608 kb
Host smart-270cc0b0-1e25-4341-94bd-0d332f6be881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267444571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3267444571
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3500980280
Short name T563
Test name
Test status
Simulation time 21180895 ps
CPU time 0.67 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 194192 kb
Host smart-0541cebe-785a-461b-b235-48ea0db2bbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500980280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3500980280
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.4020281987
Short name T260
Test name
Test status
Simulation time 251396739 ps
CPU time 1.23 seconds
Started Jun 04 12:25:46 PM PDT 24
Finished Jun 04 12:25:49 PM PDT 24
Peak memory 197196 kb
Host smart-218487dc-1ce8-4619-bc92-df83b0ce6a5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020281987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.4020281987
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_smoke.4144810956
Short name T464
Test name
Test status
Simulation time 352809439 ps
CPU time 1.08 seconds
Started Jun 04 12:25:50 PM PDT 24
Finished Jun 04 12:25:52 PM PDT 24
Peak memory 195684 kb
Host smart-edde6e2e-8d38-45f5-b320-c3093de52199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144810956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.4144810956
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2776660689
Short name T534
Test name
Test status
Simulation time 60277543 ps
CPU time 1.05 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:25:54 PM PDT 24
Peak memory 195544 kb
Host smart-33f78197-9865-47c7-a2f7-09c782d9280e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776660689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2776660689
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2731516764
Short name T513
Test name
Test status
Simulation time 25038009640 ps
CPU time 193.16 seconds
Started Jun 04 12:25:45 PM PDT 24
Finished Jun 04 12:28:59 PM PDT 24
Peak memory 198092 kb
Host smart-5cca8a2c-9e9d-4249-bc0c-429b99699e15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731516764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2731516764
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.2113185243
Short name T352
Test name
Test status
Simulation time 108862322940 ps
CPU time 2413.09 seconds
Started Jun 04 12:25:58 PM PDT 24
Finished Jun 04 01:06:13 PM PDT 24
Peak memory 198064 kb
Host smart-1dddfe13-b07f-42de-b01d-ae54af72c33f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2113185243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.2113185243
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.4044527751
Short name T38
Test name
Test status
Simulation time 14133087 ps
CPU time 0.54 seconds
Started Jun 04 12:25:49 PM PDT 24
Finished Jun 04 12:25:51 PM PDT 24
Peak memory 193716 kb
Host smart-f25a5edc-b2ba-48be-8431-01c3d3794235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044527751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.4044527751
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.164729891
Short name T377
Test name
Test status
Simulation time 25839118 ps
CPU time 0.66 seconds
Started Jun 04 12:25:58 PM PDT 24
Finished Jun 04 12:26:00 PM PDT 24
Peak memory 193976 kb
Host smart-44f88369-a40d-443a-a0fd-28809f6b68d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164729891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.164729891
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4037694549
Short name T268
Test name
Test status
Simulation time 2913441360 ps
CPU time 20.36 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:26:18 PM PDT 24
Peak memory 196896 kb
Host smart-03eb1e23-de12-4f9e-9415-a8b50b3d86a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037694549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4037694549
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.649640992
Short name T387
Test name
Test status
Simulation time 58948825 ps
CPU time 0.9 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 196868 kb
Host smart-cfba989b-f45d-4b48-a8b4-9e44a796c932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649640992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.649640992
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2434820467
Short name T179
Test name
Test status
Simulation time 39752325 ps
CPU time 0.74 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 195964 kb
Host smart-4a89ec1e-3e75-4a8a-b9ec-b32cb898cbfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434820467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2434820467
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.4184403810
Short name T11
Test name
Test status
Simulation time 65272124 ps
CPU time 2.8 seconds
Started Jun 04 12:25:59 PM PDT 24
Finished Jun 04 12:26:03 PM PDT 24
Peak memory 197928 kb
Host smart-686c1dc0-bd72-43e7-8876-67534f26b018
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184403810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.4184403810
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2890157141
Short name T281
Test name
Test status
Simulation time 208194863 ps
CPU time 3.18 seconds
Started Jun 04 12:25:48 PM PDT 24
Finished Jun 04 12:25:53 PM PDT 24
Peak memory 196928 kb
Host smart-9453510e-40d5-4aaa-9d8a-14c38444676d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890157141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2890157141
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3002433751
Short name T705
Test name
Test status
Simulation time 177727201 ps
CPU time 0.96 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:25:54 PM PDT 24
Peak memory 195628 kb
Host smart-669dfa96-8cff-4aef-ab4f-5cabd6b69def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002433751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3002433751
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2591355844
Short name T695
Test name
Test status
Simulation time 17650518 ps
CPU time 0.74 seconds
Started Jun 04 12:25:45 PM PDT 24
Finished Jun 04 12:25:47 PM PDT 24
Peak memory 195928 kb
Host smart-5252dc14-524c-4115-8f8e-041e4797e98b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591355844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2591355844
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2099846249
Short name T677
Test name
Test status
Simulation time 1241496090 ps
CPU time 3.14 seconds
Started Jun 04 12:25:58 PM PDT 24
Finished Jun 04 12:26:03 PM PDT 24
Peak memory 197564 kb
Host smart-04cf8635-654b-49a5-ae39-d41b032aca04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099846249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2099846249
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1480786661
Short name T182
Test name
Test status
Simulation time 85247608 ps
CPU time 1.24 seconds
Started Jun 04 12:25:54 PM PDT 24
Finished Jun 04 12:25:57 PM PDT 24
Peak memory 196976 kb
Host smart-627f0c3d-d69e-4d32-bf6e-70816e4f564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480786661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1480786661
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.815728527
Short name T343
Test name
Test status
Simulation time 33942699 ps
CPU time 0.94 seconds
Started Jun 04 12:25:49 PM PDT 24
Finished Jun 04 12:25:51 PM PDT 24
Peak memory 196936 kb
Host smart-94145ab0-c41e-4df8-b0fc-8d27004480b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815728527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.815728527
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3886560020
Short name T320
Test name
Test status
Simulation time 161027579828 ps
CPU time 140.29 seconds
Started Jun 04 12:25:58 PM PDT 24
Finished Jun 04 12:28:20 PM PDT 24
Peak memory 198092 kb
Host smart-212a03ce-37e7-4ce2-b876-8c35b93e5382
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886560020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3886560020
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3526265553
Short name T63
Test name
Test status
Simulation time 28440831386 ps
CPU time 689.24 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:37:23 PM PDT 24
Peak memory 198112 kb
Host smart-bf97750a-5923-440d-ba49-196b356115ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3526265553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3526265553
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1128968663
Short name T638
Test name
Test status
Simulation time 21181626 ps
CPU time 0.57 seconds
Started Jun 04 12:25:58 PM PDT 24
Finished Jun 04 12:26:00 PM PDT 24
Peak memory 193940 kb
Host smart-3a7f4373-d0cd-4b36-98fd-2c96642b089f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128968663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1128968663
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.952687155
Short name T274
Test name
Test status
Simulation time 28442173 ps
CPU time 0.84 seconds
Started Jun 04 12:25:49 PM PDT 24
Finished Jun 04 12:25:52 PM PDT 24
Peak memory 196392 kb
Host smart-196efe29-90c2-42c7-9c12-fb49cf4d4edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952687155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.952687155
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.120433395
Short name T430
Test name
Test status
Simulation time 271260138 ps
CPU time 6.54 seconds
Started Jun 04 12:25:47 PM PDT 24
Finished Jun 04 12:25:56 PM PDT 24
Peak memory 196692 kb
Host smart-85f72ae5-8fe1-41c8-9545-62e49acfbd2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120433395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.120433395
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1858125638
Short name T484
Test name
Test status
Simulation time 52457963 ps
CPU time 0.84 seconds
Started Jun 04 12:25:48 PM PDT 24
Finished Jun 04 12:25:51 PM PDT 24
Peak memory 196384 kb
Host smart-556207e7-69b3-49f9-b686-4586c5097a59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858125638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1858125638
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2719504307
Short name T412
Test name
Test status
Simulation time 35864369 ps
CPU time 0.85 seconds
Started Jun 04 12:25:58 PM PDT 24
Finished Jun 04 12:26:01 PM PDT 24
Peak memory 196264 kb
Host smart-867093ff-2342-4285-bfb5-9c5a90d5b496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719504307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2719504307
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1544290938
Short name T200
Test name
Test status
Simulation time 1434055529 ps
CPU time 4 seconds
Started Jun 04 12:25:59 PM PDT 24
Finished Jun 04 12:26:05 PM PDT 24
Peak memory 197888 kb
Host smart-e257ed68-7079-44eb-8db0-6f29f107a67a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544290938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1544290938
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1555578075
Short name T505
Test name
Test status
Simulation time 179545463 ps
CPU time 2.05 seconds
Started Jun 04 12:25:47 PM PDT 24
Finished Jun 04 12:25:51 PM PDT 24
Peak memory 196112 kb
Host smart-e095ec62-057c-4b15-a85a-75f480b0d5b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555578075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1555578075
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1666361340
Short name T616
Test name
Test status
Simulation time 51332856 ps
CPU time 1.14 seconds
Started Jun 04 12:25:47 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 195964 kb
Host smart-a0035d04-2dba-43ed-aa2b-21342993c634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666361340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1666361340
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.244278491
Short name T108
Test name
Test status
Simulation time 38689676 ps
CPU time 0.87 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:25:55 PM PDT 24
Peak memory 196320 kb
Host smart-bfb8d1bf-cb93-4760-82c6-55b9f9a60e4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244278491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.244278491
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2825655381
Short name T138
Test name
Test status
Simulation time 234703992 ps
CPU time 6 seconds
Started Jun 04 12:25:59 PM PDT 24
Finished Jun 04 12:26:06 PM PDT 24
Peak memory 197836 kb
Host smart-bc27be06-a864-4741-9863-aca204451c47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825655381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2825655381
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1324965254
Short name T259
Test name
Test status
Simulation time 55510213 ps
CPU time 0.89 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:25:55 PM PDT 24
Peak memory 196224 kb
Host smart-7a0ff60f-c3c9-4ff8-8e06-7d190a8db339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324965254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1324965254
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3146768367
Short name T66
Test name
Test status
Simulation time 85376017 ps
CPU time 0.82 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 195300 kb
Host smart-9ca0928e-e93d-4e32-a462-85ec112faceb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146768367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3146768367
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4004369700
Short name T226
Test name
Test status
Simulation time 15743339084 ps
CPU time 41.99 seconds
Started Jun 04 12:25:58 PM PDT 24
Finished Jun 04 12:26:42 PM PDT 24
Peak memory 198088 kb
Host smart-e3f329b8-0069-4735-aad5-b0148be321ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004369700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4004369700
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3109261568
Short name T189
Test name
Test status
Simulation time 23651812 ps
CPU time 0.56 seconds
Started Jun 04 12:25:55 PM PDT 24
Finished Jun 04 12:25:57 PM PDT 24
Peak memory 194400 kb
Host smart-9e15d337-651b-41f7-98eb-9d6230ba973a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109261568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3109261568
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.4256258732
Short name T568
Test name
Test status
Simulation time 54495872 ps
CPU time 0.72 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:59 PM PDT 24
Peak memory 195108 kb
Host smart-944a12fe-af1d-461f-9bee-3770243ce484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256258732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.4256258732
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1635522276
Short name T431
Test name
Test status
Simulation time 64988127 ps
CPU time 2.98 seconds
Started Jun 04 12:25:55 PM PDT 24
Finished Jun 04 12:25:59 PM PDT 24
Peak memory 196520 kb
Host smart-9d3e6ea1-f27d-4170-b3d1-806923599c45
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635522276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1635522276
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3497149660
Short name T174
Test name
Test status
Simulation time 83028597 ps
CPU time 1.05 seconds
Started Jun 04 12:25:57 PM PDT 24
Finished Jun 04 12:25:59 PM PDT 24
Peak memory 197560 kb
Host smart-a410bea3-9496-453f-acdc-5db902238588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497149660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3497149660
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.4021838383
Short name T166
Test name
Test status
Simulation time 50531553 ps
CPU time 0.75 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 194128 kb
Host smart-918316c5-50a7-462b-9a2d-5cd11306a735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021838383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.4021838383
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3425540691
Short name T699
Test name
Test status
Simulation time 45190822 ps
CPU time 1.58 seconds
Started Jun 04 12:26:05 PM PDT 24
Finished Jun 04 12:26:09 PM PDT 24
Peak memory 197924 kb
Host smart-333b24f9-e825-40d7-ae0e-3224d5a9341b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425540691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3425540691
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.4191851991
Short name T150
Test name
Test status
Simulation time 159233279 ps
CPU time 1.1 seconds
Started Jun 04 12:25:54 PM PDT 24
Finished Jun 04 12:25:57 PM PDT 24
Peak memory 196240 kb
Host smart-fee64a29-0ce4-463c-84ad-62696a860d9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191851991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.4191851991
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3007636028
Short name T403
Test name
Test status
Simulation time 116236843 ps
CPU time 1.19 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:59 PM PDT 24
Peak memory 196356 kb
Host smart-8e8aaea9-e093-4562-be5b-fa73fbe1b0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007636028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3007636028
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.983186632
Short name T664
Test name
Test status
Simulation time 81978136 ps
CPU time 0.63 seconds
Started Jun 04 12:25:59 PM PDT 24
Finished Jun 04 12:26:01 PM PDT 24
Peak memory 194212 kb
Host smart-4802a12e-8a05-46e4-9d66-ba189c3f478f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983186632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.983186632
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.892157317
Short name T488
Test name
Test status
Simulation time 1818950790 ps
CPU time 3.07 seconds
Started Jun 04 12:25:55 PM PDT 24
Finished Jun 04 12:26:00 PM PDT 24
Peak memory 197820 kb
Host smart-f16f8c60-1baf-4cbd-a814-28956ce22482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892157317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.892157317
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.883295067
Short name T95
Test name
Test status
Simulation time 51311390 ps
CPU time 1.34 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:59 PM PDT 24
Peak memory 197856 kb
Host smart-705af4c2-4f0b-4d74-afd6-7c5b85935507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883295067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.883295067
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1804268407
Short name T254
Test name
Test status
Simulation time 126252553 ps
CPU time 1.25 seconds
Started Jun 04 12:25:58 PM PDT 24
Finished Jun 04 12:26:01 PM PDT 24
Peak memory 195652 kb
Host smart-f7c31835-5ff6-4bfc-88e5-fb231b7ba694
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804268407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1804268407
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2622283000
Short name T618
Test name
Test status
Simulation time 9173489326 ps
CPU time 125.17 seconds
Started Jun 04 12:26:04 PM PDT 24
Finished Jun 04 12:28:10 PM PDT 24
Peak memory 198012 kb
Host smart-c24eabf8-f84e-45d8-9741-1205d2348a25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622283000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2622283000
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.654970353
Short name T652
Test name
Test status
Simulation time 18468774 ps
CPU time 0.55 seconds
Started Jun 04 12:25:55 PM PDT 24
Finished Jun 04 12:25:57 PM PDT 24
Peak memory 193708 kb
Host smart-3867df9f-d7ef-4574-8ac2-6482316132f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654970353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.654970353
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2044823375
Short name T514
Test name
Test status
Simulation time 40924998 ps
CPU time 0.84 seconds
Started Jun 04 12:26:03 PM PDT 24
Finished Jun 04 12:26:04 PM PDT 24
Peak memory 195196 kb
Host smart-7fc3f775-8174-433d-8f79-1f93aae1760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044823375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2044823375
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1826611630
Short name T298
Test name
Test status
Simulation time 780246600 ps
CPU time 22.05 seconds
Started Jun 04 12:26:06 PM PDT 24
Finished Jun 04 12:26:30 PM PDT 24
Peak memory 196452 kb
Host smart-4277b77c-a411-44ec-8638-01a84750c5db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826611630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1826611630
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1896813669
Short name T663
Test name
Test status
Simulation time 98843311 ps
CPU time 0.78 seconds
Started Jun 04 12:26:04 PM PDT 24
Finished Jun 04 12:26:06 PM PDT 24
Peak memory 195804 kb
Host smart-2eaac770-d2d7-4a5e-a386-126d3b552283
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896813669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1896813669
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2848406677
Short name T223
Test name
Test status
Simulation time 49651104 ps
CPU time 1.27 seconds
Started Jun 04 12:26:26 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 196452 kb
Host smart-4126c4eb-d065-442d-b1ab-9f16f65b1423
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848406677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2848406677
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3316971504
Short name T181
Test name
Test status
Simulation time 49627749 ps
CPU time 1.82 seconds
Started Jun 04 12:26:26 PM PDT 24
Finished Jun 04 12:26:30 PM PDT 24
Peak memory 195668 kb
Host smart-f5b75187-b56d-4a7b-a0e9-fc03111b3f74
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316971504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3316971504
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1192691702
Short name T432
Test name
Test status
Simulation time 113235728 ps
CPU time 2.42 seconds
Started Jun 04 12:26:27 PM PDT 24
Finished Jun 04 12:26:32 PM PDT 24
Peak memory 197040 kb
Host smart-9fa89af0-f62e-48ed-9550-456fc0d9c865
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192691702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1192691702
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2948113558
Short name T428
Test name
Test status
Simulation time 32897622 ps
CPU time 0.85 seconds
Started Jun 04 12:26:05 PM PDT 24
Finished Jun 04 12:26:08 PM PDT 24
Peak memory 196344 kb
Host smart-12beb98a-a14b-4eae-9ee0-cfb40c0c3b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948113558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2948113558
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3001551213
Short name T205
Test name
Test status
Simulation time 84756058 ps
CPU time 0.89 seconds
Started Jun 04 12:26:26 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 195808 kb
Host smart-2da23a4f-b5e4-4c9a-9fbc-8c1bd3f159ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001551213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3001551213
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3738327411
Short name T483
Test name
Test status
Simulation time 3722737353 ps
CPU time 5.33 seconds
Started Jun 04 12:27:09 PM PDT 24
Finished Jun 04 12:27:16 PM PDT 24
Peak memory 196644 kb
Host smart-3816729d-5a27-4b0f-8bd2-e963bfca73b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738327411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3738327411
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.561292734
Short name T369
Test name
Test status
Simulation time 146475483 ps
CPU time 0.92 seconds
Started Jun 04 12:26:06 PM PDT 24
Finished Jun 04 12:26:08 PM PDT 24
Peak memory 197108 kb
Host smart-47ccc22a-8fa7-42b8-9ec2-39d71c357558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561292734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.561292734
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2783947958
Short name T164
Test name
Test status
Simulation time 35129586 ps
CPU time 1.02 seconds
Started Jun 04 12:25:59 PM PDT 24
Finished Jun 04 12:26:01 PM PDT 24
Peak memory 195432 kb
Host smart-1929e188-e286-4af2-aa36-2ae351fc231d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783947958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2783947958
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2227919502
Short name T4
Test name
Test status
Simulation time 9360209614 ps
CPU time 56.06 seconds
Started Jun 04 12:27:08 PM PDT 24
Finished Jun 04 12:28:06 PM PDT 24
Peak memory 196060 kb
Host smart-9473920d-fbfb-4fc4-8b25-55f7d6341d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227919502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2227919502
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.747674341
Short name T18
Test name
Test status
Simulation time 162460356441 ps
CPU time 561.05 seconds
Started Jun 04 12:26:04 PM PDT 24
Finished Jun 04 12:35:26 PM PDT 24
Peak memory 198092 kb
Host smart-cf382f7a-453d-4cda-84db-1e732c5358b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=747674341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.747674341
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3082167875
Short name T99
Test name
Test status
Simulation time 21641833 ps
CPU time 0.61 seconds
Started Jun 04 12:27:08 PM PDT 24
Finished Jun 04 12:27:11 PM PDT 24
Peak memory 192424 kb
Host smart-ce7a47e5-ed99-4068-91d6-9a26cd891152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082167875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3082167875
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2567920026
Short name T206
Test name
Test status
Simulation time 49643422 ps
CPU time 0.76 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 195112 kb
Host smart-6574c985-f061-434b-9318-ca66dcc269c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567920026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2567920026
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1854873583
Short name T293
Test name
Test status
Simulation time 373215804 ps
CPU time 12.28 seconds
Started Jun 04 12:26:04 PM PDT 24
Finished Jun 04 12:26:17 PM PDT 24
Peak memory 197796 kb
Host smart-4fcb7e63-1247-41da-959b-101a2f4b5240
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854873583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1854873583
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3929968746
Short name T279
Test name
Test status
Simulation time 81089451 ps
CPU time 1.01 seconds
Started Jun 04 12:26:05 PM PDT 24
Finished Jun 04 12:26:08 PM PDT 24
Peak memory 196412 kb
Host smart-4e43f305-62f4-439c-a2c1-556249aedfe1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929968746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3929968746
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3244847641
Short name T486
Test name
Test status
Simulation time 18828314 ps
CPU time 0.68 seconds
Started Jun 04 12:26:04 PM PDT 24
Finished Jun 04 12:26:06 PM PDT 24
Peak memory 196024 kb
Host smart-7de2dde8-5a5a-47ba-a624-f1bd044ec622
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244847641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3244847641
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.949818005
Short name T470
Test name
Test status
Simulation time 238841827 ps
CPU time 3.25 seconds
Started Jun 04 12:27:08 PM PDT 24
Finished Jun 04 12:27:14 PM PDT 24
Peak memory 193952 kb
Host smart-6e878829-8ca7-4c60-8369-8eab41d80cdf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949818005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.949818005
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3888096831
Short name T264
Test name
Test status
Simulation time 159490673 ps
CPU time 3.39 seconds
Started Jun 04 12:25:54 PM PDT 24
Finished Jun 04 12:25:59 PM PDT 24
Peak memory 197916 kb
Host smart-0f00f84d-bcdc-4a24-949a-a65e975d7bf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888096831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3888096831
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2010203954
Short name T692
Test name
Test status
Simulation time 873708433 ps
CPU time 1.03 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:59 PM PDT 24
Peak memory 195620 kb
Host smart-b75a5f7b-a766-4ad6-ac45-339f5b99c00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010203954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2010203954
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.421490310
Short name T625
Test name
Test status
Simulation time 352696191 ps
CPU time 1.22 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 196940 kb
Host smart-76606a3a-ab45-4916-88d2-fbfebfc69595
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421490310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.421490310
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.83543931
Short name T591
Test name
Test status
Simulation time 119847940 ps
CPU time 2.75 seconds
Started Jun 04 12:26:03 PM PDT 24
Finished Jun 04 12:26:07 PM PDT 24
Peak memory 197852 kb
Host smart-cdeaaa2b-d990-43bb-ae4b-eaeb8e3161c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83543931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand
om_long_reg_writes_reg_reads.83543931
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1525868677
Short name T698
Test name
Test status
Simulation time 144764183 ps
CPU time 1.18 seconds
Started Jun 04 12:25:55 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 195656 kb
Host smart-595c4212-2527-4ac3-bd9c-5f4a82ea553f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525868677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1525868677
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.216929295
Short name T454
Test name
Test status
Simulation time 140289670 ps
CPU time 1.05 seconds
Started Jun 04 12:26:26 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 196116 kb
Host smart-2fe0f0d3-8486-46e9-ac7d-9aec3e5a3c26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216929295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.216929295
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.4151545788
Short name T246
Test name
Test status
Simulation time 4117474447 ps
CPU time 112.6 seconds
Started Jun 04 12:25:59 PM PDT 24
Finished Jun 04 12:27:53 PM PDT 24
Peak memory 197996 kb
Host smart-d2f4a2a6-ddee-40ed-8a29-80c2f6e3b113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151545788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.4151545788
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3082903823
Short name T436
Test name
Test status
Simulation time 33900298 ps
CPU time 0.59 seconds
Started Jun 04 12:26:07 PM PDT 24
Finished Jun 04 12:26:10 PM PDT 24
Peak memory 193732 kb
Host smart-2e3437a7-49b0-49fe-b0e4-2e695fa4fe04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082903823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3082903823
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1210804622
Short name T112
Test name
Test status
Simulation time 35826920 ps
CPU time 0.64 seconds
Started Jun 04 12:26:06 PM PDT 24
Finished Jun 04 12:26:09 PM PDT 24
Peak memory 194676 kb
Host smart-41322207-3002-4a10-a0b5-f6b6bd58ebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210804622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1210804622
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3277055271
Short name T374
Test name
Test status
Simulation time 2804437565 ps
CPU time 21.05 seconds
Started Jun 04 12:26:06 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 197400 kb
Host smart-6b95ac36-2643-4525-82a0-b58749bcd4ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277055271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3277055271
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.319465391
Short name T582
Test name
Test status
Simulation time 67414994 ps
CPU time 0.96 seconds
Started Jun 04 12:26:05 PM PDT 24
Finished Jun 04 12:26:08 PM PDT 24
Peak memory 196868 kb
Host smart-add13457-9306-45e7-9231-cb33d714785f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319465391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.319465391
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.715326442
Short name T500
Test name
Test status
Simulation time 22210081 ps
CPU time 0.67 seconds
Started Jun 04 12:27:13 PM PDT 24
Finished Jun 04 12:27:15 PM PDT 24
Peak memory 194896 kb
Host smart-4bb8470d-ca83-482d-841a-907d27fd903d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715326442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.715326442
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2501519179
Short name T198
Test name
Test status
Simulation time 462062531 ps
CPU time 3.52 seconds
Started Jun 04 12:26:10 PM PDT 24
Finished Jun 04 12:26:15 PM PDT 24
Peak memory 197920 kb
Host smart-9c415ccc-8945-49cd-849d-aca4bcebb00a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501519179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2501519179
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3071870428
Short name T536
Test name
Test status
Simulation time 438711150 ps
CPU time 3.53 seconds
Started Jun 04 12:26:13 PM PDT 24
Finished Jun 04 12:26:19 PM PDT 24
Peak memory 197300 kb
Host smart-a114024c-1b39-41c3-b053-29cc084a0100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071870428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3071870428
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.378972256
Short name T653
Test name
Test status
Simulation time 94064807 ps
CPU time 0.77 seconds
Started Jun 04 12:26:02 PM PDT 24
Finished Jun 04 12:26:04 PM PDT 24
Peak memory 195448 kb
Host smart-251c4258-4af9-449e-aa59-01dbb2077974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378972256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.378972256
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.847538391
Short name T626
Test name
Test status
Simulation time 97679388 ps
CPU time 1.01 seconds
Started Jun 04 12:25:56 PM PDT 24
Finished Jun 04 12:25:59 PM PDT 24
Peak memory 196056 kb
Host smart-845cb810-91a3-4510-a6ae-0055960b62e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847538391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.847538391
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3692013809
Short name T581
Test name
Test status
Simulation time 2263801326 ps
CPU time 5.12 seconds
Started Jun 04 12:26:08 PM PDT 24
Finished Jun 04 12:26:15 PM PDT 24
Peak memory 197940 kb
Host smart-aa816037-891f-4c38-a6fc-f9da3135eedc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692013809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3692013809
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3909137753
Short name T660
Test name
Test status
Simulation time 292235034 ps
CPU time 1.33 seconds
Started Jun 04 12:27:08 PM PDT 24
Finished Jun 04 12:27:12 PM PDT 24
Peak memory 194080 kb
Host smart-586d3d9b-8e90-4eb0-a545-f738db4c52e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909137753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3909137753
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.832803291
Short name T153
Test name
Test status
Simulation time 81362950 ps
CPU time 0.66 seconds
Started Jun 04 12:26:27 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 194068 kb
Host smart-b8834d6b-8a81-4f42-b9bd-b6f2fa072cef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832803291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.832803291
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2669912003
Short name T611
Test name
Test status
Simulation time 26800362262 ps
CPU time 193.52 seconds
Started Jun 04 12:26:05 PM PDT 24
Finished Jun 04 12:29:21 PM PDT 24
Peak memory 198000 kb
Host smart-7e15688a-cabc-46fa-8791-81c4e77b4e1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669912003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2669912003
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1575457716
Short name T361
Test name
Test status
Simulation time 13576574 ps
CPU time 0.54 seconds
Started Jun 04 12:26:13 PM PDT 24
Finished Jun 04 12:26:14 PM PDT 24
Peak memory 194432 kb
Host smart-4746b1dc-35a2-4f2a-ac9d-1527b651d4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575457716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1575457716
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.567177218
Short name T675
Test name
Test status
Simulation time 30944170 ps
CPU time 0.72 seconds
Started Jun 04 12:26:06 PM PDT 24
Finished Jun 04 12:26:08 PM PDT 24
Peak memory 195184 kb
Host smart-82fc218c-e892-4c42-8f3d-cb979301f279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567177218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.567177218
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3803556075
Short name T237
Test name
Test status
Simulation time 3024381006 ps
CPU time 25.73 seconds
Started Jun 04 12:26:04 PM PDT 24
Finished Jun 04 12:26:31 PM PDT 24
Peak memory 197296 kb
Host smart-a42c174d-2737-4f39-a241-9ca37e894fe6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803556075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3803556075
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1044351767
Short name T657
Test name
Test status
Simulation time 78398595 ps
CPU time 1.03 seconds
Started Jun 04 12:26:06 PM PDT 24
Finished Jun 04 12:26:08 PM PDT 24
Peak memory 196520 kb
Host smart-b0869267-3ea5-48e4-849b-e1df551d308b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044351767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1044351767
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1760241682
Short name T261
Test name
Test status
Simulation time 68035426 ps
CPU time 0.76 seconds
Started Jun 04 12:26:11 PM PDT 24
Finished Jun 04 12:26:13 PM PDT 24
Peak memory 195312 kb
Host smart-db8eb912-c5be-42db-8142-9f674048b4cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760241682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1760241682
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4206064308
Short name T676
Test name
Test status
Simulation time 73585997 ps
CPU time 1.4 seconds
Started Jun 04 12:26:05 PM PDT 24
Finished Jun 04 12:26:09 PM PDT 24
Peak memory 196324 kb
Host smart-e7de2268-c650-4a57-8947-57aa87120d7c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206064308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4206064308
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1481622599
Short name T531
Test name
Test status
Simulation time 520200970 ps
CPU time 2.83 seconds
Started Jun 04 12:26:06 PM PDT 24
Finished Jun 04 12:26:11 PM PDT 24
Peak memory 196388 kb
Host smart-60527df1-7952-406f-ae81-b1af0dd0212e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481622599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1481622599
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2014967266
Short name T400
Test name
Test status
Simulation time 82668553 ps
CPU time 1.04 seconds
Started Jun 04 12:26:08 PM PDT 24
Finished Jun 04 12:26:11 PM PDT 24
Peak memory 195848 kb
Host smart-92ff3dd3-c001-4543-81e2-61390caf82b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014967266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2014967266
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1557789079
Short name T227
Test name
Test status
Simulation time 62532048 ps
CPU time 0.81 seconds
Started Jun 04 12:26:06 PM PDT 24
Finished Jun 04 12:26:08 PM PDT 24
Peak memory 195320 kb
Host smart-a0c450f4-cb8a-4332-8bf4-e6e92606fb74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557789079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1557789079
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.129348257
Short name T422
Test name
Test status
Simulation time 59544624 ps
CPU time 2.52 seconds
Started Jun 04 12:26:07 PM PDT 24
Finished Jun 04 12:26:12 PM PDT 24
Peak memory 197928 kb
Host smart-50975e3e-fc3c-4271-a77e-c75abdd916e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129348257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.129348257
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2510434544
Short name T641
Test name
Test status
Simulation time 42937444 ps
CPU time 1.21 seconds
Started Jun 04 12:26:08 PM PDT 24
Finished Jun 04 12:26:11 PM PDT 24
Peak memory 195372 kb
Host smart-d40ba5fe-20c6-4a4f-94c6-2c678c6b9c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510434544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2510434544
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2200170250
Short name T414
Test name
Test status
Simulation time 219581681 ps
CPU time 0.96 seconds
Started Jun 04 12:26:06 PM PDT 24
Finished Jun 04 12:26:08 PM PDT 24
Peak memory 196080 kb
Host smart-7445ffab-9ef7-4a9e-b376-0e9ea22af2b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200170250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2200170250
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.910086543
Short name T659
Test name
Test status
Simulation time 10572532479 ps
CPU time 144.07 seconds
Started Jun 04 12:26:05 PM PDT 24
Finished Jun 04 12:28:31 PM PDT 24
Peak memory 198000 kb
Host smart-bae64c01-b48d-41b9-8753-6d360f33cc1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910086543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.910086543
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.4209677036
Short name T58
Test name
Test status
Simulation time 96130814198 ps
CPU time 291.27 seconds
Started Jun 04 12:26:17 PM PDT 24
Finished Jun 04 12:31:10 PM PDT 24
Peak memory 198228 kb
Host smart-7cad0690-89d3-45c9-8fc2-81634c7e1764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4209677036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.4209677036
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2302917602
Short name T337
Test name
Test status
Simulation time 46106151 ps
CPU time 0.56 seconds
Started Jun 04 12:24:48 PM PDT 24
Finished Jun 04 12:24:50 PM PDT 24
Peak memory 193984 kb
Host smart-8f6ad273-2ac7-49de-8f15-6ca7933bd260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302917602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2302917602
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.531412810
Short name T314
Test name
Test status
Simulation time 41706012 ps
CPU time 0.9 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:24:44 PM PDT 24
Peak memory 196516 kb
Host smart-190d4c82-eeeb-452c-a8bc-85c3d315a4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531412810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.531412810
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1874638064
Short name T533
Test name
Test status
Simulation time 295781012 ps
CPU time 14.52 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:24:58 PM PDT 24
Peak memory 197828 kb
Host smart-708610b2-c139-41a4-987d-83584074489e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874638064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1874638064
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.225891811
Short name T191
Test name
Test status
Simulation time 433941450 ps
CPU time 0.87 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:24:44 PM PDT 24
Peak memory 195800 kb
Host smart-1bec138d-8aea-40d2-a254-cc89e98c0255
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225891811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.225891811
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2760786069
Short name T573
Test name
Test status
Simulation time 315833346 ps
CPU time 1.14 seconds
Started Jun 04 12:24:44 PM PDT 24
Finished Jun 04 12:24:47 PM PDT 24
Peak memory 196020 kb
Host smart-73fb7fa2-b023-4e13-be34-13e1f2eba042
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760786069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2760786069
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2098618382
Short name T142
Test name
Test status
Simulation time 32268677 ps
CPU time 1.29 seconds
Started Jun 04 12:24:52 PM PDT 24
Finished Jun 04 12:24:55 PM PDT 24
Peak memory 196736 kb
Host smart-bef847f9-9f01-4ab4-b753-2555ae5b3565
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098618382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2098618382
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.527506377
Short name T600
Test name
Test status
Simulation time 70717781 ps
CPU time 2.02 seconds
Started Jun 04 12:24:51 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 196916 kb
Host smart-d9badc88-cb85-43b7-83fd-ad8e3aed05a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527506377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.527506377
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1435301726
Short name T410
Test name
Test status
Simulation time 78489765 ps
CPU time 0.77 seconds
Started Jun 04 12:24:44 PM PDT 24
Finished Jun 04 12:24:46 PM PDT 24
Peak memory 197260 kb
Host smart-4736aad8-4acb-4838-a135-cee076bebb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435301726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1435301726
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1329952277
Short name T438
Test name
Test status
Simulation time 739011548 ps
CPU time 1.06 seconds
Started Jun 04 12:24:50 PM PDT 24
Finished Jun 04 12:24:53 PM PDT 24
Peak memory 195848 kb
Host smart-f5cf28a3-a024-4fc0-9dd4-b617ca1d8ce5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329952277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1329952277
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4171143884
Short name T490
Test name
Test status
Simulation time 215257825 ps
CPU time 2.49 seconds
Started Jun 04 12:24:53 PM PDT 24
Finished Jun 04 12:24:57 PM PDT 24
Peak memory 197824 kb
Host smart-db23e768-fb68-4142-b1df-4b5077c4fdb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171143884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4171143884
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1125335258
Short name T48
Test name
Test status
Simulation time 337527609 ps
CPU time 0.9 seconds
Started Jun 04 12:24:50 PM PDT 24
Finished Jun 04 12:24:53 PM PDT 24
Peak memory 214728 kb
Host smart-a2e2d6cd-09dd-49bf-b5e1-368d8874846c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125335258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1125335258
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.607674232
Short name T313
Test name
Test status
Simulation time 112209217 ps
CPU time 1.09 seconds
Started Jun 04 12:24:44 PM PDT 24
Finished Jun 04 12:24:47 PM PDT 24
Peak memory 195636 kb
Host smart-95ba0539-1d0d-47e1-bfc5-44f626365bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607674232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.607674232
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1695373812
Short name T123
Test name
Test status
Simulation time 66624941 ps
CPU time 1.07 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:24:44 PM PDT 24
Peak memory 196280 kb
Host smart-39118646-ee77-4c27-97a7-2bf921e7b529
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695373812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1695373812
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1076552600
Short name T406
Test name
Test status
Simulation time 28815852 ps
CPU time 0.54 seconds
Started Jun 04 12:26:18 PM PDT 24
Finished Jun 04 12:26:20 PM PDT 24
Peak memory 194524 kb
Host smart-7e631cb6-d5ca-41b9-a22f-377c72c331c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076552600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1076552600
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3248534733
Short name T336
Test name
Test status
Simulation time 243194952 ps
CPU time 0.77 seconds
Started Jun 04 12:26:17 PM PDT 24
Finished Jun 04 12:26:20 PM PDT 24
Peak memory 195208 kb
Host smart-0ea52b55-efb2-4c06-b796-ebfd0fb71aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248534733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3248534733
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1950495684
Short name T658
Test name
Test status
Simulation time 1605617785 ps
CPU time 13.58 seconds
Started Jun 04 12:26:22 PM PDT 24
Finished Jun 04 12:26:36 PM PDT 24
Peak memory 197784 kb
Host smart-2bafc22e-dd72-481a-9607-38703c3f10c5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950495684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1950495684
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3193714891
Short name T213
Test name
Test status
Simulation time 43097910 ps
CPU time 0.82 seconds
Started Jun 04 12:26:16 PM PDT 24
Finished Jun 04 12:26:19 PM PDT 24
Peak memory 195788 kb
Host smart-7c9e488b-9e2d-46dd-a1d2-64ea9f47a840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193714891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3193714891
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1457067285
Short name T565
Test name
Test status
Simulation time 283599994 ps
CPU time 1.1 seconds
Started Jun 04 12:26:14 PM PDT 24
Finished Jun 04 12:26:17 PM PDT 24
Peak memory 196388 kb
Host smart-5ec533d9-aaa5-41d1-a9b5-d9052bcac7be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457067285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1457067285
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1379959804
Short name T689
Test name
Test status
Simulation time 64322148 ps
CPU time 2.47 seconds
Started Jun 04 12:26:13 PM PDT 24
Finished Jun 04 12:26:17 PM PDT 24
Peak memory 196256 kb
Host smart-32bdd0c6-3f2c-4c67-b501-73674c2c7f94
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379959804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1379959804
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2553975321
Short name T345
Test name
Test status
Simulation time 108187201 ps
CPU time 3.02 seconds
Started Jun 04 12:26:19 PM PDT 24
Finished Jun 04 12:26:23 PM PDT 24
Peak memory 196844 kb
Host smart-bc229efd-c9a1-401c-a2d4-6bfd0a9edbab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553975321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2553975321
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3185691579
Short name T196
Test name
Test status
Simulation time 30269213 ps
CPU time 1.19 seconds
Started Jun 04 12:26:21 PM PDT 24
Finished Jun 04 12:26:23 PM PDT 24
Peak memory 195848 kb
Host smart-e1a72022-fe69-40b1-a876-dcd1dbd92fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185691579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3185691579
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.490318692
Short name T379
Test name
Test status
Simulation time 143359596 ps
CPU time 0.88 seconds
Started Jun 04 12:26:21 PM PDT 24
Finished Jun 04 12:26:23 PM PDT 24
Peak memory 196648 kb
Host smart-480fa6dc-21cb-4117-a746-424f90325f21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490318692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.490318692
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.483908693
Short name T170
Test name
Test status
Simulation time 309365061 ps
CPU time 1.37 seconds
Started Jun 04 12:26:15 PM PDT 24
Finished Jun 04 12:26:17 PM PDT 24
Peak memory 197828 kb
Host smart-4d484bc8-a575-41c4-b0e1-f52d23abfd18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483908693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.483908693
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2129211110
Short name T712
Test name
Test status
Simulation time 274752793 ps
CPU time 1.17 seconds
Started Jun 04 12:27:34 PM PDT 24
Finished Jun 04 12:27:37 PM PDT 24
Peak memory 196368 kb
Host smart-e6effe8a-218c-498a-948f-15da88d6f7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129211110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2129211110
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3200789205
Short name T646
Test name
Test status
Simulation time 83956118 ps
CPU time 1.19 seconds
Started Jun 04 12:26:17 PM PDT 24
Finished Jun 04 12:26:20 PM PDT 24
Peak memory 196624 kb
Host smart-a76a7eb9-9811-4148-abfe-540c026d0b34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200789205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3200789205
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2258205827
Short name T527
Test name
Test status
Simulation time 18679806089 ps
CPU time 101.91 seconds
Started Jun 04 12:26:13 PM PDT 24
Finished Jun 04 12:27:56 PM PDT 24
Peak memory 197892 kb
Host smart-f9e8a143-a72f-4703-be53-812a3fb80d18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258205827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2258205827
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3983205787
Short name T113
Test name
Test status
Simulation time 96158866 ps
CPU time 0.57 seconds
Started Jun 04 12:26:17 PM PDT 24
Finished Jun 04 12:26:19 PM PDT 24
Peak memory 193660 kb
Host smart-d14704bb-47d6-494d-b8e6-2ab840773b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983205787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3983205787
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2756632277
Short name T654
Test name
Test status
Simulation time 77130541 ps
CPU time 0.75 seconds
Started Jun 04 12:27:34 PM PDT 24
Finished Jun 04 12:27:36 PM PDT 24
Peak memory 195108 kb
Host smart-31dcc82e-6e57-4caa-8a8e-02a0fc2da4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756632277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2756632277
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.601790471
Short name T168
Test name
Test status
Simulation time 969565946 ps
CPU time 12.87 seconds
Started Jun 04 12:26:15 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 196560 kb
Host smart-2cbc856e-cbd4-4949-9aa0-f3c348031d2a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601790471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.601790471
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3203200517
Short name T441
Test name
Test status
Simulation time 202032136 ps
CPU time 0.93 seconds
Started Jun 04 12:26:14 PM PDT 24
Finished Jun 04 12:26:16 PM PDT 24
Peak memory 196404 kb
Host smart-c99e87e9-d545-477a-9573-ccc86901e522
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203200517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3203200517
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3639354145
Short name T373
Test name
Test status
Simulation time 19829515 ps
CPU time 0.65 seconds
Started Jun 04 12:26:14 PM PDT 24
Finished Jun 04 12:26:16 PM PDT 24
Peak memory 194152 kb
Host smart-927d5c8e-c0ac-4749-b2f7-292daf0d1316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639354145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3639354145
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2820220567
Short name T21
Test name
Test status
Simulation time 25297243 ps
CPU time 1.08 seconds
Started Jun 04 12:26:15 PM PDT 24
Finished Jun 04 12:26:18 PM PDT 24
Peak memory 197344 kb
Host smart-e5750340-651c-420f-980b-d4fa0d0e03c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820220567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2820220567
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2695563458
Short name T160
Test name
Test status
Simulation time 177780057 ps
CPU time 1.97 seconds
Started Jun 04 12:26:15 PM PDT 24
Finished Jun 04 12:26:19 PM PDT 24
Peak memory 196592 kb
Host smart-03d6aca3-1579-4c4e-8ad0-81695673b7fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695563458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2695563458
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2417386175
Short name T649
Test name
Test status
Simulation time 81113965 ps
CPU time 0.99 seconds
Started Jun 04 12:26:15 PM PDT 24
Finished Jun 04 12:26:17 PM PDT 24
Peak memory 195816 kb
Host smart-befe27ef-be6a-41c6-89f2-6ced3f0d3dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417386175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2417386175
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2573951215
Short name T116
Test name
Test status
Simulation time 1004016475 ps
CPU time 1.22 seconds
Started Jun 04 12:26:13 PM PDT 24
Finished Jun 04 12:26:16 PM PDT 24
Peak memory 197864 kb
Host smart-b368d59c-bc85-4671-8350-80e50a01c6d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573951215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2573951215
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2572057974
Short name T404
Test name
Test status
Simulation time 1099506936 ps
CPU time 2.7 seconds
Started Jun 04 12:26:14 PM PDT 24
Finished Jun 04 12:26:18 PM PDT 24
Peak memory 197772 kb
Host smart-8fc9b2e1-9927-4c7e-9ac9-40b0f3ce95f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572057974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2572057974
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.285942544
Short name T666
Test name
Test status
Simulation time 378538260 ps
CPU time 1.14 seconds
Started Jun 04 12:26:14 PM PDT 24
Finished Jun 04 12:26:16 PM PDT 24
Peak memory 195680 kb
Host smart-a2e7b2a2-3025-4502-97f8-b9dfa5636ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285942544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.285942544
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3911262407
Short name T559
Test name
Test status
Simulation time 64942066 ps
CPU time 0.98 seconds
Started Jun 04 12:26:16 PM PDT 24
Finished Jun 04 12:26:18 PM PDT 24
Peak memory 195384 kb
Host smart-8a920aaf-eab0-4ef3-9ff2-0706d7267452
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911262407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3911262407
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2813473842
Short name T217
Test name
Test status
Simulation time 44621510512 ps
CPU time 72.3 seconds
Started Jun 04 12:26:14 PM PDT 24
Finished Jun 04 12:27:28 PM PDT 24
Peak memory 198080 kb
Host smart-a93cc101-20ba-4918-88fe-2a7704a7dc0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813473842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2813473842
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3156965685
Short name T328
Test name
Test status
Simulation time 13613423 ps
CPU time 0.54 seconds
Started Jun 04 12:26:16 PM PDT 24
Finished Jun 04 12:26:18 PM PDT 24
Peak memory 193888 kb
Host smart-5d993b11-8ec2-4389-8808-7770306ae4cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156965685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3156965685
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3799333641
Short name T558
Test name
Test status
Simulation time 25328105 ps
CPU time 0.71 seconds
Started Jun 04 12:26:16 PM PDT 24
Finished Jun 04 12:26:18 PM PDT 24
Peak memory 195060 kb
Host smart-af0fa7bd-fb52-4f8a-88ad-ec19e187d580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799333641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3799333641
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.366816601
Short name T201
Test name
Test status
Simulation time 712486433 ps
CPU time 16.75 seconds
Started Jun 04 12:26:17 PM PDT 24
Finished Jun 04 12:26:35 PM PDT 24
Peak memory 196896 kb
Host smart-39a98afb-5a7e-451f-90b6-b7a33d001db3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366816601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.366816601
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.4074662597
Short name T435
Test name
Test status
Simulation time 597932423 ps
CPU time 0.9 seconds
Started Jun 04 12:26:13 PM PDT 24
Finished Jun 04 12:26:16 PM PDT 24
Peak memory 197112 kb
Host smart-a81579aa-d71a-429e-9507-6007780aa24d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074662597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.4074662597
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3325449567
Short name T624
Test name
Test status
Simulation time 49920956 ps
CPU time 1.29 seconds
Started Jun 04 12:26:22 PM PDT 24
Finished Jun 04 12:26:24 PM PDT 24
Peak memory 196560 kb
Host smart-ff517578-c45e-4008-b5f4-915442725273
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325449567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3325449567
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3893474796
Short name T580
Test name
Test status
Simulation time 79207902 ps
CPU time 1.71 seconds
Started Jun 04 12:26:15 PM PDT 24
Finished Jun 04 12:26:18 PM PDT 24
Peak memory 197900 kb
Host smart-7bbec221-5db1-4538-b9d0-f8d9e00e163b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893474796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3893474796
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.286135346
Short name T291
Test name
Test status
Simulation time 54858847 ps
CPU time 1.21 seconds
Started Jun 04 12:26:13 PM PDT 24
Finished Jun 04 12:26:15 PM PDT 24
Peak memory 196444 kb
Host smart-56c81744-ea51-49f0-8d50-abe81a59e3fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286135346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
286135346
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1480035268
Short name T713
Test name
Test status
Simulation time 27873681 ps
CPU time 0.99 seconds
Started Jun 04 12:27:34 PM PDT 24
Finished Jun 04 12:27:36 PM PDT 24
Peak memory 196580 kb
Host smart-7110246a-2041-4c80-9f9b-c8408e921b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480035268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1480035268
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2174387410
Short name T443
Test name
Test status
Simulation time 25434761 ps
CPU time 0.69 seconds
Started Jun 04 12:26:15 PM PDT 24
Finished Jun 04 12:26:17 PM PDT 24
Peak memory 195184 kb
Host smart-0ee0b6b1-2e68-40a3-934d-6928e8dbd6c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174387410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2174387410
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1482000417
Short name T673
Test name
Test status
Simulation time 219747012 ps
CPU time 2.58 seconds
Started Jun 04 12:26:16 PM PDT 24
Finished Jun 04 12:26:20 PM PDT 24
Peak memory 197840 kb
Host smart-2d30b891-91d5-431a-a148-cffc08742af5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482000417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1482000417
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1746032331
Short name T165
Test name
Test status
Simulation time 230588149 ps
CPU time 1.16 seconds
Started Jun 04 12:26:15 PM PDT 24
Finished Jun 04 12:26:18 PM PDT 24
Peak memory 196296 kb
Host smart-f88f7a1f-61ef-4772-90e4-3077bc623486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746032331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1746032331
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2379206065
Short name T586
Test name
Test status
Simulation time 96851643 ps
CPU time 0.84 seconds
Started Jun 04 12:26:22 PM PDT 24
Finished Jun 04 12:26:23 PM PDT 24
Peak memory 195232 kb
Host smart-24a8ef2d-b0e2-4e88-b937-5d7b856a68e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379206065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2379206065
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3175215182
Short name T415
Test name
Test status
Simulation time 43346660713 ps
CPU time 153.78 seconds
Started Jun 04 12:26:21 PM PDT 24
Finished Jun 04 12:28:56 PM PDT 24
Peak memory 198048 kb
Host smart-20ef1f72-8cbe-4d86-8d7d-49802894cc8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175215182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3175215182
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.4126972445
Short name T602
Test name
Test status
Simulation time 308271178890 ps
CPU time 1684.27 seconds
Started Jun 04 12:26:18 PM PDT 24
Finished Jun 04 12:54:24 PM PDT 24
Peak memory 198056 kb
Host smart-ef8c2da3-47fe-4897-9249-0b1371e7b66e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4126972445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.4126972445
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.362711080
Short name T215
Test name
Test status
Simulation time 12553043 ps
CPU time 0.62 seconds
Started Jun 04 12:26:28 PM PDT 24
Finished Jun 04 12:26:31 PM PDT 24
Peak memory 193756 kb
Host smart-77311c08-5955-4ce9-bb03-c53fad7da9c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362711080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.362711080
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1829622255
Short name T419
Test name
Test status
Simulation time 32115702 ps
CPU time 0.89 seconds
Started Jun 04 12:26:26 PM PDT 24
Finished Jun 04 12:26:28 PM PDT 24
Peak memory 195708 kb
Host smart-d5e4c248-15a8-4113-be56-b1c27a96a4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829622255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1829622255
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.111806643
Short name T539
Test name
Test status
Simulation time 3947267373 ps
CPU time 24.23 seconds
Started Jun 04 12:26:24 PM PDT 24
Finished Jun 04 12:26:49 PM PDT 24
Peak memory 196892 kb
Host smart-46b6a745-8608-4f88-9989-f31aa6f9e0df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111806643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.111806643
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3087955167
Short name T5
Test name
Test status
Simulation time 195398039 ps
CPU time 0.91 seconds
Started Jun 04 12:26:30 PM PDT 24
Finished Jun 04 12:26:33 PM PDT 24
Peak memory 195956 kb
Host smart-fcac2d1e-335a-4d46-b51c-7ec74e7d130d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087955167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3087955167
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.599802144
Short name T216
Test name
Test status
Simulation time 143436505 ps
CPU time 0.92 seconds
Started Jun 04 12:26:28 PM PDT 24
Finished Jun 04 12:26:31 PM PDT 24
Peak memory 195584 kb
Host smart-746cf905-6410-467d-9443-11250bd60b7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599802144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.599802144
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1323004876
Short name T411
Test name
Test status
Simulation time 83718738 ps
CPU time 3.05 seconds
Started Jun 04 12:26:23 PM PDT 24
Finished Jun 04 12:26:27 PM PDT 24
Peak memory 197552 kb
Host smart-c78a3690-e4a1-40be-9fec-e7b31db83a4e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323004876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1323004876
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1488610967
Short name T335
Test name
Test status
Simulation time 466724096 ps
CPU time 3.25 seconds
Started Jun 04 12:26:24 PM PDT 24
Finished Jun 04 12:26:28 PM PDT 24
Peak memory 197192 kb
Host smart-b63b33c9-7b56-4783-8932-9def4defc15c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488610967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1488610967
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3101705244
Short name T326
Test name
Test status
Simulation time 60384531 ps
CPU time 1.13 seconds
Started Jun 04 12:26:14 PM PDT 24
Finished Jun 04 12:26:16 PM PDT 24
Peak memory 195820 kb
Host smart-5b7a1aa0-f18b-445c-9f43-11591cfa2523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101705244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3101705244
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1555964827
Short name T596
Test name
Test status
Simulation time 212263965 ps
CPU time 1.23 seconds
Started Jun 04 12:26:27 PM PDT 24
Finished Jun 04 12:26:31 PM PDT 24
Peak memory 196916 kb
Host smart-fa4d34c1-f8a3-4e8e-b55f-7601604869e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555964827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1555964827
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1779596348
Short name T220
Test name
Test status
Simulation time 35798182 ps
CPU time 1.62 seconds
Started Jun 04 12:26:41 PM PDT 24
Finished Jun 04 12:26:44 PM PDT 24
Peak memory 197800 kb
Host smart-eb422eea-c653-436e-9faf-6fbdcd579ee1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779596348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1779596348
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1202614298
Short name T636
Test name
Test status
Simulation time 32615532 ps
CPU time 0.92 seconds
Started Jun 04 12:26:13 PM PDT 24
Finished Jun 04 12:26:16 PM PDT 24
Peak memory 196040 kb
Host smart-360bad11-256e-4fb1-b06d-0575a5df7b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202614298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1202614298
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.827381989
Short name T385
Test name
Test status
Simulation time 246119142 ps
CPU time 1.03 seconds
Started Jun 04 12:26:22 PM PDT 24
Finished Jun 04 12:26:23 PM PDT 24
Peak memory 195272 kb
Host smart-3884f337-2bd1-40b1-b360-2b8e9b1cd2e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827381989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.827381989
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2027867378
Short name T208
Test name
Test status
Simulation time 23420387041 ps
CPU time 56.46 seconds
Started Jun 04 12:26:23 PM PDT 24
Finished Jun 04 12:27:21 PM PDT 24
Peak memory 197948 kb
Host smart-9ddcc00f-24c7-47e3-beed-0732934adc63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027867378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2027867378
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2215457239
Short name T278
Test name
Test status
Simulation time 24883954 ps
CPU time 0.6 seconds
Started Jun 04 12:26:28 PM PDT 24
Finished Jun 04 12:26:31 PM PDT 24
Peak memory 193672 kb
Host smart-e08ec138-ec29-4388-9895-cb4fa99aac88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215457239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2215457239
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3794101447
Short name T614
Test name
Test status
Simulation time 40819016 ps
CPU time 0.87 seconds
Started Jun 04 12:26:24 PM PDT 24
Finished Jun 04 12:26:26 PM PDT 24
Peak memory 196340 kb
Host smart-1bd07a1d-24a0-4ca9-a7be-864bb7dc5826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794101447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3794101447
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1252517576
Short name T546
Test name
Test status
Simulation time 1574294899 ps
CPU time 10.41 seconds
Started Jun 04 12:26:23 PM PDT 24
Finished Jun 04 12:26:35 PM PDT 24
Peak memory 196736 kb
Host smart-20743b59-7a8f-4311-99f6-57c88b0a1baa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252517576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1252517576
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.300881599
Short name T50
Test name
Test status
Simulation time 119925460 ps
CPU time 0.9 seconds
Started Jun 04 12:26:24 PM PDT 24
Finished Jun 04 12:26:27 PM PDT 24
Peak memory 197800 kb
Host smart-0e760a17-0ea4-407b-9613-7faef9dc07f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300881599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.300881599
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2740427945
Short name T158
Test name
Test status
Simulation time 172922428 ps
CPU time 0.81 seconds
Started Jun 04 12:26:28 PM PDT 24
Finished Jun 04 12:26:31 PM PDT 24
Peak memory 195460 kb
Host smart-cd43743c-4bb4-455a-9619-6f072de10c44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740427945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2740427945
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2755676487
Short name T604
Test name
Test status
Simulation time 50050897 ps
CPU time 2.14 seconds
Started Jun 04 12:26:28 PM PDT 24
Finished Jun 04 12:26:32 PM PDT 24
Peak memory 197940 kb
Host smart-008ef244-16c0-4597-9d3f-0dac616c0385
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755676487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2755676487
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.49144500
Short name T589
Test name
Test status
Simulation time 174792202 ps
CPU time 3.06 seconds
Started Jun 04 12:26:27 PM PDT 24
Finished Jun 04 12:26:33 PM PDT 24
Peak memory 197896 kb
Host smart-dda961d9-2db1-4a48-b781-a1c0f423b27c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49144500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.49144500
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4229731711
Short name T498
Test name
Test status
Simulation time 86835843 ps
CPU time 1.03 seconds
Started Jun 04 12:26:28 PM PDT 24
Finished Jun 04 12:26:31 PM PDT 24
Peak memory 195796 kb
Host smart-20d0a8ef-15ff-4ce7-bb79-ae19df4faa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229731711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4229731711
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.770019503
Short name T409
Test name
Test status
Simulation time 27396952 ps
CPU time 0.95 seconds
Started Jun 04 12:26:24 PM PDT 24
Finished Jun 04 12:26:27 PM PDT 24
Peak memory 196484 kb
Host smart-0b8ff895-0912-4356-a67f-115fc754a435
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770019503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.770019503
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.706992391
Short name T508
Test name
Test status
Simulation time 1161324076 ps
CPU time 4.42 seconds
Started Jun 04 12:26:44 PM PDT 24
Finished Jun 04 12:26:50 PM PDT 24
Peak memory 197772 kb
Host smart-1922f3c2-35f0-482d-92a4-9a007d9791e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706992391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.706992391
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2258842465
Short name T644
Test name
Test status
Simulation time 58891644 ps
CPU time 0.96 seconds
Started Jun 04 12:26:24 PM PDT 24
Finished Jun 04 12:26:26 PM PDT 24
Peak memory 196464 kb
Host smart-f789ea99-ee83-429b-8b31-361505acc021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258842465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2258842465
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3189601761
Short name T192
Test name
Test status
Simulation time 54374990 ps
CPU time 1.09 seconds
Started Jun 04 12:26:28 PM PDT 24
Finished Jun 04 12:26:31 PM PDT 24
Peak memory 195596 kb
Host smart-89cc14cd-9c99-44b8-a3d9-5ba238d6f086
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189601761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3189601761
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3168925701
Short name T672
Test name
Test status
Simulation time 6318571574 ps
CPU time 84.04 seconds
Started Jun 04 12:26:24 PM PDT 24
Finished Jun 04 12:27:50 PM PDT 24
Peak memory 198052 kb
Host smart-1b4fc856-9e88-42c7-b853-824c3285270a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168925701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3168925701
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2593186564
Short name T90
Test name
Test status
Simulation time 87042665423 ps
CPU time 1881.63 seconds
Started Jun 04 12:26:25 PM PDT 24
Finished Jun 04 12:57:48 PM PDT 24
Peak memory 198084 kb
Host smart-339aad02-5e3c-4228-93b1-a33c53eba9b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2593186564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2593186564
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.117887689
Short name T481
Test name
Test status
Simulation time 51414746 ps
CPU time 0.62 seconds
Started Jun 04 12:26:34 PM PDT 24
Finished Jun 04 12:26:36 PM PDT 24
Peak memory 194648 kb
Host smart-ebd6555a-73ae-4c68-9b18-444fe0fe51f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117887689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.117887689
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2935735712
Short name T301
Test name
Test status
Simulation time 198981739 ps
CPU time 0.92 seconds
Started Jun 04 12:26:28 PM PDT 24
Finished Jun 04 12:26:31 PM PDT 24
Peak memory 195496 kb
Host smart-dc1802b6-523f-4a63-b735-2d2c96d35510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935735712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2935735712
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2694484429
Short name T195
Test name
Test status
Simulation time 381728582 ps
CPU time 13.04 seconds
Started Jun 04 12:26:25 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 196524 kb
Host smart-ea36e580-3bc5-4932-97c2-dff51a8a9044
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694484429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2694484429
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3475206890
Short name T124
Test name
Test status
Simulation time 203240453 ps
CPU time 0.96 seconds
Started Jun 04 12:26:27 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 197964 kb
Host smart-f2f4f733-7327-4629-9db7-c55b66aaeecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475206890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3475206890
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3005717976
Short name T637
Test name
Test status
Simulation time 349566614 ps
CPU time 1.43 seconds
Started Jun 04 12:26:28 PM PDT 24
Finished Jun 04 12:26:31 PM PDT 24
Peak memory 196064 kb
Host smart-c4d495cc-f5bd-4650-88be-f4437a82dc3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005717976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3005717976
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3995567733
Short name T167
Test name
Test status
Simulation time 112451737 ps
CPU time 2.05 seconds
Started Jun 04 12:27:34 PM PDT 24
Finished Jun 04 12:27:38 PM PDT 24
Peak memory 197900 kb
Host smart-6ff9e443-f889-4871-8755-b642f9a44fce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995567733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3995567733
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.471557605
Short name T143
Test name
Test status
Simulation time 182712011 ps
CPU time 2.15 seconds
Started Jun 04 12:26:28 PM PDT 24
Finished Jun 04 12:26:32 PM PDT 24
Peak memory 196848 kb
Host smart-c4aeb99e-6774-46b3-b74f-592951d0fd92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471557605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
471557605
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3570456110
Short name T110
Test name
Test status
Simulation time 247237510 ps
CPU time 0.99 seconds
Started Jun 04 12:26:26 PM PDT 24
Finished Jun 04 12:26:28 PM PDT 24
Peak memory 196336 kb
Host smart-6605c7fd-8703-43b7-8288-aacd28dd89c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570456110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3570456110
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2181120136
Short name T211
Test name
Test status
Simulation time 308735988 ps
CPU time 1.04 seconds
Started Jun 04 12:26:30 PM PDT 24
Finished Jun 04 12:26:33 PM PDT 24
Peak memory 195816 kb
Host smart-fd5c4f1e-56db-424f-91fd-310290e83941
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181120136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2181120136
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3149007241
Short name T6
Test name
Test status
Simulation time 654928284 ps
CPU time 3.67 seconds
Started Jun 04 12:26:26 PM PDT 24
Finished Jun 04 12:26:32 PM PDT 24
Peak memory 197748 kb
Host smart-883fdd33-f1b0-436c-9ea1-f22ae1fa370f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149007241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3149007241
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1563451037
Short name T329
Test name
Test status
Simulation time 73097544 ps
CPU time 1.09 seconds
Started Jun 04 12:26:24 PM PDT 24
Finished Jun 04 12:26:26 PM PDT 24
Peak memory 196860 kb
Host smart-638b0703-342a-44ef-a74a-6c5f7ca8c9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563451037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1563451037
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1189312549
Short name T631
Test name
Test status
Simulation time 594855357 ps
CPU time 1.21 seconds
Started Jun 04 12:26:23 PM PDT 24
Finished Jun 04 12:26:26 PM PDT 24
Peak memory 196728 kb
Host smart-8e57aaca-114f-4a50-b7f5-6183664a9380
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189312549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1189312549
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.4128281095
Short name T520
Test name
Test status
Simulation time 18766547492 ps
CPU time 43.03 seconds
Started Jun 04 12:26:26 PM PDT 24
Finished Jun 04 12:27:11 PM PDT 24
Peak memory 197936 kb
Host smart-36cfc3a0-e8af-466e-9500-012dc6191244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128281095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.4128281095
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.708081303
Short name T397
Test name
Test status
Simulation time 39657587675 ps
CPU time 180.52 seconds
Started Jun 04 12:26:35 PM PDT 24
Finished Jun 04 12:29:37 PM PDT 24
Peak memory 197996 kb
Host smart-4bef8299-d720-4ae3-aa07-e5bb9e4b4e8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=708081303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.708081303
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.69691440
Short name T459
Test name
Test status
Simulation time 39364661 ps
CPU time 0.56 seconds
Started Jun 04 12:26:38 PM PDT 24
Finished Jun 04 12:26:40 PM PDT 24
Peak memory 194408 kb
Host smart-2e815096-caf6-40ff-b95d-0b6d8e72f2eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69691440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.69691440
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2053476549
Short name T176
Test name
Test status
Simulation time 84187255 ps
CPU time 0.82 seconds
Started Jun 04 12:26:34 PM PDT 24
Finished Jun 04 12:26:36 PM PDT 24
Peak memory 195292 kb
Host smart-9d6de9f0-d9b3-42ca-b483-1a8d4e91bcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053476549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2053476549
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1769128499
Short name T193
Test name
Test status
Simulation time 2930349916 ps
CPU time 21.59 seconds
Started Jun 04 12:26:39 PM PDT 24
Finished Jun 04 12:27:02 PM PDT 24
Peak memory 197200 kb
Host smart-067a373e-6dda-49ff-b763-a805bad91045
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769128499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1769128499
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.366741428
Short name T96
Test name
Test status
Simulation time 44218870 ps
CPU time 0.84 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 195780 kb
Host smart-c5c8b855-3039-4da1-81ce-102f90d9477c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366741428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.366741428
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1169917748
Short name T295
Test name
Test status
Simulation time 55230182 ps
CPU time 1.34 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 197896 kb
Host smart-8ee0d841-7ecf-4cde-ace8-4bbb26433d4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169917748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1169917748
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3262331299
Short name T183
Test name
Test status
Simulation time 455028435 ps
CPU time 3.3 seconds
Started Jun 04 12:26:37 PM PDT 24
Finished Jun 04 12:26:41 PM PDT 24
Peak memory 197608 kb
Host smart-77a906e3-9d48-4974-a43e-c174aa564826
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262331299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3262331299
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3848236161
Short name T375
Test name
Test status
Simulation time 92781440 ps
CPU time 2.32 seconds
Started Jun 04 12:26:41 PM PDT 24
Finished Jun 04 12:26:45 PM PDT 24
Peak memory 197048 kb
Host smart-b19c81d4-e874-4cd8-be49-880c92f49a4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848236161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3848236161
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2829794317
Short name T129
Test name
Test status
Simulation time 27711465 ps
CPU time 1.08 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 195672 kb
Host smart-ece73078-09c8-4e34-8e9e-610655a75d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829794317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2829794317
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1186786191
Short name T294
Test name
Test status
Simulation time 78926042 ps
CPU time 0.98 seconds
Started Jun 04 12:26:38 PM PDT 24
Finished Jun 04 12:26:40 PM PDT 24
Peak memory 196560 kb
Host smart-fac53bcb-6160-4e1c-be60-4a6f46734723
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186786191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1186786191
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.289712620
Short name T595
Test name
Test status
Simulation time 795891261 ps
CPU time 2.69 seconds
Started Jun 04 12:26:40 PM PDT 24
Finished Jun 04 12:26:44 PM PDT 24
Peak memory 197024 kb
Host smart-12b74ca6-628d-4b53-aa60-bc7be24eb9dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289712620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.289712620
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1644596695
Short name T210
Test name
Test status
Simulation time 94674689 ps
CPU time 1.36 seconds
Started Jun 04 12:26:39 PM PDT 24
Finished Jun 04 12:26:42 PM PDT 24
Peak memory 195456 kb
Host smart-adbba99b-8b5b-432c-b881-19726dcbbf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644596695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1644596695
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.866135431
Short name T395
Test name
Test status
Simulation time 286023592 ps
CPU time 1.13 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 195576 kb
Host smart-6d7301f2-1413-4d90-973d-4ff2262a2f75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866135431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.866135431
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1664939029
Short name T674
Test name
Test status
Simulation time 14432896298 ps
CPU time 199.95 seconds
Started Jun 04 12:26:35 PM PDT 24
Finished Jun 04 12:29:57 PM PDT 24
Peak memory 198028 kb
Host smart-58148845-34b8-4594-ae4c-d39b1929156a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664939029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1664939029
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.227084430
Short name T549
Test name
Test status
Simulation time 12053141981 ps
CPU time 208.29 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:30:06 PM PDT 24
Peak memory 198132 kb
Host smart-df832550-cf28-4b4b-83a7-dfb22bbb20bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=227084430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.227084430
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3914411949
Short name T413
Test name
Test status
Simulation time 79166923 ps
CPU time 0.56 seconds
Started Jun 04 12:26:44 PM PDT 24
Finished Jun 04 12:26:46 PM PDT 24
Peak memory 194436 kb
Host smart-17eb2174-24fd-4db6-8abc-4787257f1fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914411949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3914411949
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2439981570
Short name T679
Test name
Test status
Simulation time 63223299 ps
CPU time 0.68 seconds
Started Jun 04 12:26:37 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 193908 kb
Host smart-9b02caf6-1ef2-4a35-bf63-a1995ebdbdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439981570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2439981570
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3438841134
Short name T353
Test name
Test status
Simulation time 844000434 ps
CPU time 12.46 seconds
Started Jun 04 12:26:41 PM PDT 24
Finished Jun 04 12:26:55 PM PDT 24
Peak memory 197404 kb
Host smart-6f2b7db3-9790-4ce3-a16b-96db8f123e3a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438841134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3438841134
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.20757583
Short name T55
Test name
Test status
Simulation time 237733117 ps
CPU time 0.86 seconds
Started Jun 04 12:26:38 PM PDT 24
Finished Jun 04 12:26:40 PM PDT 24
Peak memory 197596 kb
Host smart-6cc35c06-e584-43a7-8017-21eb7ce81d37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20757583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.20757583
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3251363818
Short name T368
Test name
Test status
Simulation time 34246541 ps
CPU time 1.03 seconds
Started Jun 04 12:26:41 PM PDT 24
Finished Jun 04 12:26:43 PM PDT 24
Peak memory 195276 kb
Host smart-9e59c684-2312-4435-9f43-a708c0740489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251363818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3251363818
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1107797518
Short name T91
Test name
Test status
Simulation time 47125429 ps
CPU time 1.44 seconds
Started Jun 04 12:26:42 PM PDT 24
Finished Jun 04 12:26:45 PM PDT 24
Peak memory 198004 kb
Host smart-81db6bae-5729-403f-9ba7-665c822572d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107797518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1107797518
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2314388333
Short name T456
Test name
Test status
Simulation time 157574455 ps
CPU time 2.2 seconds
Started Jun 04 12:26:38 PM PDT 24
Finished Jun 04 12:26:42 PM PDT 24
Peak memory 196616 kb
Host smart-94321276-fe2b-43c1-b390-bd371a769f8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314388333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2314388333
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3237048443
Short name T442
Test name
Test status
Simulation time 25540777 ps
CPU time 1.01 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 195764 kb
Host smart-7db1ca97-65dc-4d4f-bace-635ed274d396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237048443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3237048443
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1571068174
Short name T209
Test name
Test status
Simulation time 33572380 ps
CPU time 1.17 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 196828 kb
Host smart-a612dca3-e878-4958-84f7-42f5d284e497
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571068174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1571068174
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2053077359
Short name T711
Test name
Test status
Simulation time 1703718330 ps
CPU time 5.53 seconds
Started Jun 04 12:26:38 PM PDT 24
Finished Jun 04 12:26:45 PM PDT 24
Peak memory 197824 kb
Host smart-76692f80-29a9-4f82-abfa-2a5133995da0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053077359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2053077359
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1554868607
Short name T225
Test name
Test status
Simulation time 33503129 ps
CPU time 0.93 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 196096 kb
Host smart-d6df123f-e521-417c-8781-775766cad21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554868607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1554868607
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.4230124549
Short name T372
Test name
Test status
Simulation time 31199417 ps
CPU time 0.92 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 195520 kb
Host smart-2fd89561-7488-4a02-8f9f-dc8c35e22a6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230124549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.4230124549
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.619035507
Short name T386
Test name
Test status
Simulation time 10518108879 ps
CPU time 36.52 seconds
Started Jun 04 12:26:37 PM PDT 24
Finished Jun 04 12:27:16 PM PDT 24
Peak memory 198036 kb
Host smart-b581c918-c6af-4c92-a05b-a640503334e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619035507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.619035507
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1344018996
Short name T61
Test name
Test status
Simulation time 104178621579 ps
CPU time 928.2 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:42:06 PM PDT 24
Peak memory 198052 kb
Host smart-7e230990-88d0-47b8-a0c5-3f46adf907ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1344018996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1344018996
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1458042370
Short name T128
Test name
Test status
Simulation time 35700024 ps
CPU time 0.57 seconds
Started Jun 04 12:26:40 PM PDT 24
Finished Jun 04 12:26:42 PM PDT 24
Peak memory 193804 kb
Host smart-02dc63e8-7ded-4f45-a25f-c43813423a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458042370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1458042370
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3308407769
Short name T506
Test name
Test status
Simulation time 252064795 ps
CPU time 0.8 seconds
Started Jun 04 12:26:40 PM PDT 24
Finished Jun 04 12:26:42 PM PDT 24
Peak memory 195832 kb
Host smart-bcd30998-ee31-41c3-80e9-8f14354b7c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308407769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3308407769
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2689207208
Short name T655
Test name
Test status
Simulation time 748309330 ps
CPU time 25.51 seconds
Started Jun 04 12:26:40 PM PDT 24
Finished Jun 04 12:27:07 PM PDT 24
Peak memory 196964 kb
Host smart-1c86e7c1-614b-4592-bd08-6f3cb1e93bd0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689207208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2689207208
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.631640207
Short name T322
Test name
Test status
Simulation time 287752416 ps
CPU time 0.8 seconds
Started Jun 04 12:26:42 PM PDT 24
Finished Jun 04 12:26:44 PM PDT 24
Peak memory 195856 kb
Host smart-22c2c135-f502-4601-809d-fac9be5e4cc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631640207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.631640207
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3751539491
Short name T161
Test name
Test status
Simulation time 164458498 ps
CPU time 1.09 seconds
Started Jun 04 12:26:41 PM PDT 24
Finished Jun 04 12:26:44 PM PDT 24
Peak memory 196424 kb
Host smart-f7df0019-1ca0-43fd-adbc-0e4b08cfb9b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751539491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3751539491
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3987870106
Short name T407
Test name
Test status
Simulation time 270069102 ps
CPU time 2.45 seconds
Started Jun 04 12:26:37 PM PDT 24
Finished Jun 04 12:26:41 PM PDT 24
Peak memory 197944 kb
Host smart-36ee15cd-1bf5-4d6a-b65c-f0909f17473c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987870106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3987870106
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1628423879
Short name T347
Test name
Test status
Simulation time 360659222 ps
CPU time 3.13 seconds
Started Jun 04 12:26:40 PM PDT 24
Finished Jun 04 12:26:44 PM PDT 24
Peak memory 195644 kb
Host smart-d8ec8fb9-3d54-49bb-aa46-04a808156ae8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628423879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1628423879
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4243444868
Short name T468
Test name
Test status
Simulation time 77131497 ps
CPU time 0.84 seconds
Started Jun 04 12:26:45 PM PDT 24
Finished Jun 04 12:26:47 PM PDT 24
Peak memory 196316 kb
Host smart-65a68448-7239-4d19-8bfe-b5d17e377658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243444868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4243444868
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3817157352
Short name T681
Test name
Test status
Simulation time 17728066 ps
CPU time 0.63 seconds
Started Jun 04 12:26:39 PM PDT 24
Finished Jun 04 12:26:41 PM PDT 24
Peak memory 194824 kb
Host smart-89021257-7dc5-4d12-aefe-bb4774e82d1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817157352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3817157352
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1117263752
Short name T330
Test name
Test status
Simulation time 568949957 ps
CPU time 4.84 seconds
Started Jun 04 12:26:40 PM PDT 24
Finished Jun 04 12:26:46 PM PDT 24
Peak memory 197804 kb
Host smart-4767f8a4-971b-42aa-adcd-e32f5a51f212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117263752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1117263752
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3539365676
Short name T149
Test name
Test status
Simulation time 265968440 ps
CPU time 1.11 seconds
Started Jun 04 12:26:44 PM PDT 24
Finished Jun 04 12:26:47 PM PDT 24
Peak memory 195560 kb
Host smart-a38a3aef-cb49-435a-89f0-145fd377514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539365676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3539365676
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.4149291020
Short name T364
Test name
Test status
Simulation time 77968377 ps
CPU time 1.19 seconds
Started Jun 04 12:26:39 PM PDT 24
Finished Jun 04 12:26:41 PM PDT 24
Peak memory 196536 kb
Host smart-53ae45c6-e41c-4863-a327-2cdcdf62abc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149291020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.4149291020
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1509199433
Short name T325
Test name
Test status
Simulation time 13807453499 ps
CPU time 172.34 seconds
Started Jun 04 12:26:40 PM PDT 24
Finished Jun 04 12:29:34 PM PDT 24
Peak memory 198072 kb
Host smart-563ed4c0-a642-45f0-9cb6-db037dfceaa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509199433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1509199433
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2972724036
Short name T315
Test name
Test status
Simulation time 144546699 ps
CPU time 0.62 seconds
Started Jun 04 12:26:35 PM PDT 24
Finished Jun 04 12:26:38 PM PDT 24
Peak memory 194516 kb
Host smart-cc566503-4c6a-476b-ad29-39cc7ed96931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972724036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2972724036
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.976522612
Short name T576
Test name
Test status
Simulation time 25097070 ps
CPU time 0.78 seconds
Started Jun 04 12:26:42 PM PDT 24
Finished Jun 04 12:26:44 PM PDT 24
Peak memory 195120 kb
Host smart-f3f32d05-bf5a-4414-a984-35fd722fc699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976522612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.976522612
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.4223979866
Short name T603
Test name
Test status
Simulation time 1403469378 ps
CPU time 16.45 seconds
Started Jun 04 12:26:35 PM PDT 24
Finished Jun 04 12:26:53 PM PDT 24
Peak memory 197828 kb
Host smart-c474ab01-6e84-4371-af6f-ff61eeb78317
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223979866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.4223979866
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.372256817
Short name T145
Test name
Test status
Simulation time 80116445 ps
CPU time 1.02 seconds
Started Jun 04 12:26:34 PM PDT 24
Finished Jun 04 12:26:37 PM PDT 24
Peak memory 196348 kb
Host smart-96b5e99b-13d2-4785-aa14-4b0cabe6bc59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372256817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.372256817
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.721697758
Short name T512
Test name
Test status
Simulation time 68874238 ps
CPU time 0.92 seconds
Started Jun 04 12:26:44 PM PDT 24
Finished Jun 04 12:26:47 PM PDT 24
Peak memory 195804 kb
Host smart-29f6351a-9878-4c77-8068-a82f0000bbef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721697758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.721697758
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1261505150
Short name T523
Test name
Test status
Simulation time 195548538 ps
CPU time 3.62 seconds
Started Jun 04 12:26:35 PM PDT 24
Finished Jun 04 12:26:40 PM PDT 24
Peak memory 197864 kb
Host smart-9d938cbd-9724-482d-8613-a1eb5fd0d9eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261505150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1261505150
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3981952031
Short name T420
Test name
Test status
Simulation time 277566627 ps
CPU time 1.76 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 196444 kb
Host smart-d164ba7a-e179-4f2b-a54e-055f40ec301e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981952031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3981952031
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.403372305
Short name T130
Test name
Test status
Simulation time 66006386 ps
CPU time 1.23 seconds
Started Jun 04 12:26:44 PM PDT 24
Finished Jun 04 12:26:47 PM PDT 24
Peak memory 196880 kb
Host smart-4165a701-e60d-4d6c-a982-d1ce64385529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403372305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.403372305
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1829179117
Short name T321
Test name
Test status
Simulation time 97251163 ps
CPU time 1.03 seconds
Started Jun 04 12:26:43 PM PDT 24
Finished Jun 04 12:26:45 PM PDT 24
Peak memory 196468 kb
Host smart-3dbbb6f6-8f1b-4a08-8eda-ad6fb2efc9b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829179117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1829179117
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3646089091
Short name T423
Test name
Test status
Simulation time 127739371 ps
CPU time 5.6 seconds
Started Jun 04 12:26:34 PM PDT 24
Finished Jun 04 12:26:41 PM PDT 24
Peak memory 197840 kb
Host smart-41fd1096-119a-4ed4-a124-b22991cb8ce0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646089091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3646089091
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3751203551
Short name T175
Test name
Test status
Simulation time 190791942 ps
CPU time 0.99 seconds
Started Jun 04 12:26:44 PM PDT 24
Finished Jun 04 12:26:46 PM PDT 24
Peak memory 195548 kb
Host smart-cb95dd5c-2f2f-4c1b-8238-7cb6c8c5b454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751203551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3751203551
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.984010405
Short name T639
Test name
Test status
Simulation time 226605863 ps
CPU time 0.89 seconds
Started Jun 04 12:26:42 PM PDT 24
Finished Jun 04 12:26:44 PM PDT 24
Peak memory 197056 kb
Host smart-17f1742a-f7b4-411e-9fca-f00fa183c217
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984010405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.984010405
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3042435379
Short name T309
Test name
Test status
Simulation time 44650268581 ps
CPU time 147.46 seconds
Started Jun 04 12:26:36 PM PDT 24
Finished Jun 04 12:29:05 PM PDT 24
Peak memory 198028 kb
Host smart-44297d4b-15e1-4295-a0c0-f98c233cef93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042435379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3042435379
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.323963993
Short name T480
Test name
Test status
Simulation time 12947889 ps
CPU time 0.53 seconds
Started Jun 04 12:24:51 PM PDT 24
Finished Jun 04 12:24:53 PM PDT 24
Peak memory 193716 kb
Host smart-3d2089a2-eaf1-49b5-8210-3f2cbfbf15c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323963993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.323963993
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1964034121
Short name T668
Test name
Test status
Simulation time 38405363 ps
CPU time 0.75 seconds
Started Jun 04 12:24:47 PM PDT 24
Finished Jun 04 12:24:50 PM PDT 24
Peak memory 195740 kb
Host smart-41dfe866-b60d-435b-b098-2d2bf9f2404e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964034121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1964034121
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2635099048
Short name T355
Test name
Test status
Simulation time 465753351 ps
CPU time 6.29 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:26:00 PM PDT 24
Peak memory 194020 kb
Host smart-def9f476-f985-4552-b492-491da667f58f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635099048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2635099048
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3800501302
Short name T567
Test name
Test status
Simulation time 23497338 ps
CPU time 0.61 seconds
Started Jun 04 12:24:48 PM PDT 24
Finished Jun 04 12:24:50 PM PDT 24
Peak memory 194480 kb
Host smart-5a6945da-5f01-47f9-b83b-f9d276759fc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800501302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3800501302
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2835600679
Short name T107
Test name
Test status
Simulation time 45308320 ps
CPU time 1.16 seconds
Started Jun 04 12:24:52 PM PDT 24
Finished Jun 04 12:24:55 PM PDT 24
Peak memory 197036 kb
Host smart-4ed1ff81-04f3-4215-9470-013ffd98b2f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835600679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2835600679
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2978178599
Short name T292
Test name
Test status
Simulation time 475416389 ps
CPU time 2.49 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:25:56 PM PDT 24
Peak memory 196648 kb
Host smart-e4d50dd4-b1bf-4a55-99a7-6b138bf21b7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978178599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2978178599
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1271355785
Short name T324
Test name
Test status
Simulation time 290061326 ps
CPU time 2.28 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:24:45 PM PDT 24
Peak memory 197064 kb
Host smart-a4ee43ad-4cea-41be-bad0-bd05af331e66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271355785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1271355785
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.867420271
Short name T177
Test name
Test status
Simulation time 278501685 ps
CPU time 0.87 seconds
Started Jun 04 12:26:00 PM PDT 24
Finished Jun 04 12:26:03 PM PDT 24
Peak memory 195760 kb
Host smart-d93874d7-25b2-4ce9-8931-846fb22dd662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867420271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.867420271
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.195033801
Short name T627
Test name
Test status
Simulation time 76606328 ps
CPU time 1.18 seconds
Started Jun 04 12:24:47 PM PDT 24
Finished Jun 04 12:24:50 PM PDT 24
Peak memory 195680 kb
Host smart-e0d8de6b-8fab-4eb5-b252-1b7a7d6294f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195033801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.195033801
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3143125342
Short name T267
Test name
Test status
Simulation time 112173033 ps
CPU time 4.72 seconds
Started Jun 04 12:24:51 PM PDT 24
Finished Jun 04 12:24:57 PM PDT 24
Peak memory 197780 kb
Host smart-e7a41bec-9afd-4046-b5f7-752a2080bc09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143125342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3143125342
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.560219283
Short name T36
Test name
Test status
Simulation time 187958649 ps
CPU time 0.73 seconds
Started Jun 04 12:24:51 PM PDT 24
Finished Jun 04 12:24:53 PM PDT 24
Peak memory 213404 kb
Host smart-d17bc108-0b69-40f1-bc7a-077f8bd59a29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560219283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.560219283
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1184416655
Short name T283
Test name
Test status
Simulation time 223077543 ps
CPU time 1.11 seconds
Started Jun 04 12:24:52 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 196056 kb
Host smart-1efa8591-ddb6-4900-bdda-16e1dca49c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184416655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1184416655
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1977033253
Short name T529
Test name
Test status
Simulation time 77800959 ps
CPU time 1.2 seconds
Started Jun 04 12:24:53 PM PDT 24
Finished Jun 04 12:24:56 PM PDT 24
Peak memory 196796 kb
Host smart-68c74317-a974-45a9-8d96-b631a3f6d3e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977033253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1977033253
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.4273107364
Short name T690
Test name
Test status
Simulation time 26885216664 ps
CPU time 66.63 seconds
Started Jun 04 12:24:49 PM PDT 24
Finished Jun 04 12:25:57 PM PDT 24
Peak memory 198000 kb
Host smart-e5328d98-ff7e-46a7-93f0-6aced99bffac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273107364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.4273107364
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1786643290
Short name T599
Test name
Test status
Simulation time 58549261 ps
CPU time 0.57 seconds
Started Jun 04 12:26:48 PM PDT 24
Finished Jun 04 12:26:50 PM PDT 24
Peak memory 193720 kb
Host smart-231d0c00-f895-40a1-9b07-645e2cbcdf86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786643290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1786643290
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3260963404
Short name T354
Test name
Test status
Simulation time 44427445 ps
CPU time 0.62 seconds
Started Jun 04 12:26:49 PM PDT 24
Finished Jun 04 12:26:51 PM PDT 24
Peak memory 193828 kb
Host smart-f75f1c15-4221-45d5-9722-9292c4d78c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260963404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3260963404
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1284394647
Short name T686
Test name
Test status
Simulation time 860955643 ps
CPU time 23.06 seconds
Started Jun 04 12:26:45 PM PDT 24
Finished Jun 04 12:27:10 PM PDT 24
Peak memory 197828 kb
Host smart-a09ec56e-ffd7-441d-8650-0fdb020d122b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284394647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1284394647
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3980236243
Short name T519
Test name
Test status
Simulation time 137013695 ps
CPU time 0.76 seconds
Started Jun 04 12:26:48 PM PDT 24
Finished Jun 04 12:26:50 PM PDT 24
Peak memory 195408 kb
Host smart-c2d93973-cb52-478f-be1d-b8958b274de5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980236243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3980236243
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.4075224211
Short name T541
Test name
Test status
Simulation time 77044297 ps
CPU time 1.11 seconds
Started Jun 04 12:26:46 PM PDT 24
Finished Jun 04 12:26:48 PM PDT 24
Peak memory 196780 kb
Host smart-e590c0a9-7f01-4c16-ba40-548bca9d56c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075224211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.4075224211
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2239360741
Short name T440
Test name
Test status
Simulation time 26096438 ps
CPU time 1.19 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:26:55 PM PDT 24
Peak memory 197268 kb
Host smart-02aa9703-0e17-4ba3-9366-5636c8c3f783
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239360741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2239360741
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2179533014
Short name T197
Test name
Test status
Simulation time 550927842 ps
CPU time 2.76 seconds
Started Jun 04 12:26:48 PM PDT 24
Finished Jun 04 12:26:53 PM PDT 24
Peak memory 196944 kb
Host smart-01e06aaf-a854-4456-aa6a-62e7b2f54ef5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179533014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2179533014
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1897501502
Short name T178
Test name
Test status
Simulation time 188719193 ps
CPU time 1.14 seconds
Started Jun 04 12:26:48 PM PDT 24
Finished Jun 04 12:26:51 PM PDT 24
Peak memory 195916 kb
Host smart-af9ea1f4-8c32-44b5-b57c-bf2146b0397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897501502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1897501502
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1977935703
Short name T132
Test name
Test status
Simulation time 48886553 ps
CPU time 0.6 seconds
Started Jun 04 12:26:45 PM PDT 24
Finished Jun 04 12:26:47 PM PDT 24
Peak memory 194160 kb
Host smart-1b0cfa26-e053-46b9-9b48-a9e8bb0d58fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977935703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1977935703
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2494304970
Short name T8
Test name
Test status
Simulation time 1109138896 ps
CPU time 6.1 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:27:04 PM PDT 24
Peak memory 197800 kb
Host smart-fe66e3c8-492a-4bd3-b28a-e3bc26d48c6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494304970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2494304970
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1468748660
Short name T303
Test name
Test status
Simulation time 141759519 ps
CPU time 1.31 seconds
Started Jun 04 12:26:35 PM PDT 24
Finished Jun 04 12:26:37 PM PDT 24
Peak memory 196576 kb
Host smart-d2dffe75-91c2-492e-b0f6-3b7c96cda264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468748660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1468748660
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.297210383
Short name T346
Test name
Test status
Simulation time 347242517 ps
CPU time 1.14 seconds
Started Jun 04 12:26:44 PM PDT 24
Finished Jun 04 12:26:46 PM PDT 24
Peak memory 195616 kb
Host smart-cabe1c11-1ed4-426e-a111-36119e138ca9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297210383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.297210383
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.111174223
Short name T708
Test name
Test status
Simulation time 5281816204 ps
CPU time 102.09 seconds
Started Jun 04 12:26:50 PM PDT 24
Finished Jun 04 12:28:34 PM PDT 24
Peak memory 198308 kb
Host smart-26c5a773-447c-47da-b090-5727ba803bc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111174223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.111174223
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1504383654
Short name T64
Test name
Test status
Simulation time 52019948830 ps
CPU time 306.31 seconds
Started Jun 04 12:26:47 PM PDT 24
Finished Jun 04 12:31:54 PM PDT 24
Peak memory 198188 kb
Host smart-8039a3f2-ff4c-4ab0-a61e-deb8e7c0bf5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1504383654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1504383654
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1342935221
Short name T548
Test name
Test status
Simulation time 26849702 ps
CPU time 0.56 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:26:54 PM PDT 24
Peak memory 193748 kb
Host smart-e506d236-4f23-4d3c-a494-0684e294dbd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342935221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1342935221
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3406847324
Short name T473
Test name
Test status
Simulation time 26962929 ps
CPU time 0.87 seconds
Started Jun 04 12:26:53 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 196248 kb
Host smart-1b6fbed1-187e-4371-8510-f026144ef203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406847324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3406847324
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3753367590
Short name T585
Test name
Test status
Simulation time 377787676 ps
CPU time 3.64 seconds
Started Jun 04 12:26:43 PM PDT 24
Finished Jun 04 12:26:48 PM PDT 24
Peak memory 196532 kb
Host smart-c87375ca-7d0a-4fa8-bc53-a7b76c9011ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753367590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3753367590
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1771634110
Short name T332
Test name
Test status
Simulation time 86160760 ps
CPU time 1.06 seconds
Started Jun 04 12:26:47 PM PDT 24
Finished Jun 04 12:26:49 PM PDT 24
Peak memory 196604 kb
Host smart-cb022a07-3559-454a-9bbf-77793c034316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771634110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1771634110
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1149284947
Short name T266
Test name
Test status
Simulation time 200417730 ps
CPU time 1.02 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 195992 kb
Host smart-5564d601-80e1-4511-86a8-28fcf8f18b9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149284947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1149284947
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1314047040
Short name T551
Test name
Test status
Simulation time 53515995 ps
CPU time 2.14 seconds
Started Jun 04 12:26:48 PM PDT 24
Finished Jun 04 12:26:52 PM PDT 24
Peak memory 197824 kb
Host smart-fc198752-cbdd-498a-9a9b-861830d33040
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314047040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1314047040
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3241010467
Short name T247
Test name
Test status
Simulation time 28162516 ps
CPU time 0.79 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 194904 kb
Host smart-9cc74da1-ab4d-443f-a682-0f98ac0f621b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241010467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3241010467
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.726835095
Short name T25
Test name
Test status
Simulation time 156987699 ps
CPU time 1.05 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 195952 kb
Host smart-365ef554-1f6b-4d83-84ac-c811a6061836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726835095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.726835095
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1150234728
Short name T169
Test name
Test status
Simulation time 22276431 ps
CPU time 0.85 seconds
Started Jun 04 12:26:48 PM PDT 24
Finished Jun 04 12:26:50 PM PDT 24
Peak memory 196404 kb
Host smart-81c3aaea-cd4c-4a12-9c43-8f60fc6ad3b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150234728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1150234728
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1936529570
Short name T56
Test name
Test status
Simulation time 26725890 ps
CPU time 1.17 seconds
Started Jun 04 12:26:46 PM PDT 24
Finished Jun 04 12:26:49 PM PDT 24
Peak memory 197824 kb
Host smart-c02794b0-b22e-4b54-8951-7328678bc130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936529570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1936529570
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.897354493
Short name T497
Test name
Test status
Simulation time 95131698 ps
CPU time 0.9 seconds
Started Jun 04 12:26:55 PM PDT 24
Finished Jun 04 12:27:00 PM PDT 24
Peak memory 195484 kb
Host smart-169c182a-cbfb-442d-a40e-c56025d4b049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897354493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.897354493
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.403999344
Short name T282
Test name
Test status
Simulation time 32682129 ps
CPU time 0.96 seconds
Started Jun 04 12:26:47 PM PDT 24
Finished Jun 04 12:26:49 PM PDT 24
Peak memory 195444 kb
Host smart-22f64cc9-c207-427a-8403-49562a043bd0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403999344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.403999344
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.276014453
Short name T10
Test name
Test status
Simulation time 8248881692 ps
CPU time 88.09 seconds
Started Jun 04 12:26:48 PM PDT 24
Finished Jun 04 12:28:18 PM PDT 24
Peak memory 198060 kb
Host smart-6e54e8c9-4be8-47a5-ab97-cc25d442857e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276014453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.276014453
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1481453384
Short name T401
Test name
Test status
Simulation time 16158095 ps
CPU time 0.56 seconds
Started Jun 04 12:26:43 PM PDT 24
Finished Jun 04 12:26:44 PM PDT 24
Peak memory 193748 kb
Host smart-e2dfb3c7-8a8a-4656-9e65-46a17fa87d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481453384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1481453384
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2473183470
Short name T299
Test name
Test status
Simulation time 24933178 ps
CPU time 0.84 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:26:55 PM PDT 24
Peak memory 195748 kb
Host smart-1998a470-83a8-4958-a48c-6b7ede539b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473183470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2473183470
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4109524807
Short name T135
Test name
Test status
Simulation time 1026377537 ps
CPU time 8.57 seconds
Started Jun 04 12:26:48 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 196596 kb
Host smart-3f65f414-65b2-4d77-90da-d96963fd03b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109524807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4109524807
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2053327223
Short name T125
Test name
Test status
Simulation time 150272917 ps
CPU time 0.83 seconds
Started Jun 04 12:26:55 PM PDT 24
Finished Jun 04 12:27:00 PM PDT 24
Peak memory 195952 kb
Host smart-ba5a64d2-eef7-4486-ac59-9b21f1eaea9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053327223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2053327223
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2467649753
Short name T358
Test name
Test status
Simulation time 42303255 ps
CPU time 0.83 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:57 PM PDT 24
Peak memory 195424 kb
Host smart-20321506-6d28-490e-8f71-04aacbc8970b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467649753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2467649753
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.284151194
Short name T154
Test name
Test status
Simulation time 53117339 ps
CPU time 2.03 seconds
Started Jun 04 12:26:45 PM PDT 24
Finished Jun 04 12:26:48 PM PDT 24
Peak memory 197844 kb
Host smart-370c956a-624d-4cdf-93bc-c350d64991b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284151194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.284151194
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.928444443
Short name T525
Test name
Test status
Simulation time 569323855 ps
CPU time 2.69 seconds
Started Jun 04 12:26:47 PM PDT 24
Finished Jun 04 12:26:51 PM PDT 24
Peak memory 195636 kb
Host smart-d577b266-d6dd-4e50-9f0f-308c318d5a94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928444443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
928444443
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1892446676
Short name T327
Test name
Test status
Simulation time 151135920 ps
CPU time 0.95 seconds
Started Jun 04 12:26:44 PM PDT 24
Finished Jun 04 12:26:47 PM PDT 24
Peak memory 195836 kb
Host smart-71e64e64-e887-47f4-b1a7-c0a70e288d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892446676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1892446676
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3045833818
Short name T682
Test name
Test status
Simulation time 57595297 ps
CPU time 1.01 seconds
Started Jun 04 12:26:44 PM PDT 24
Finished Jun 04 12:26:47 PM PDT 24
Peak memory 195916 kb
Host smart-581308e9-90a5-4afb-943a-7a8a8f894a78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045833818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3045833818
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.465764768
Short name T356
Test name
Test status
Simulation time 747761465 ps
CPU time 6.24 seconds
Started Jun 04 12:26:55 PM PDT 24
Finished Jun 04 12:27:06 PM PDT 24
Peak memory 197756 kb
Host smart-99970b6d-c9b0-4c0b-a721-310c29f4fa49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465764768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.465764768
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.445566860
Short name T564
Test name
Test status
Simulation time 155804784 ps
CPU time 1.37 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:57 PM PDT 24
Peak memory 197772 kb
Host smart-9943c965-4636-4b9e-bce6-990ee1911c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445566860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.445566860
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2742943318
Short name T579
Test name
Test status
Simulation time 250415086 ps
CPU time 1.12 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:26:55 PM PDT 24
Peak memory 195568 kb
Host smart-260a4d70-8a49-4be2-a3ab-c1396aa6a57d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742943318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2742943318
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3268590479
Short name T466
Test name
Test status
Simulation time 15199347099 ps
CPU time 176.59 seconds
Started Jun 04 12:26:49 PM PDT 24
Finished Jun 04 12:29:47 PM PDT 24
Peak memory 198020 kb
Host smart-9d6e2190-f21a-4c15-ae66-68bbfa92c25f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268590479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3268590479
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2536873719
Short name T458
Test name
Test status
Simulation time 48645306 ps
CPU time 0.57 seconds
Started Jun 04 12:27:00 PM PDT 24
Finished Jun 04 12:27:02 PM PDT 24
Peak memory 193916 kb
Host smart-308aea74-3872-4e66-b4b9-d96b87bd06db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536873719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2536873719
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3741007884
Short name T592
Test name
Test status
Simulation time 49894502 ps
CPU time 0.6 seconds
Started Jun 04 12:26:48 PM PDT 24
Finished Jun 04 12:26:50 PM PDT 24
Peak memory 193828 kb
Host smart-6efd794b-b0c9-4e2e-a2e6-84d7b7c8d0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741007884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3741007884
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.588859258
Short name T687
Test name
Test status
Simulation time 1417415106 ps
CPU time 16.9 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:27:11 PM PDT 24
Peak memory 196732 kb
Host smart-e049a81b-af10-421d-94ce-d404d78056a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588859258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.588859258
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1096559746
Short name T111
Test name
Test status
Simulation time 181804803 ps
CPU time 0.68 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 195152 kb
Host smart-6a5d2971-3835-4591-a025-ad0f1d6ca262
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096559746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1096559746
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.46846125
Short name T171
Test name
Test status
Simulation time 408726308 ps
CPU time 0.63 seconds
Started Jun 04 12:26:45 PM PDT 24
Finished Jun 04 12:26:48 PM PDT 24
Peak memory 194184 kb
Host smart-52efab2a-1962-47ce-8aa4-a678ff6a68a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46846125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.46846125
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.4126980088
Short name T647
Test name
Test status
Simulation time 78387944 ps
CPU time 1.71 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:58 PM PDT 24
Peak memory 197924 kb
Host smart-452ecfa1-2ea4-4843-8f38-bc9cd01cfd43
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126980088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.4126980088
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3545617241
Short name T54
Test name
Test status
Simulation time 52861781 ps
CPU time 1.21 seconds
Started Jun 04 12:26:55 PM PDT 24
Finished Jun 04 12:27:01 PM PDT 24
Peak memory 195528 kb
Host smart-08b97aa4-0b57-4d46-ab0e-58a4d224bb66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545617241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3545617241
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1562663935
Short name T204
Test name
Test status
Simulation time 32035497 ps
CPU time 1.15 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:57 PM PDT 24
Peak memory 196480 kb
Host smart-0ffc6a03-61c0-4ef4-9051-bb8eeb9abb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562663935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1562663935
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.172057365
Short name T194
Test name
Test status
Simulation time 188093050 ps
CPU time 0.69 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:57 PM PDT 24
Peak memory 195908 kb
Host smart-7493376b-1e46-4e70-b5d3-31d67b26332c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172057365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.172057365
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2203700269
Short name T173
Test name
Test status
Simulation time 305717535 ps
CPU time 3.67 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:26:58 PM PDT 24
Peak memory 197692 kb
Host smart-c5796460-752b-49bf-93a4-0eee3d6a0d24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203700269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2203700269
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.4163469684
Short name T635
Test name
Test status
Simulation time 127461512 ps
CPU time 1.02 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:57 PM PDT 24
Peak memory 195332 kb
Host smart-d0c259aa-fd40-4a1f-8950-4b4b909238bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163469684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.4163469684
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.228201723
Short name T351
Test name
Test status
Simulation time 53601968 ps
CPU time 1.01 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 196072 kb
Host smart-dfd83b70-59ce-4a26-805d-14c825a4da0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228201723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.228201723
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1430777696
Short name T588
Test name
Test status
Simulation time 20714525693 ps
CPU time 116.18 seconds
Started Jun 04 12:26:53 PM PDT 24
Finished Jun 04 12:28:54 PM PDT 24
Peak memory 197964 kb
Host smart-4a47c4b2-c212-4795-8dde-4d511df32f69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430777696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1430777696
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.645359923
Short name T544
Test name
Test status
Simulation time 252280694019 ps
CPU time 960.89 seconds
Started Jun 04 12:26:55 PM PDT 24
Finished Jun 04 12:43:00 PM PDT 24
Peak memory 198124 kb
Host smart-d2be5853-9e5d-422c-92e3-36031271af60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=645359923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.645359923
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1795529567
Short name T482
Test name
Test status
Simulation time 21485152 ps
CPU time 0.61 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:56 PM PDT 24
Peak memory 193636 kb
Host smart-5f2f7a1a-d17c-497c-8062-40ef0b9b5e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795529567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1795529567
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1857367401
Short name T661
Test name
Test status
Simulation time 16408156 ps
CPU time 0.61 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 193816 kb
Host smart-76024b06-1309-4298-b001-f62bb1ba23ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857367401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1857367401
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3146179313
Short name T408
Test name
Test status
Simulation time 610255062 ps
CPU time 17.79 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:27:12 PM PDT 24
Peak memory 197792 kb
Host smart-a40f0bff-c876-4677-a1f9-2e4266b38254
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146179313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3146179313
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.4005580167
Short name T52
Test name
Test status
Simulation time 20820170 ps
CPU time 0.67 seconds
Started Jun 04 12:26:53 PM PDT 24
Finished Jun 04 12:26:58 PM PDT 24
Peak memory 194396 kb
Host smart-89d0f4d1-a335-49bd-9b5d-0750e2bfbcab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005580167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4005580167
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2037299364
Short name T621
Test name
Test status
Simulation time 27784657 ps
CPU time 0.69 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:26:54 PM PDT 24
Peak memory 194256 kb
Host smart-5f8d4d56-a586-464a-9af5-4c3033c05fff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037299364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2037299364
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1950882680
Short name T383
Test name
Test status
Simulation time 57890876 ps
CPU time 2.4 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:26:57 PM PDT 24
Peak memory 197864 kb
Host smart-c623e191-53f5-4aa6-8379-4319f57e8056
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950882680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1950882680
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2768969711
Short name T106
Test name
Test status
Simulation time 530690109 ps
CPU time 2.5 seconds
Started Jun 04 12:26:55 PM PDT 24
Finished Jun 04 12:27:01 PM PDT 24
Peak memory 195632 kb
Host smart-0feaede0-3d54-4c48-a3c2-38adcf15ffda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768969711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2768969711
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2040771113
Short name T521
Test name
Test status
Simulation time 59537388 ps
CPU time 0.86 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:57 PM PDT 24
Peak memory 196572 kb
Host smart-aa8ef907-9e12-4a36-a830-0b4cc28af40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040771113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2040771113
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4071375105
Short name T537
Test name
Test status
Simulation time 27357798 ps
CPU time 0.75 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:56 PM PDT 24
Peak memory 196024 kb
Host smart-f24e64bd-e33b-4900-b9ad-c51e4117ab5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071375105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.4071375105
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1934306120
Short name T109
Test name
Test status
Simulation time 1253641431 ps
CPU time 3.01 seconds
Started Jun 04 12:26:53 PM PDT 24
Finished Jun 04 12:27:00 PM PDT 24
Peak memory 197976 kb
Host smart-1a6ad7dc-9807-499e-a15c-0e3f89eff3be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934306120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1934306120
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.808490157
Short name T232
Test name
Test status
Simulation time 164759433 ps
CPU time 1.42 seconds
Started Jun 04 12:26:55 PM PDT 24
Finished Jun 04 12:27:00 PM PDT 24
Peak memory 197820 kb
Host smart-062d0dda-fc94-4d79-982d-a0e897aceccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808490157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.808490157
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3603085636
Short name T382
Test name
Test status
Simulation time 28817334 ps
CPU time 0.93 seconds
Started Jun 04 12:26:53 PM PDT 24
Finished Jun 04 12:26:58 PM PDT 24
Peak memory 196960 kb
Host smart-7f5e2fda-5a38-4a48-8272-e29b961f19ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603085636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3603085636
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.77042299
Short name T339
Test name
Test status
Simulation time 21035506757 ps
CPU time 223.84 seconds
Started Jun 04 12:27:02 PM PDT 24
Finished Jun 04 12:30:47 PM PDT 24
Peak memory 197912 kb
Host smart-8b362da8-58bc-4106-9e99-cfe3e38f445b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77042299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gp
io_stress_all.77042299
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3271545810
Short name T396
Test name
Test status
Simulation time 97971155590 ps
CPU time 1103.09 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:45:19 PM PDT 24
Peak memory 198136 kb
Host smart-143100f2-9a40-4518-87b8-f141189d0317
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3271545810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3271545810
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2700123098
Short name T121
Test name
Test status
Simulation time 30541560 ps
CPU time 0.61 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:56 PM PDT 24
Peak memory 194064 kb
Host smart-cb077ee1-a486-41cc-8b56-d18263727d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700123098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2700123098
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.468696774
Short name T317
Test name
Test status
Simulation time 23548883 ps
CPU time 0.74 seconds
Started Jun 04 12:27:00 PM PDT 24
Finished Jun 04 12:27:02 PM PDT 24
Peak memory 194772 kb
Host smart-c1824d8a-237d-4ece-bc69-5632d7debc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468696774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.468696774
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1884512903
Short name T615
Test name
Test status
Simulation time 907612533 ps
CPU time 15.03 seconds
Started Jun 04 12:27:03 PM PDT 24
Finished Jun 04 12:27:20 PM PDT 24
Peak memory 197776 kb
Host smart-c09c1c08-f8fd-4cad-8cbe-27356c9f8d4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884512903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1884512903
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.291515429
Short name T703
Test name
Test status
Simulation time 124431503 ps
CPU time 0.91 seconds
Started Jun 04 12:27:00 PM PDT 24
Finished Jun 04 12:27:03 PM PDT 24
Peak memory 197136 kb
Host smart-e42a33b7-c29c-4190-b432-39a711ed021c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291515429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.291515429
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.139315067
Short name T437
Test name
Test status
Simulation time 81407828 ps
CPU time 1.15 seconds
Started Jun 04 12:27:01 PM PDT 24
Finished Jun 04 12:27:04 PM PDT 24
Peak memory 195576 kb
Host smart-ed1651ce-b315-491b-ac14-5d56b5e02e1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139315067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.139315067
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2327314044
Short name T365
Test name
Test status
Simulation time 31414135 ps
CPU time 1.23 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 196600 kb
Host smart-1894e843-e55e-4a40-9f15-9381e6e0fcf2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327314044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2327314044
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1683450524
Short name T421
Test name
Test status
Simulation time 447289064 ps
CPU time 2.38 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:27:00 PM PDT 24
Peak memory 197868 kb
Host smart-b0184350-2486-41db-b17a-56fcac528643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683450524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1683450524
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.695440050
Short name T612
Test name
Test status
Simulation time 30020455 ps
CPU time 0.92 seconds
Started Jun 04 12:26:55 PM PDT 24
Finished Jun 04 12:27:00 PM PDT 24
Peak memory 196300 kb
Host smart-1fe2c209-58d9-4a21-8aa1-fe0f12dff7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695440050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.695440050
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2994333647
Short name T554
Test name
Test status
Simulation time 227011818 ps
CPU time 1.2 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:26:57 PM PDT 24
Peak memory 197896 kb
Host smart-67ea035d-29f7-47cc-b08b-01db8113af7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994333647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2994333647
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.891252681
Short name T465
Test name
Test status
Simulation time 453237329 ps
CPU time 5.05 seconds
Started Jun 04 12:27:02 PM PDT 24
Finished Jun 04 12:27:09 PM PDT 24
Peak memory 197812 kb
Host smart-562f9dc6-5466-47f1-901c-4aa4f2adc931
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891252681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.891252681
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.4128064169
Short name T507
Test name
Test status
Simulation time 542412062 ps
CPU time 0.93 seconds
Started Jun 04 12:26:55 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 196384 kb
Host smart-9c3aa854-9dd4-4ca1-abfb-577929d9759e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128064169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.4128064169
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2347747105
Short name T122
Test name
Test status
Simulation time 152652091 ps
CPU time 0.98 seconds
Started Jun 04 12:27:02 PM PDT 24
Finished Jun 04 12:27:05 PM PDT 24
Peak memory 195304 kb
Host smart-205b1736-19d7-45f3-8158-fed95b4433dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347747105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2347747105
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3178115576
Short name T19
Test name
Test status
Simulation time 6335355248 ps
CPU time 64.11 seconds
Started Jun 04 12:26:52 PM PDT 24
Finished Jun 04 12:27:59 PM PDT 24
Peak memory 198028 kb
Host smart-c4a078ec-8d85-4473-a163-b2d6b41a9bc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178115576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3178115576
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.4066589113
Short name T632
Test name
Test status
Simulation time 100536548214 ps
CPU time 1463.79 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:51:18 PM PDT 24
Peak memory 198044 kb
Host smart-afccd23b-b9fc-442c-97a8-9afbb1c6c607
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4066589113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.4066589113
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2973367929
Short name T606
Test name
Test status
Simulation time 11852016 ps
CPU time 0.61 seconds
Started Jun 04 12:26:57 PM PDT 24
Finished Jun 04 12:27:01 PM PDT 24
Peak memory 192620 kb
Host smart-283ce908-cf0e-44fb-9c2f-c56d19b8fb74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973367929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2973367929
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2260124145
Short name T467
Test name
Test status
Simulation time 77583995 ps
CPU time 0.93 seconds
Started Jun 04 12:26:56 PM PDT 24
Finished Jun 04 12:27:00 PM PDT 24
Peak memory 197136 kb
Host smart-7c087eca-26ff-4b36-98bb-a7564e3b3eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260124145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2260124145
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2155468762
Short name T393
Test name
Test status
Simulation time 989029277 ps
CPU time 7.68 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:27:06 PM PDT 24
Peak memory 197824 kb
Host smart-b325ac00-9394-4416-aa17-ecae6093b881
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155468762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2155468762
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.99106094
Short name T286
Test name
Test status
Simulation time 335986954 ps
CPU time 1.06 seconds
Started Jun 04 12:26:57 PM PDT 24
Finished Jun 04 12:27:01 PM PDT 24
Peak memory 197900 kb
Host smart-70dcb82b-156c-42a1-88e6-c3f7a10fd5ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99106094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.99106094
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2810946951
Short name T478
Test name
Test status
Simulation time 132891882 ps
CPU time 1.01 seconds
Started Jun 04 12:26:53 PM PDT 24
Finished Jun 04 12:26:58 PM PDT 24
Peak memory 196068 kb
Host smart-57843def-bfce-4d6c-984d-1f534ed03687
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810946951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2810946951
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1481515506
Short name T157
Test name
Test status
Simulation time 65369691 ps
CPU time 2.07 seconds
Started Jun 04 12:26:54 PM PDT 24
Finished Jun 04 12:27:00 PM PDT 24
Peak memory 197856 kb
Host smart-617d3048-f600-4778-9934-8b4d22c2c5a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481515506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1481515506
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3733262308
Short name T416
Test name
Test status
Simulation time 48490420 ps
CPU time 1.06 seconds
Started Jun 04 12:26:55 PM PDT 24
Finished Jun 04 12:27:00 PM PDT 24
Peak memory 195896 kb
Host smart-9aa6410f-307d-4d4b-ac65-34bd78b84cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733262308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3733262308
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2876622039
Short name T610
Test name
Test status
Simulation time 141218949 ps
CPU time 1.16 seconds
Started Jun 04 12:26:56 PM PDT 24
Finished Jun 04 12:27:01 PM PDT 24
Peak memory 196848 kb
Host smart-18d90262-75a8-41a8-882c-7c3203bf7c31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876622039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2876622039
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2798345453
Short name T697
Test name
Test status
Simulation time 382592266 ps
CPU time 5.51 seconds
Started Jun 04 12:26:51 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 197844 kb
Host smart-0a30f681-7d07-4bee-be19-22d662cdd6e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798345453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2798345453
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.384365242
Short name T67
Test name
Test status
Simulation time 80200718 ps
CPU time 1.28 seconds
Started Jun 04 12:27:00 PM PDT 24
Finished Jun 04 12:27:03 PM PDT 24
Peak memory 196260 kb
Host smart-769c813f-b2d0-492c-93a1-c379d2184866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384365242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.384365242
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1263798073
Short name T289
Test name
Test status
Simulation time 238931696 ps
CPU time 1.13 seconds
Started Jun 04 12:26:53 PM PDT 24
Finished Jun 04 12:26:58 PM PDT 24
Peak memory 196680 kb
Host smart-a93bc407-2abd-4d26-9afc-94d957e8bbb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263798073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1263798073
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2815603030
Short name T331
Test name
Test status
Simulation time 33568559404 ps
CPU time 109.53 seconds
Started Jun 04 12:26:53 PM PDT 24
Finished Jun 04 12:28:46 PM PDT 24
Peak memory 197976 kb
Host smart-69a08adf-6ba9-4c78-bab0-283cde9f910e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815603030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2815603030
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3271569184
Short name T62
Test name
Test status
Simulation time 81212757613 ps
CPU time 1566.62 seconds
Started Jun 04 12:27:00 PM PDT 24
Finished Jun 04 12:53:09 PM PDT 24
Peak memory 198064 kb
Host smart-15b8b3d5-22bb-453a-abf7-04828ab5d966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3271569184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3271569184
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1474816492
Short name T405
Test name
Test status
Simulation time 23981674 ps
CPU time 0.54 seconds
Started Jun 04 12:27:04 PM PDT 24
Finished Jun 04 12:27:07 PM PDT 24
Peak memory 193712 kb
Host smart-222f9308-818f-4da8-9c95-6a05616874c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474816492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1474816492
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2819669409
Short name T493
Test name
Test status
Simulation time 54260012 ps
CPU time 0.79 seconds
Started Jun 04 12:27:03 PM PDT 24
Finished Jun 04 12:27:06 PM PDT 24
Peak memory 195320 kb
Host smart-de3bcd36-f4b5-4821-a9d2-9dcb2df41967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819669409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2819669409
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2657276795
Short name T126
Test name
Test status
Simulation time 9322662829 ps
CPU time 24.73 seconds
Started Jun 04 12:27:05 PM PDT 24
Finished Jun 04 12:27:32 PM PDT 24
Peak memory 197996 kb
Host smart-a9599bc4-04b4-4ebe-b122-06e3c1241ffa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657276795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2657276795
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3886270694
Short name T623
Test name
Test status
Simulation time 134750953 ps
CPU time 0.7 seconds
Started Jun 04 12:27:03 PM PDT 24
Finished Jun 04 12:27:05 PM PDT 24
Peak memory 194508 kb
Host smart-2ebe6e5f-5190-4124-8f4c-1e3d29560c17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886270694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3886270694
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2879581523
Short name T391
Test name
Test status
Simulation time 235429878 ps
CPU time 1.16 seconds
Started Jun 04 12:27:04 PM PDT 24
Finished Jun 04 12:27:08 PM PDT 24
Peak memory 196736 kb
Host smart-f9a7e5f6-06cf-4e33-959f-121622f4493a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879581523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2879581523
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.257502458
Short name T146
Test name
Test status
Simulation time 125586623 ps
CPU time 2.74 seconds
Started Jun 04 12:27:03 PM PDT 24
Finished Jun 04 12:27:08 PM PDT 24
Peak memory 197928 kb
Host smart-0df72aab-3517-4841-8a05-daf492ee1dde
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257502458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.257502458
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1108147553
Short name T224
Test name
Test status
Simulation time 215077300 ps
CPU time 0.89 seconds
Started Jun 04 12:27:04 PM PDT 24
Finished Jun 04 12:27:07 PM PDT 24
Peak memory 194380 kb
Host smart-66fa1d05-93d2-4d52-b7f6-15df5ee3338e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108147553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1108147553
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3484810006
Short name T540
Test name
Test status
Simulation time 542977670 ps
CPU time 1.22 seconds
Started Jun 04 12:27:04 PM PDT 24
Finished Jun 04 12:27:07 PM PDT 24
Peak memory 195748 kb
Host smart-ae21cafa-8a55-4095-a391-c747ce254bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484810006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3484810006
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.4029945102
Short name T242
Test name
Test status
Simulation time 114986873 ps
CPU time 1.27 seconds
Started Jun 04 12:27:09 PM PDT 24
Finished Jun 04 12:27:12 PM PDT 24
Peak memory 196364 kb
Host smart-8d28862a-c095-4817-a576-e6b70412dcd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029945102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.4029945102
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.50686626
Short name T184
Test name
Test status
Simulation time 1165943240 ps
CPU time 4.72 seconds
Started Jun 04 12:27:06 PM PDT 24
Finished Jun 04 12:27:13 PM PDT 24
Peak memory 197844 kb
Host smart-7d92b05f-bc9c-4741-9889-e70a23c268bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50686626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand
om_long_reg_writes_reg_reads.50686626
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2626549730
Short name T57
Test name
Test status
Simulation time 161269195 ps
CPU time 1.29 seconds
Started Jun 04 12:26:53 PM PDT 24
Finished Jun 04 12:26:59 PM PDT 24
Peak memory 195660 kb
Host smart-37fdbc98-bb1f-466f-b568-2169d21f1d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626549730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2626549730
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1369507003
Short name T388
Test name
Test status
Simulation time 46002054 ps
CPU time 1.17 seconds
Started Jun 04 12:27:03 PM PDT 24
Finished Jun 04 12:27:05 PM PDT 24
Peak memory 196040 kb
Host smart-c33a7b25-b705-4210-be17-4b45394a1420
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369507003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1369507003
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.4275701977
Short name T2
Test name
Test status
Simulation time 21953739826 ps
CPU time 38.22 seconds
Started Jun 04 12:27:06 PM PDT 24
Finished Jun 04 12:27:46 PM PDT 24
Peak memory 198016 kb
Host smart-75702e99-0bd1-4fda-a345-39cc8570ad8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275701977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.4275701977
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3468123708
Short name T60
Test name
Test status
Simulation time 66762304579 ps
CPU time 595.27 seconds
Started Jun 04 12:27:04 PM PDT 24
Finished Jun 04 12:37:01 PM PDT 24
Peak memory 198084 kb
Host smart-c7128774-f54f-4df8-8ced-32439e8c80e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3468123708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3468123708
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4252802075
Short name T277
Test name
Test status
Simulation time 138971553 ps
CPU time 0.6 seconds
Started Jun 04 12:27:10 PM PDT 24
Finished Jun 04 12:27:12 PM PDT 24
Peak memory 193880 kb
Host smart-f5bb483c-db8b-4b6f-aaaa-7935df4e8527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252802075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4252802075
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.173423202
Short name T243
Test name
Test status
Simulation time 33875083 ps
CPU time 0.81 seconds
Started Jun 04 12:27:05 PM PDT 24
Finished Jun 04 12:27:07 PM PDT 24
Peak memory 195076 kb
Host smart-9bac6594-e897-4883-a43d-0452182727ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173423202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.173423202
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3366403919
Short name T288
Test name
Test status
Simulation time 668772112 ps
CPU time 5.48 seconds
Started Jun 04 12:27:07 PM PDT 24
Finished Jun 04 12:27:14 PM PDT 24
Peak memory 196584 kb
Host smart-3182c354-2e59-4649-8b46-523f63182cdd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366403919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3366403919
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1428794083
Short name T245
Test name
Test status
Simulation time 24552738 ps
CPU time 0.69 seconds
Started Jun 04 12:27:09 PM PDT 24
Finished Jun 04 12:27:11 PM PDT 24
Peak memory 195088 kb
Host smart-652b4bde-05ee-4ea8-a888-76225a5e71ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428794083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1428794083
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1427987199
Short name T474
Test name
Test status
Simulation time 61389639 ps
CPU time 1.11 seconds
Started Jun 04 12:27:03 PM PDT 24
Finished Jun 04 12:27:06 PM PDT 24
Peak memory 195996 kb
Host smart-d259e051-70f4-47ed-9e75-435630fb1367
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427987199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1427987199
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2955785999
Short name T496
Test name
Test status
Simulation time 28205342 ps
CPU time 1.26 seconds
Started Jun 04 12:27:07 PM PDT 24
Finished Jun 04 12:27:10 PM PDT 24
Peak memory 197340 kb
Host smart-1deb0085-4c2d-4777-a2b0-acc562531b39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955785999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2955785999
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.4226242732
Short name T144
Test name
Test status
Simulation time 672208530 ps
CPU time 3.08 seconds
Started Jun 04 12:27:09 PM PDT 24
Finished Jun 04 12:27:13 PM PDT 24
Peak memory 197888 kb
Host smart-d5ffeadb-7e04-4d8c-a1df-eaea7fc30514
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226242732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.4226242732
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2838190751
Short name T12
Test name
Test status
Simulation time 109436656 ps
CPU time 0.79 seconds
Started Jun 04 12:27:07 PM PDT 24
Finished Jun 04 12:27:09 PM PDT 24
Peak memory 196084 kb
Host smart-d6a51119-b5f2-42f8-91b2-4e53710d813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838190751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2838190751
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3731195299
Short name T151
Test name
Test status
Simulation time 413219385 ps
CPU time 1.01 seconds
Started Jun 04 12:27:11 PM PDT 24
Finished Jun 04 12:27:13 PM PDT 24
Peak memory 195780 kb
Host smart-1ddf2759-8efe-4896-8d37-836e0182eb7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731195299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3731195299
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.806050194
Short name T569
Test name
Test status
Simulation time 156947606 ps
CPU time 2.04 seconds
Started Jun 04 12:27:02 PM PDT 24
Finished Jun 04 12:27:06 PM PDT 24
Peak memory 197768 kb
Host smart-9f15af46-85eb-4074-8c16-cda3fa8f7aca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806050194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.806050194
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2506868483
Short name T696
Test name
Test status
Simulation time 29462611 ps
CPU time 0.73 seconds
Started Jun 04 12:27:05 PM PDT 24
Finished Jun 04 12:27:08 PM PDT 24
Peak memory 195804 kb
Host smart-59c1aaaa-053e-478d-95b7-22b32a686f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506868483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2506868483
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1718303508
Short name T29
Test name
Test status
Simulation time 66917754 ps
CPU time 1.01 seconds
Started Jun 04 12:27:07 PM PDT 24
Finished Jun 04 12:27:10 PM PDT 24
Peak memory 195380 kb
Host smart-c6d35801-bd0d-444c-b578-8f48d81d5237
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718303508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1718303508
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3630619631
Short name T344
Test name
Test status
Simulation time 3189539508 ps
CPU time 33.31 seconds
Started Jun 04 12:27:06 PM PDT 24
Finished Jun 04 12:27:42 PM PDT 24
Peak memory 197940 kb
Host smart-88d1ae3b-265f-41fc-9905-e0f605752759
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630619631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3630619631
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3979742837
Short name T308
Test name
Test status
Simulation time 257314596203 ps
CPU time 1741.87 seconds
Started Jun 04 12:27:10 PM PDT 24
Finished Jun 04 12:56:13 PM PDT 24
Peak memory 198032 kb
Host smart-4e939f3f-5c4d-4c39-aebe-223171edabd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3979742837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3979742837
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2790595057
Short name T199
Test name
Test status
Simulation time 12596858 ps
CPU time 0.56 seconds
Started Jun 04 12:27:04 PM PDT 24
Finished Jun 04 12:27:06 PM PDT 24
Peak memory 193740 kb
Host smart-96dd1655-844a-422a-a1c4-3c2ff6adba27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790595057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2790595057
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2226868052
Short name T685
Test name
Test status
Simulation time 263145285 ps
CPU time 0.96 seconds
Started Jun 04 12:27:08 PM PDT 24
Finished Jun 04 12:27:10 PM PDT 24
Peak memory 196308 kb
Host smart-f525497a-888f-4406-ac32-fa470c488041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226868052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2226868052
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.659520153
Short name T477
Test name
Test status
Simulation time 153237945 ps
CPU time 4.02 seconds
Started Jun 04 12:27:02 PM PDT 24
Finished Jun 04 12:27:08 PM PDT 24
Peak memory 195428 kb
Host smart-9b909113-273e-4ecc-b37f-5b423209b867
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659520153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.659520153
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2725986868
Short name T609
Test name
Test status
Simulation time 42952290 ps
CPU time 0.8 seconds
Started Jun 04 12:27:04 PM PDT 24
Finished Jun 04 12:27:07 PM PDT 24
Peak memory 195920 kb
Host smart-14e680c0-6c06-424e-81c0-c21418a7d1a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725986868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2725986868
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2111912298
Short name T701
Test name
Test status
Simulation time 209435729 ps
CPU time 1.27 seconds
Started Jun 04 12:27:04 PM PDT 24
Finished Jun 04 12:27:08 PM PDT 24
Peak memory 197036 kb
Host smart-10dced16-a421-4769-99e4-329efdd5fc0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111912298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2111912298
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3457298638
Short name T357
Test name
Test status
Simulation time 247046948 ps
CPU time 2.58 seconds
Started Jun 04 12:27:10 PM PDT 24
Finished Jun 04 12:27:14 PM PDT 24
Peak memory 197908 kb
Host smart-4371bd44-1f51-4eaf-b979-4cdbc07a84c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457298638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3457298638
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3600566275
Short name T645
Test name
Test status
Simulation time 2510644341 ps
CPU time 3.13 seconds
Started Jun 04 12:27:10 PM PDT 24
Finished Jun 04 12:27:15 PM PDT 24
Peak memory 197340 kb
Host smart-5d03701f-12bd-4867-8754-598140f87a3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600566275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3600566275
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.875041311
Short name T472
Test name
Test status
Simulation time 22212101 ps
CPU time 0.81 seconds
Started Jun 04 12:27:04 PM PDT 24
Finished Jun 04 12:27:07 PM PDT 24
Peak memory 196564 kb
Host smart-d349d540-2c0b-40fc-a60f-71f8df1e072e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875041311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.875041311
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.372184454
Short name T671
Test name
Test status
Simulation time 115879916 ps
CPU time 1.17 seconds
Started Jun 04 12:27:03 PM PDT 24
Finished Jun 04 12:27:05 PM PDT 24
Peak memory 196364 kb
Host smart-f79311e0-7d67-4568-a791-01771c737aae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372184454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.372184454
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1574574614
Short name T141
Test name
Test status
Simulation time 160858255 ps
CPU time 3.84 seconds
Started Jun 04 12:27:11 PM PDT 24
Finished Jun 04 12:27:16 PM PDT 24
Peak memory 197224 kb
Host smart-98e8b3cc-9e6e-45d6-94e5-a9ba812fbb03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574574614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1574574614
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.349510992
Short name T451
Test name
Test status
Simulation time 269424095 ps
CPU time 1.5 seconds
Started Jun 04 12:27:04 PM PDT 24
Finished Jun 04 12:27:08 PM PDT 24
Peak memory 196024 kb
Host smart-76d3d298-b97d-441e-b5a4-2d1d58691b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349510992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.349510992
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2175683606
Short name T691
Test name
Test status
Simulation time 93234084 ps
CPU time 1.21 seconds
Started Jun 04 12:27:05 PM PDT 24
Finished Jun 04 12:27:08 PM PDT 24
Peak memory 197896 kb
Host smart-dc2c6b87-5c29-4d6b-8439-e44943be1f3d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175683606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2175683606
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.438697382
Short name T517
Test name
Test status
Simulation time 52984630849 ps
CPU time 169.73 seconds
Started Jun 04 12:27:05 PM PDT 24
Finished Jun 04 12:29:56 PM PDT 24
Peak memory 197976 kb
Host smart-d0020c78-cbeb-498e-a360-cb64ed5be586
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438697382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.438697382
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.435205952
Short name T535
Test name
Test status
Simulation time 14123052 ps
CPU time 0.55 seconds
Started Jun 04 12:24:48 PM PDT 24
Finished Jun 04 12:24:51 PM PDT 24
Peak memory 194412 kb
Host smart-7415287a-a85c-4aca-8b43-fe428b358c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435205952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.435205952
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2987459060
Short name T139
Test name
Test status
Simulation time 11787799 ps
CPU time 0.57 seconds
Started Jun 04 12:24:53 PM PDT 24
Finished Jun 04 12:24:55 PM PDT 24
Peak memory 193768 kb
Host smart-450328db-28c5-424e-bb60-123d55b5126f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987459060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2987459060
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2413212251
Short name T577
Test name
Test status
Simulation time 1575838417 ps
CPU time 12.8 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:25:01 PM PDT 24
Peak memory 196548 kb
Host smart-14e7fe79-bd62-4538-a16d-dd7c255fa7a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413212251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2413212251
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.4121740590
Short name T140
Test name
Test status
Simulation time 120882056 ps
CPU time 0.92 seconds
Started Jun 04 12:24:41 PM PDT 24
Finished Jun 04 12:24:45 PM PDT 24
Peak memory 197056 kb
Host smart-1d5dadd1-f417-4cd3-87ec-5ec6d693e153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121740590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.4121740590
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1024567261
Short name T433
Test name
Test status
Simulation time 30584392 ps
CPU time 0.7 seconds
Started Jun 04 12:26:00 PM PDT 24
Finished Jun 04 12:26:02 PM PDT 24
Peak memory 194980 kb
Host smart-1a200832-36ee-441e-8551-ae933da41fa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024567261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1024567261
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.437822144
Short name T296
Test name
Test status
Simulation time 84257305 ps
CPU time 2.96 seconds
Started Jun 04 12:24:55 PM PDT 24
Finished Jun 04 12:24:59 PM PDT 24
Peak memory 197832 kb
Host smart-f23a1489-1ede-45d1-a6f6-25b866b4d14f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437822144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.437822144
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2835263438
Short name T471
Test name
Test status
Simulation time 95345480 ps
CPU time 0.87 seconds
Started Jun 04 12:24:52 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 195436 kb
Host smart-0a6abf72-5bcd-45e3-98ff-0dd5508e3fa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835263438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2835263438
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3914485000
Short name T350
Test name
Test status
Simulation time 118034450 ps
CPU time 0.76 seconds
Started Jun 04 12:24:51 PM PDT 24
Finished Jun 04 12:24:53 PM PDT 24
Peak memory 196044 kb
Host smart-a2148e22-c51c-48b5-b73e-979ecc4a2634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914485000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3914485000
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.929684713
Short name T648
Test name
Test status
Simulation time 22752576 ps
CPU time 0.63 seconds
Started Jun 04 12:25:53 PM PDT 24
Finished Jun 04 12:25:55 PM PDT 24
Peak memory 193876 kb
Host smart-2cd248f8-ece6-48df-8197-23985718c790
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929684713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.929684713
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.767360079
Short name T342
Test name
Test status
Simulation time 1944471593 ps
CPU time 6.18 seconds
Started Jun 04 12:24:53 PM PDT 24
Finished Jun 04 12:25:01 PM PDT 24
Peak memory 197796 kb
Host smart-1c04e2a7-4723-423c-a0a4-dd0202b1c310
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767360079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.767360079
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1618252086
Short name T311
Test name
Test status
Simulation time 355791954 ps
CPU time 1.12 seconds
Started Jun 04 12:24:53 PM PDT 24
Finished Jun 04 12:24:56 PM PDT 24
Peak memory 196324 kb
Host smart-6ccd3e76-49ed-4519-a9a7-a0e336a17820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618252086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1618252086
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1344514495
Short name T333
Test name
Test status
Simulation time 249258023 ps
CPU time 0.94 seconds
Started Jun 04 12:24:48 PM PDT 24
Finished Jun 04 12:24:51 PM PDT 24
Peak memory 195412 kb
Host smart-3630b287-0457-4e28-a09a-540986bb9bfc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344514495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1344514495
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1264269326
Short name T190
Test name
Test status
Simulation time 7648668664 ps
CPU time 145.95 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:28:20 PM PDT 24
Peak memory 197680 kb
Host smart-3f11793c-6e32-4028-8afe-9a67fb80ebbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264269326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1264269326
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2422183285
Short name T263
Test name
Test status
Simulation time 13019176 ps
CPU time 0.6 seconds
Started Jun 04 12:24:48 PM PDT 24
Finished Jun 04 12:24:51 PM PDT 24
Peak memory 194780 kb
Host smart-8e7cd511-aed1-457f-9ee1-d3b56885de8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422183285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2422183285
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2746152599
Short name T601
Test name
Test status
Simulation time 52963521 ps
CPU time 0.62 seconds
Started Jun 04 12:24:57 PM PDT 24
Finished Jun 04 12:24:59 PM PDT 24
Peak memory 193996 kb
Host smart-3ea5bc5e-7362-4986-95b7-b06eb8c9c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746152599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2746152599
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1127902448
Short name T593
Test name
Test status
Simulation time 3226570578 ps
CPU time 26.66 seconds
Started Jun 04 12:24:49 PM PDT 24
Finished Jun 04 12:25:17 PM PDT 24
Peak memory 196904 kb
Host smart-e53f128d-0106-451c-bed0-5fd2e0c4b485
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127902448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1127902448
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.593752961
Short name T446
Test name
Test status
Simulation time 225578287 ps
CPU time 0.64 seconds
Started Jun 04 12:24:41 PM PDT 24
Finished Jun 04 12:24:45 PM PDT 24
Peak memory 194380 kb
Host smart-c23541fc-e013-4136-b14a-ac23d0dfacb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593752961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.593752961
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2413534594
Short name T290
Test name
Test status
Simulation time 63113745 ps
CPU time 1.05 seconds
Started Jun 04 12:24:52 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 195840 kb
Host smart-4988e635-02bb-4f08-b3d9-1a9e293cb8e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413534594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2413534594
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3110388598
Short name T207
Test name
Test status
Simulation time 306856191 ps
CPU time 1.67 seconds
Started Jun 04 12:24:50 PM PDT 24
Finished Jun 04 12:24:53 PM PDT 24
Peak memory 197120 kb
Host smart-f383fbde-9845-46b8-a1c9-e9366edb60d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110388598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3110388598
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3583668182
Short name T15
Test name
Test status
Simulation time 553606355 ps
CPU time 3 seconds
Started Jun 04 12:24:50 PM PDT 24
Finished Jun 04 12:24:55 PM PDT 24
Peak memory 195632 kb
Host smart-59b620d4-690c-4567-89fd-4d6e07d43d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583668182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3583668182
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2575997443
Short name T630
Test name
Test status
Simulation time 74103776 ps
CPU time 0.7 seconds
Started Jun 04 12:24:52 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 195292 kb
Host smart-cf32c0b9-a987-4e5c-a863-d60ba10e4c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575997443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2575997443
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1093090138
Short name T334
Test name
Test status
Simulation time 151497953 ps
CPU time 0.86 seconds
Started Jun 04 12:24:51 PM PDT 24
Finished Jun 04 12:24:53 PM PDT 24
Peak memory 196448 kb
Host smart-3021199d-e806-4446-9985-981ca35f0d29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093090138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1093090138
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.702050751
Short name T608
Test name
Test status
Simulation time 1471450833 ps
CPU time 5.53 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 197748 kb
Host smart-21823311-2db2-4204-8aad-e6f670bc09eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702050751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.702050751
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.759785583
Short name T136
Test name
Test status
Simulation time 353755790 ps
CPU time 1.28 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:24:48 PM PDT 24
Peak memory 196096 kb
Host smart-678c0254-2aeb-4312-afcb-e43f0feab52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759785583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.759785583
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2447584104
Short name T380
Test name
Test status
Simulation time 32745219 ps
CPU time 0.95 seconds
Started Jun 04 12:24:52 PM PDT 24
Finished Jun 04 12:24:55 PM PDT 24
Peak memory 196300 kb
Host smart-1464a756-0387-4065-92f4-ba005d2e7685
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447584104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2447584104
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1482543241
Short name T542
Test name
Test status
Simulation time 26916230495 ps
CPU time 139.99 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:27:08 PM PDT 24
Peak memory 197972 kb
Host smart-5dc598aa-2ddd-458f-a227-6ac5a5b5063e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482543241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1482543241
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.2516836363
Short name T530
Test name
Test status
Simulation time 66527879314 ps
CPU time 794.8 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:38:02 PM PDT 24
Peak memory 198072 kb
Host smart-1ab244c1-8d05-4efe-b6d3-a965f2c88818
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2516836363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.2516836363
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4008840031
Short name T394
Test name
Test status
Simulation time 13343895 ps
CPU time 0.56 seconds
Started Jun 04 12:25:03 PM PDT 24
Finished Jun 04 12:25:05 PM PDT 24
Peak memory 193628 kb
Host smart-fe1d62a7-30ab-423f-a225-f53b678229cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008840031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4008840031
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2247375255
Short name T287
Test name
Test status
Simulation time 52635718 ps
CPU time 0.86 seconds
Started Jun 04 12:24:52 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 196416 kb
Host smart-ee647c02-f3a2-4320-a392-74f6105245ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247375255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2247375255
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2109122314
Short name T613
Test name
Test status
Simulation time 139393909 ps
CPU time 3.93 seconds
Started Jun 04 12:24:58 PM PDT 24
Finished Jun 04 12:25:03 PM PDT 24
Peak memory 195764 kb
Host smart-b79df763-55ea-46d9-820a-fc5f26fbe009
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109122314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2109122314
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1890316322
Short name T583
Test name
Test status
Simulation time 37152560 ps
CPU time 0.75 seconds
Started Jun 04 12:25:06 PM PDT 24
Finished Jun 04 12:25:09 PM PDT 24
Peak memory 196604 kb
Host smart-419b7993-da15-4b70-9f0d-edc9bb52c6e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890316322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1890316322
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1809922184
Short name T449
Test name
Test status
Simulation time 173550723 ps
CPU time 0.69 seconds
Started Jun 04 12:25:52 PM PDT 24
Finished Jun 04 12:25:55 PM PDT 24
Peak memory 194964 kb
Host smart-9660ff44-d068-45a8-8bc1-2110e4b49e1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809922184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1809922184
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3737844193
Short name T524
Test name
Test status
Simulation time 19720006 ps
CPU time 0.85 seconds
Started Jun 04 12:24:54 PM PDT 24
Finished Jun 04 12:24:56 PM PDT 24
Peak memory 195812 kb
Host smart-674ab321-7b22-4bb1-9074-e3c317b79922
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737844193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3737844193
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2439816322
Short name T338
Test name
Test status
Simulation time 498089201 ps
CPU time 2.79 seconds
Started Jun 04 12:24:47 PM PDT 24
Finished Jun 04 12:24:52 PM PDT 24
Peak memory 197116 kb
Host smart-2b7521b3-a0a9-4ba3-a81d-2bff34264b07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439816322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2439816322
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.492244838
Short name T273
Test name
Test status
Simulation time 29007846 ps
CPU time 0.71 seconds
Started Jun 04 12:24:54 PM PDT 24
Finished Jun 04 12:24:56 PM PDT 24
Peak memory 195272 kb
Host smart-da69b579-1e6f-4187-b112-27569feee063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492244838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.492244838
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.793205363
Short name T516
Test name
Test status
Simulation time 58785684 ps
CPU time 1.04 seconds
Started Jun 04 12:24:51 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 196656 kb
Host smart-faf33e2a-b332-45ca-b21f-7d847a1a3e85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793205363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.793205363
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.424501376
Short name T597
Test name
Test status
Simulation time 697807609 ps
CPU time 2.55 seconds
Started Jun 04 12:24:58 PM PDT 24
Finished Jun 04 12:25:02 PM PDT 24
Peak memory 197880 kb
Host smart-7fe9d4f4-d793-4b18-8b7a-00cd231b08f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424501376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.424501376
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.754348638
Short name T94
Test name
Test status
Simulation time 123764361 ps
CPU time 1.11 seconds
Started Jun 04 12:24:50 PM PDT 24
Finished Jun 04 12:24:53 PM PDT 24
Peak memory 195640 kb
Host smart-32892466-34ef-4aac-9fd1-4098c35a8a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754348638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.754348638
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3535151329
Short name T13
Test name
Test status
Simulation time 1238645534 ps
CPU time 1.48 seconds
Started Jun 04 12:24:49 PM PDT 24
Finished Jun 04 12:24:51 PM PDT 24
Peak memory 196680 kb
Host smart-d6f9a264-b84c-4d85-8b3d-6773c8f89013
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535151329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3535151329
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2423543158
Short name T186
Test name
Test status
Simulation time 6613110101 ps
CPU time 88.31 seconds
Started Jun 04 12:25:07 PM PDT 24
Finished Jun 04 12:26:37 PM PDT 24
Peak memory 198028 kb
Host smart-f8840c82-7b0f-4203-acce-da9c2725d049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423543158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2423543158
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.669010517
Short name T40
Test name
Test status
Simulation time 20064444 ps
CPU time 0.56 seconds
Started Jun 04 12:25:03 PM PDT 24
Finished Jun 04 12:25:05 PM PDT 24
Peak memory 194580 kb
Host smart-048471d3-2709-4ffc-8105-29c49dedaa6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669010517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.669010517
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1901996688
Short name T239
Test name
Test status
Simulation time 64788650 ps
CPU time 0.69 seconds
Started Jun 04 12:25:03 PM PDT 24
Finished Jun 04 12:25:05 PM PDT 24
Peak memory 195184 kb
Host smart-18feb747-9054-4f9a-8016-e57417d1bca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901996688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1901996688
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.572157550
Short name T714
Test name
Test status
Simulation time 992125076 ps
CPU time 12.22 seconds
Started Jun 04 12:24:52 PM PDT 24
Finished Jun 04 12:25:06 PM PDT 24
Peak memory 197804 kb
Host smart-b9cf5670-5052-4e3d-8a31-74fb2b75cf74
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572157550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.572157550
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1193107715
Short name T340
Test name
Test status
Simulation time 509051800 ps
CPU time 1.02 seconds
Started Jun 04 12:25:03 PM PDT 24
Finished Jun 04 12:25:05 PM PDT 24
Peak memory 196116 kb
Host smart-c0101214-a88a-4dbe-8f55-44c9973ae60f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193107715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1193107715
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.848830187
Short name T214
Test name
Test status
Simulation time 67090154 ps
CPU time 0.96 seconds
Started Jun 04 12:25:04 PM PDT 24
Finished Jun 04 12:25:06 PM PDT 24
Peak memory 195620 kb
Host smart-6c7f62d1-0543-4924-b93e-96fb53535192
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848830187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.848830187
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1217457878
Short name T24
Test name
Test status
Simulation time 78095082 ps
CPU time 2.59 seconds
Started Jun 04 12:24:57 PM PDT 24
Finished Jun 04 12:25:01 PM PDT 24
Peak memory 196148 kb
Host smart-1a138ca5-9feb-4eb5-a9f4-e95d90de0e19
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217457878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1217457878
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2020320442
Short name T120
Test name
Test status
Simulation time 47630368 ps
CPU time 1.39 seconds
Started Jun 04 12:24:57 PM PDT 24
Finished Jun 04 12:24:59 PM PDT 24
Peak memory 196020 kb
Host smart-f9974daf-e7df-4c41-9f3f-770a97175c21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020320442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2020320442
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.181093113
Short name T367
Test name
Test status
Simulation time 30764076 ps
CPU time 1.1 seconds
Started Jun 04 12:24:55 PM PDT 24
Finished Jun 04 12:24:57 PM PDT 24
Peak memory 197872 kb
Host smart-70492732-7a86-4ffb-8b44-c1e558182721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181093113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.181093113
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2477880375
Short name T115
Test name
Test status
Simulation time 73240620 ps
CPU time 1.2 seconds
Started Jun 04 12:24:54 PM PDT 24
Finished Jun 04 12:24:57 PM PDT 24
Peak memory 196892 kb
Host smart-31de58fa-4315-4b07-80a6-db594184ef93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477880375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2477880375
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.378588127
Short name T9
Test name
Test status
Simulation time 372563646 ps
CPU time 4.56 seconds
Started Jun 04 12:25:01 PM PDT 24
Finished Jun 04 12:25:06 PM PDT 24
Peak memory 197740 kb
Host smart-94ff4a5a-77aa-44c0-b2f6-f784ad977442
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378588127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.378588127
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3878456277
Short name T253
Test name
Test status
Simulation time 47566544 ps
CPU time 0.96 seconds
Started Jun 04 12:25:53 PM PDT 24
Finished Jun 04 12:25:56 PM PDT 24
Peak memory 195428 kb
Host smart-9c1af08e-6dcf-45ad-86ce-5af1674a56e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878456277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3878456277
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3649302167
Short name T341
Test name
Test status
Simulation time 123525499 ps
CPU time 1.26 seconds
Started Jun 04 12:25:04 PM PDT 24
Finished Jun 04 12:25:07 PM PDT 24
Peak memory 196576 kb
Host smart-bfe9b704-5064-4183-92f5-6fc481146e20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649302167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3649302167
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3964984725
Short name T550
Test name
Test status
Simulation time 178556953917 ps
CPU time 125.85 seconds
Started Jun 04 12:26:07 PM PDT 24
Finished Jun 04 12:28:15 PM PDT 24
Peak memory 197948 kb
Host smart-e2ef8dd2-e2d7-410b-adcc-bb2ce2208d32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964984725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3964984725
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3332674209
Short name T460
Test name
Test status
Simulation time 11546260 ps
CPU time 0.55 seconds
Started Jun 04 12:25:06 PM PDT 24
Finished Jun 04 12:25:08 PM PDT 24
Peak memory 193828 kb
Host smart-f30d4e06-6680-4999-a54c-d0259f0952c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332674209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3332674209
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1371820198
Short name T556
Test name
Test status
Simulation time 21085365 ps
CPU time 0.73 seconds
Started Jun 04 12:26:07 PM PDT 24
Finished Jun 04 12:26:10 PM PDT 24
Peak memory 193960 kb
Host smart-6612746a-c566-45f7-b217-4d8a392b19b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371820198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1371820198
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3174328851
Short name T634
Test name
Test status
Simulation time 2170813820 ps
CPU time 10.34 seconds
Started Jun 04 12:24:56 PM PDT 24
Finished Jun 04 12:25:08 PM PDT 24
Peak memory 196764 kb
Host smart-05900f94-4a95-4f97-a04d-ace425dee91b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174328851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3174328851
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3003904824
Short name T248
Test name
Test status
Simulation time 24430859 ps
CPU time 0.64 seconds
Started Jun 04 12:25:06 PM PDT 24
Finished Jun 04 12:25:08 PM PDT 24
Peak memory 194384 kb
Host smart-59c952c6-b40a-4dad-a5fc-312e49dbaf1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003904824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3003904824
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4029779544
Short name T131
Test name
Test status
Simulation time 69025320 ps
CPU time 0.66 seconds
Started Jun 04 12:24:50 PM PDT 24
Finished Jun 04 12:24:52 PM PDT 24
Peak memory 194372 kb
Host smart-a80f3d43-dfd5-4cec-a0c7-480bd902ac63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029779544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4029779544
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2556731300
Short name T272
Test name
Test status
Simulation time 44600552 ps
CPU time 1.21 seconds
Started Jun 04 12:25:03 PM PDT 24
Finished Jun 04 12:25:05 PM PDT 24
Peak memory 196480 kb
Host smart-2d7cd14c-5622-4e7a-b5f3-3ccadaa47188
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556731300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2556731300
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.304337203
Short name T378
Test name
Test status
Simulation time 199025022 ps
CPU time 1.97 seconds
Started Jun 04 12:25:07 PM PDT 24
Finished Jun 04 12:25:10 PM PDT 24
Peak memory 195932 kb
Host smart-8cc02ddc-74d7-4c28-9bc8-662c75e70fe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304337203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.304337203
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3853982545
Short name T492
Test name
Test status
Simulation time 165179503 ps
CPU time 0.92 seconds
Started Jun 04 12:24:51 PM PDT 24
Finished Jun 04 12:24:53 PM PDT 24
Peak memory 195700 kb
Host smart-a67568b0-c19b-4421-977d-a977c6df7512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853982545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3853982545
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1991973058
Short name T117
Test name
Test status
Simulation time 36421499 ps
CPU time 0.85 seconds
Started Jun 04 12:25:06 PM PDT 24
Finished Jun 04 12:25:09 PM PDT 24
Peak memory 196436 kb
Host smart-556923db-8522-4ee0-a2fb-f3285a47f700
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991973058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1991973058
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1076144540
Short name T202
Test name
Test status
Simulation time 179437511 ps
CPU time 2.3 seconds
Started Jun 04 12:24:52 PM PDT 24
Finished Jun 04 12:24:56 PM PDT 24
Peak memory 197748 kb
Host smart-596efd79-a9f8-4668-a232-9608f916b5fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076144540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1076144540
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2557155095
Short name T390
Test name
Test status
Simulation time 166632144 ps
CPU time 1.11 seconds
Started Jun 04 12:25:03 PM PDT 24
Finished Jun 04 12:25:05 PM PDT 24
Peak memory 196072 kb
Host smart-0ea0d974-8f64-4766-969f-72d5b4b398e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557155095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2557155095
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2047876953
Short name T229
Test name
Test status
Simulation time 93167578 ps
CPU time 0.92 seconds
Started Jun 04 12:24:58 PM PDT 24
Finished Jun 04 12:25:00 PM PDT 24
Peak memory 196436 kb
Host smart-1309f58a-6c38-4cde-8074-d47cda5fa29c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047876953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2047876953
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2035546110
Short name T97
Test name
Test status
Simulation time 33726096475 ps
CPU time 224.65 seconds
Started Jun 04 12:25:02 PM PDT 24
Finished Jun 04 12:28:48 PM PDT 24
Peak memory 198012 kb
Host smart-24dfe237-17b7-4e59-9daa-49a8722cf9f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035546110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2035546110
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2553888812
Short name T919
Test name
Test status
Simulation time 83844598 ps
CPU time 1.04 seconds
Started Jun 04 12:24:03 PM PDT 24
Finished Jun 04 12:24:06 PM PDT 24
Peak memory 197968 kb
Host smart-2f42b3ea-fc1d-46e4-8511-ffb1cc949381
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2553888812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2553888812
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.137296424
Short name T912
Test name
Test status
Simulation time 41291133 ps
CPU time 1.14 seconds
Started Jun 04 12:21:30 PM PDT 24
Finished Jun 04 12:21:32 PM PDT 24
Peak memory 197952 kb
Host smart-76812f3e-1db3-459d-9113-727dc25b3d92
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137296424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.137296424
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1045604886
Short name T858
Test name
Test status
Simulation time 157971326 ps
CPU time 1.24 seconds
Started Jun 04 12:22:16 PM PDT 24
Finished Jun 04 12:22:18 PM PDT 24
Peak memory 196220 kb
Host smart-133c4f99-4cea-46cb-af7e-5e914293e995
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1045604886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1045604886
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2175127967
Short name T853
Test name
Test status
Simulation time 99483273 ps
CPU time 0.81 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:23:10 PM PDT 24
Peak memory 195268 kb
Host smart-24e30d9e-bab3-4166-b131-7403160bb7fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175127967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2175127967
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.559673757
Short name T940
Test name
Test status
Simulation time 42661616 ps
CPU time 0.93 seconds
Started Jun 04 12:19:20 PM PDT 24
Finished Jun 04 12:19:22 PM PDT 24
Peak memory 196664 kb
Host smart-286acfe8-49e3-492e-bfc7-ba6f5952045c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=559673757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.559673757
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2301013808
Short name T905
Test name
Test status
Simulation time 44959736 ps
CPU time 1.03 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 196436 kb
Host smart-a00bad99-ec36-4a17-9552-e5f8f9d91f0d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301013808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2301013808
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.406605544
Short name T945
Test name
Test status
Simulation time 192637452 ps
CPU time 1.48 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:35 PM PDT 24
Peak memory 195896 kb
Host smart-37592c65-6b3e-4b42-8d78-7b93b4d3f5cc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=406605544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.406605544
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3447373361
Short name T870
Test name
Test status
Simulation time 139374106 ps
CPU time 0.84 seconds
Started Jun 04 12:23:59 PM PDT 24
Finished Jun 04 12:24:01 PM PDT 24
Peak memory 195152 kb
Host smart-fb4df19a-175e-4353-9422-e26755504c7f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447373361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3447373361
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2759058008
Short name T875
Test name
Test status
Simulation time 31782215 ps
CPU time 1.05 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:23:17 PM PDT 24
Peak memory 197708 kb
Host smart-36dc577a-0606-402f-8b23-8aa57debec38
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2759058008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2759058008
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3977870811
Short name T891
Test name
Test status
Simulation time 194505264 ps
CPU time 1.49 seconds
Started Jun 04 12:23:04 PM PDT 24
Finished Jun 04 12:23:07 PM PDT 24
Peak memory 195296 kb
Host smart-831b97e6-9868-4974-a3e8-e32db0e41023
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977870811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3977870811
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2721644708
Short name T886
Test name
Test status
Simulation time 35220365 ps
CPU time 0.87 seconds
Started Jun 04 12:23:04 PM PDT 24
Finished Jun 04 12:23:07 PM PDT 24
Peak memory 193524 kb
Host smart-c25ec219-f598-4bc9-94ca-128894811297
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2721644708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2721644708
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3661356200
Short name T927
Test name
Test status
Simulation time 79637451 ps
CPU time 0.84 seconds
Started Jun 04 12:23:59 PM PDT 24
Finished Jun 04 12:24:00 PM PDT 24
Peak memory 196268 kb
Host smart-785f8469-8525-4d6a-8ece-85ca91dd18cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661356200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3661356200
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.919490952
Short name T904
Test name
Test status
Simulation time 71654730 ps
CPU time 0.75 seconds
Started Jun 04 12:21:30 PM PDT 24
Finished Jun 04 12:21:32 PM PDT 24
Peak memory 195268 kb
Host smart-f8fc3233-32cb-43ba-b9b5-b2a2aae4abc6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=919490952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.919490952
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2818820883
Short name T901
Test name
Test status
Simulation time 47632389 ps
CPU time 1.04 seconds
Started Jun 04 12:23:15 PM PDT 24
Finished Jun 04 12:23:17 PM PDT 24
Peak memory 197444 kb
Host smart-66da3506-630f-4003-8c84-b1f14e220364
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818820883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2818820883
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1186998259
Short name T893
Test name
Test status
Simulation time 233322792 ps
CPU time 1.08 seconds
Started Jun 04 12:23:35 PM PDT 24
Finished Jun 04 12:23:38 PM PDT 24
Peak memory 196312 kb
Host smart-82bbe7e2-dd7c-4e2a-a2c2-3ae98bfa48ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1186998259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1186998259
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1414186732
Short name T909
Test name
Test status
Simulation time 418472601 ps
CPU time 1.51 seconds
Started Jun 04 12:21:55 PM PDT 24
Finished Jun 04 12:21:57 PM PDT 24
Peak memory 196768 kb
Host smart-27203176-0700-480a-8439-5d39656af8c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414186732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1414186732
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.950456621
Short name T933
Test name
Test status
Simulation time 154102065 ps
CPU time 0.94 seconds
Started Jun 04 12:23:35 PM PDT 24
Finished Jun 04 12:23:38 PM PDT 24
Peak memory 197736 kb
Host smart-5a7bc316-1cba-44ad-9446-32973c69a58a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=950456621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.950456621
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3572179755
Short name T848
Test name
Test status
Simulation time 82600932 ps
CPU time 1.02 seconds
Started Jun 04 12:23:33 PM PDT 24
Finished Jun 04 12:23:36 PM PDT 24
Peak memory 197980 kb
Host smart-a069ba48-4cf8-45e3-b7ec-4d2d44b787f6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572179755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3572179755
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3820991675
Short name T882
Test name
Test status
Simulation time 91235045 ps
CPU time 0.93 seconds
Started Jun 04 12:23:12 PM PDT 24
Finished Jun 04 12:23:14 PM PDT 24
Peak memory 196036 kb
Host smart-c6e9abc9-bbc7-47b1-81fd-c9b17b985563
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3820991675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3820991675
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.44878453
Short name T846
Test name
Test status
Simulation time 297520500 ps
CPU time 0.92 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:23:23 PM PDT 24
Peak memory 197176 kb
Host smart-edad85ec-83b5-4bb1-9d1a-e2ae4b61f1a8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44878453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.44878453
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3164919147
Short name T854
Test name
Test status
Simulation time 147487595 ps
CPU time 1.05 seconds
Started Jun 04 12:23:46 PM PDT 24
Finished Jun 04 12:23:48 PM PDT 24
Peak memory 196308 kb
Host smart-efc3fe8f-b840-40fe-af06-e3f2b009666f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3164919147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3164919147
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2784977968
Short name T873
Test name
Test status
Simulation time 581696841 ps
CPU time 1.35 seconds
Started Jun 04 12:20:22 PM PDT 24
Finished Jun 04 12:20:24 PM PDT 24
Peak memory 196412 kb
Host smart-7293d8fc-0a89-4566-a38c-57b2bd49e69d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784977968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2784977968
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1748306810
Short name T890
Test name
Test status
Simulation time 131937414 ps
CPU time 1.12 seconds
Started Jun 04 12:18:10 PM PDT 24
Finished Jun 04 12:18:12 PM PDT 24
Peak memory 196552 kb
Host smart-06861ac2-125d-4861-8353-5161865b70ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1748306810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1748306810
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2166194392
Short name T894
Test name
Test status
Simulation time 60260726 ps
CPU time 1.33 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:23:59 PM PDT 24
Peak memory 196860 kb
Host smart-6ab0ad84-c4de-41ac-bd82-32377fc3f00f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166194392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2166194392
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3376558868
Short name T938
Test name
Test status
Simulation time 38813904 ps
CPU time 0.95 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 195228 kb
Host smart-e9de6c10-e8de-4328-b89b-b6ed821b7891
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3376558868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3376558868
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4179217809
Short name T881
Test name
Test status
Simulation time 368450906 ps
CPU time 1.46 seconds
Started Jun 04 12:24:03 PM PDT 24
Finished Jun 04 12:24:06 PM PDT 24
Peak memory 197364 kb
Host smart-d75c18d8-0db1-47fd-87fc-f4088254e5ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179217809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4179217809
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1883113451
Short name T936
Test name
Test status
Simulation time 29411454 ps
CPU time 0.75 seconds
Started Jun 04 12:21:09 PM PDT 24
Finished Jun 04 12:21:10 PM PDT 24
Peak memory 194392 kb
Host smart-418d8c06-065c-4249-a813-9491cb2cd2ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1883113451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1883113451
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2851352182
Short name T860
Test name
Test status
Simulation time 119566792 ps
CPU time 1.08 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:23:58 PM PDT 24
Peak memory 196280 kb
Host smart-510898d7-52b8-4111-af88-3f3a9c367205
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851352182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2851352182
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1961770807
Short name T916
Test name
Test status
Simulation time 1324980652 ps
CPU time 1.38 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:23:59 PM PDT 24
Peak memory 197692 kb
Host smart-3dbb53ce-20e5-45cf-a9f5-13cf521f9129
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1961770807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1961770807
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3611101263
Short name T864
Test name
Test status
Simulation time 50638424 ps
CPU time 0.82 seconds
Started Jun 04 12:19:44 PM PDT 24
Finished Jun 04 12:19:46 PM PDT 24
Peak memory 197760 kb
Host smart-062581bf-4d9a-4ac1-8a22-1db5896f76d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611101263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3611101263
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2647955236
Short name T931
Test name
Test status
Simulation time 179274604 ps
CPU time 1.06 seconds
Started Jun 04 12:19:45 PM PDT 24
Finished Jun 04 12:19:46 PM PDT 24
Peak memory 197836 kb
Host smart-6e31232b-0d53-4b53-aae3-37ac44e48d58
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2647955236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2647955236
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2679284200
Short name T884
Test name
Test status
Simulation time 97219494 ps
CPU time 0.95 seconds
Started Jun 04 12:18:52 PM PDT 24
Finished Jun 04 12:18:54 PM PDT 24
Peak memory 195468 kb
Host smart-ef043a29-a2ab-4ef5-a28a-57701ee36871
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679284200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2679284200
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3714369117
Short name T847
Test name
Test status
Simulation time 99471444 ps
CPU time 1.42 seconds
Started Jun 04 12:23:54 PM PDT 24
Finished Jun 04 12:23:57 PM PDT 24
Peak memory 196064 kb
Host smart-7de0e999-36c4-4800-a1a2-b506995656bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3714369117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3714369117
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3793178419
Short name T917
Test name
Test status
Simulation time 153086129 ps
CPU time 1.16 seconds
Started Jun 04 12:24:03 PM PDT 24
Finished Jun 04 12:24:06 PM PDT 24
Peak memory 196660 kb
Host smart-880c5634-35ed-4ad8-ae12-479ec64cb005
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793178419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3793178419
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2035257390
Short name T932
Test name
Test status
Simulation time 300667855 ps
CPU time 1.26 seconds
Started Jun 04 12:18:53 PM PDT 24
Finished Jun 04 12:18:54 PM PDT 24
Peak memory 198016 kb
Host smart-f8718e8b-c28c-48d0-abf3-d554ad0aab72
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2035257390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2035257390
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1503251661
Short name T868
Test name
Test status
Simulation time 114663258 ps
CPU time 1.08 seconds
Started Jun 04 12:20:23 PM PDT 24
Finished Jun 04 12:20:24 PM PDT 24
Peak memory 196680 kb
Host smart-ebc0bc7a-3411-446c-a825-a13e2269b29a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503251661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1503251661
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.872917874
Short name T900
Test name
Test status
Simulation time 155168390 ps
CPU time 0.96 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:23:16 PM PDT 24
Peak memory 197860 kb
Host smart-01cdb9e1-baed-417f-9ef4-83579d80dd02
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=872917874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.872917874
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3302332104
Short name T852
Test name
Test status
Simulation time 38345456 ps
CPU time 0.87 seconds
Started Jun 04 12:21:03 PM PDT 24
Finished Jun 04 12:21:05 PM PDT 24
Peak memory 196376 kb
Host smart-2058d30a-78c8-402c-942f-237a2d5699c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302332104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3302332104
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1474878876
Short name T903
Test name
Test status
Simulation time 130200633 ps
CPU time 1.11 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 195320 kb
Host smart-8ae8b8b3-c32d-4798-990e-9270b9045323
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1474878876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1474878876
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3492994147
Short name T892
Test name
Test status
Simulation time 80193017 ps
CPU time 1.03 seconds
Started Jun 04 12:19:21 PM PDT 24
Finished Jun 04 12:19:23 PM PDT 24
Peak memory 196768 kb
Host smart-991a5be5-0809-4507-b175-27eabf8ae5f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492994147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3492994147
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1991279620
Short name T899
Test name
Test status
Simulation time 205522622 ps
CPU time 1.24 seconds
Started Jun 04 12:23:57 PM PDT 24
Finished Jun 04 12:24:00 PM PDT 24
Peak memory 197920 kb
Host smart-275a89a0-9b10-4116-96c3-5d9dcd498533
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1991279620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1991279620
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.916927914
Short name T898
Test name
Test status
Simulation time 165020191 ps
CPU time 1.23 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:23:17 PM PDT 24
Peak memory 196624 kb
Host smart-201a2409-1164-4ae6-87f0-7c03374aba7c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916927914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.916927914
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3102196085
Short name T926
Test name
Test status
Simulation time 309268437 ps
CPU time 1.12 seconds
Started Jun 04 12:24:03 PM PDT 24
Finished Jun 04 12:24:06 PM PDT 24
Peak memory 195696 kb
Host smart-1620cbc9-ac6c-4ca7-971c-3f1a1d96198b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3102196085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3102196085
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3773449756
Short name T937
Test name
Test status
Simulation time 34822069 ps
CPU time 1.1 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 196676 kb
Host smart-56a1a1d2-8cbd-490f-a187-62aa976cd16d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773449756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3773449756
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1743906359
Short name T935
Test name
Test status
Simulation time 79822554 ps
CPU time 0.97 seconds
Started Jun 04 12:23:11 PM PDT 24
Finished Jun 04 12:23:13 PM PDT 24
Peak memory 194724 kb
Host smart-4fb5a51b-40ff-480b-a14e-12c9786b7e80
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1743906359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1743906359
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2486306897
Short name T918
Test name
Test status
Simulation time 34173084 ps
CPU time 1.1 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:33 PM PDT 24
Peak memory 196632 kb
Host smart-30a50fa4-b843-4cf1-8f1f-b0a7efcb0758
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486306897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2486306897
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.523716938
Short name T872
Test name
Test status
Simulation time 95067119 ps
CPU time 1.07 seconds
Started Jun 04 12:17:55 PM PDT 24
Finished Jun 04 12:17:57 PM PDT 24
Peak memory 196536 kb
Host smart-3c439cd8-31ce-47aa-b0c6-3d2e65dcae25
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=523716938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.523716938
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2390063386
Short name T861
Test name
Test status
Simulation time 196295895 ps
CPU time 0.75 seconds
Started Jun 04 12:20:21 PM PDT 24
Finished Jun 04 12:20:22 PM PDT 24
Peak memory 195540 kb
Host smart-c49adfde-dba7-4554-b68a-84396c320d3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390063386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2390063386
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1295181722
Short name T869
Test name
Test status
Simulation time 77533261 ps
CPU time 1.35 seconds
Started Jun 04 12:23:22 PM PDT 24
Finished Jun 04 12:23:24 PM PDT 24
Peak memory 196544 kb
Host smart-5c498b3b-73e5-46df-ada2-564255e72a70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1295181722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1295181722
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2482833149
Short name T928
Test name
Test status
Simulation time 409440494 ps
CPU time 1 seconds
Started Jun 04 12:23:11 PM PDT 24
Finished Jun 04 12:23:13 PM PDT 24
Peak memory 195420 kb
Host smart-f408c44c-5a23-4774-a7ee-02d4a7d5a0fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482833149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2482833149
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.944321579
Short name T896
Test name
Test status
Simulation time 77267075 ps
CPU time 0.98 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:23:10 PM PDT 24
Peak memory 195648 kb
Host smart-e0f788c6-0b97-40cb-b172-69935f19e5ef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=944321579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.944321579
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2301128596
Short name T880
Test name
Test status
Simulation time 73062863 ps
CPU time 1.3 seconds
Started Jun 04 12:23:43 PM PDT 24
Finished Jun 04 12:23:45 PM PDT 24
Peak memory 195644 kb
Host smart-1c07d5b3-6ab3-4c56-a446-f5b094d7c454
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301128596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2301128596
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.682064175
Short name T887
Test name
Test status
Simulation time 39281216 ps
CPU time 1.08 seconds
Started Jun 04 12:22:24 PM PDT 24
Finished Jun 04 12:22:26 PM PDT 24
Peak memory 194404 kb
Host smart-c36fa9a9-3823-41df-aff6-82c76d8a638d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=682064175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.682064175
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2617082502
Short name T889
Test name
Test status
Simulation time 104459345 ps
CPU time 1.05 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 194476 kb
Host smart-2204aeab-3bfb-4ba5-b7df-eee32a73bcc6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617082502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2617082502
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3074727548
Short name T944
Test name
Test status
Simulation time 100012652 ps
CPU time 1.4 seconds
Started Jun 04 12:23:42 PM PDT 24
Finished Jun 04 12:23:44 PM PDT 24
Peak memory 197328 kb
Host smart-a09638db-9229-45f3-aa46-46cd94a9f777
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3074727548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3074727548
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2410183314
Short name T943
Test name
Test status
Simulation time 1693187363 ps
CPU time 1.47 seconds
Started Jun 04 12:18:40 PM PDT 24
Finished Jun 04 12:18:42 PM PDT 24
Peak memory 196828 kb
Host smart-d5134877-6886-4a36-a7d4-f09921b5ce48
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410183314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2410183314
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1996523987
Short name T863
Test name
Test status
Simulation time 38971032 ps
CPU time 0.94 seconds
Started Jun 04 12:22:24 PM PDT 24
Finished Jun 04 12:22:26 PM PDT 24
Peak memory 195404 kb
Host smart-063cbc3e-36b2-4c84-a4f4-9262c53649d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1996523987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1996523987
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1617796999
Short name T874
Test name
Test status
Simulation time 53044300 ps
CPU time 0.86 seconds
Started Jun 04 12:22:24 PM PDT 24
Finished Jun 04 12:22:26 PM PDT 24
Peak memory 193944 kb
Host smart-9d0e53f8-3be3-44de-9c62-7140c9e05279
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617796999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1617796999
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4045879441
Short name T922
Test name
Test status
Simulation time 66664628 ps
CPU time 0.98 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 195488 kb
Host smart-0a6bcfe8-43fe-4e64-b147-6cf32d0cd645
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4045879441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4045879441
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1323844261
Short name T913
Test name
Test status
Simulation time 112109183 ps
CPU time 1.33 seconds
Started Jun 04 12:21:28 PM PDT 24
Finished Jun 04 12:21:30 PM PDT 24
Peak memory 196584 kb
Host smart-fd04ce81-eea9-4270-97dc-a4bcbca7f4a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323844261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1323844261
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3360229776
Short name T878
Test name
Test status
Simulation time 261525918 ps
CPU time 1.08 seconds
Started Jun 04 12:22:25 PM PDT 24
Finished Jun 04 12:22:27 PM PDT 24
Peak memory 195428 kb
Host smart-3cb59e58-79cb-4352-953e-ca769d7b71e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3360229776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3360229776
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2834549391
Short name T849
Test name
Test status
Simulation time 211636754 ps
CPU time 1.18 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:35 PM PDT 24
Peak memory 196184 kb
Host smart-3ca23c4b-3611-421f-adb1-6c8372e50478
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834549391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2834549391
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1941338315
Short name T911
Test name
Test status
Simulation time 248399249 ps
CPU time 1.04 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:23:16 PM PDT 24
Peak memory 195296 kb
Host smart-e4fd2038-d974-4691-9cfd-3dce2fc36840
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1941338315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1941338315
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.7510897
Short name T906
Test name
Test status
Simulation time 90362518 ps
CPU time 1.3 seconds
Started Jun 04 12:23:59 PM PDT 24
Finished Jun 04 12:24:01 PM PDT 24
Peak memory 197716 kb
Host smart-118f84cf-7292-4cb8-96f2-880b193a691c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7510897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.7510897
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1096375980
Short name T923
Test name
Test status
Simulation time 51881265 ps
CPU time 1.27 seconds
Started Jun 04 12:23:59 PM PDT 24
Finished Jun 04 12:24:01 PM PDT 24
Peak memory 196256 kb
Host smart-b68b9edc-71f3-434d-857c-12623d5f6b98
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1096375980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1096375980
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1179817534
Short name T879
Test name
Test status
Simulation time 228478356 ps
CPU time 1.11 seconds
Started Jun 04 12:23:17 PM PDT 24
Finished Jun 04 12:23:20 PM PDT 24
Peak memory 197228 kb
Host smart-74e5282e-4b33-489d-8bb9-cf352e524068
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179817534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1179817534
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3013668913
Short name T942
Test name
Test status
Simulation time 495983888 ps
CPU time 1.22 seconds
Started Jun 04 12:23:59 PM PDT 24
Finished Jun 04 12:24:02 PM PDT 24
Peak memory 197796 kb
Host smart-6df0187c-7039-4551-85b4-ab57fe71613c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3013668913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3013668913
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.619469067
Short name T895
Test name
Test status
Simulation time 205322062 ps
CPU time 1.14 seconds
Started Jun 04 12:22:48 PM PDT 24
Finished Jun 04 12:22:50 PM PDT 24
Peak memory 196372 kb
Host smart-ba1664ca-5224-4ed1-b389-5ac2a1626342
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619469067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.619469067
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2399952423
Short name T865
Test name
Test status
Simulation time 79884826 ps
CPU time 1.42 seconds
Started Jun 04 12:22:00 PM PDT 24
Finished Jun 04 12:22:02 PM PDT 24
Peak memory 197172 kb
Host smart-2e1cda72-5e5f-4f20-a12c-9c1c928bc648
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2399952423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2399952423
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2564046938
Short name T856
Test name
Test status
Simulation time 464865438 ps
CPU time 1.21 seconds
Started Jun 04 12:23:31 PM PDT 24
Finished Jun 04 12:23:36 PM PDT 24
Peak memory 195448 kb
Host smart-f25a6ea6-acf7-4837-97d1-6ec985ec7f57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564046938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2564046938
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.773665656
Short name T907
Test name
Test status
Simulation time 53217549 ps
CPU time 1.37 seconds
Started Jun 04 12:23:33 PM PDT 24
Finished Jun 04 12:23:36 PM PDT 24
Peak memory 195632 kb
Host smart-2fb472ac-f5a6-493a-a228-b37543faaa53
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=773665656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.773665656
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3975249008
Short name T939
Test name
Test status
Simulation time 52166826 ps
CPU time 1.03 seconds
Started Jun 04 12:23:59 PM PDT 24
Finished Jun 04 12:24:01 PM PDT 24
Peak memory 196000 kb
Host smart-06f135a0-cd5c-407e-b789-b81dcda2c51b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975249008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3975249008
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.98114297
Short name T941
Test name
Test status
Simulation time 53416510 ps
CPU time 0.83 seconds
Started Jun 04 12:18:44 PM PDT 24
Finished Jun 04 12:18:46 PM PDT 24
Peak memory 196048 kb
Host smart-e67ebaf8-2dc4-4803-a493-9f6e0ed79e0e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=98114297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.98114297
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1291052802
Short name T885
Test name
Test status
Simulation time 193475116 ps
CPU time 1.5 seconds
Started Jun 04 12:18:54 PM PDT 24
Finished Jun 04 12:18:56 PM PDT 24
Peak memory 197272 kb
Host smart-c1287e3a-9819-4d9b-9d97-b4ec27d7c3b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291052802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1291052802
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1262768048
Short name T877
Test name
Test status
Simulation time 88375719 ps
CPU time 1.27 seconds
Started Jun 04 12:23:34 PM PDT 24
Finished Jun 04 12:23:37 PM PDT 24
Peak memory 196828 kb
Host smart-c255933e-eca8-49fc-80a7-2f392bd8635a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1262768048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1262768048
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.382242328
Short name T921
Test name
Test status
Simulation time 85019077 ps
CPU time 1.34 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:23:59 PM PDT 24
Peak memory 197784 kb
Host smart-2d709eaa-ffcd-4c95-aa48-a182ecd9f278
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382242328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.382242328
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2261628848
Short name T851
Test name
Test status
Simulation time 50758273 ps
CPU time 0.92 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:23:29 PM PDT 24
Peak memory 196376 kb
Host smart-7224382b-76b4-4047-a991-c8ada0ad62da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2261628848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2261628848
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3621262369
Short name T930
Test name
Test status
Simulation time 48531564 ps
CPU time 1.43 seconds
Started Jun 04 12:20:05 PM PDT 24
Finished Jun 04 12:20:07 PM PDT 24
Peak memory 198052 kb
Host smart-ce046bad-5815-4ac1-9f0d-101eb5d4288a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621262369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3621262369
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2224940171
Short name T871
Test name
Test status
Simulation time 86146829 ps
CPU time 0.95 seconds
Started Jun 04 12:18:01 PM PDT 24
Finished Jun 04 12:18:02 PM PDT 24
Peak memory 195552 kb
Host smart-c9b0efba-214e-4489-a3bf-aaa7514c1e0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2224940171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2224940171
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2269505231
Short name T914
Test name
Test status
Simulation time 102867879 ps
CPU time 1.15 seconds
Started Jun 04 12:23:45 PM PDT 24
Finished Jun 04 12:23:48 PM PDT 24
Peak memory 195732 kb
Host smart-6958e2a6-b6e1-434f-a1dc-68f216a37012
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269505231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2269505231
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2155607421
Short name T915
Test name
Test status
Simulation time 41818771 ps
CPU time 1.19 seconds
Started Jun 04 12:19:43 PM PDT 24
Finished Jun 04 12:19:45 PM PDT 24
Peak memory 195112 kb
Host smart-e5498121-7cc5-4ceb-8780-c612f444ded3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2155607421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2155607421
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.71348676
Short name T924
Test name
Test status
Simulation time 62929156 ps
CPU time 1.16 seconds
Started Jun 04 12:20:21 PM PDT 24
Finished Jun 04 12:20:22 PM PDT 24
Peak memory 195640 kb
Host smart-27ccd0cb-38e4-4105-b2ad-8be020e9d2e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71348676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.71348676
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3830508009
Short name T910
Test name
Test status
Simulation time 43120041 ps
CPU time 0.77 seconds
Started Jun 04 12:23:44 PM PDT 24
Finished Jun 04 12:23:46 PM PDT 24
Peak memory 195108 kb
Host smart-90139f8e-228f-4e8b-84ca-b2fcdb5537d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3830508009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3830508009
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2496660314
Short name T867
Test name
Test status
Simulation time 86615304 ps
CPU time 1.02 seconds
Started Jun 04 12:18:52 PM PDT 24
Finished Jun 04 12:18:54 PM PDT 24
Peak memory 195568 kb
Host smart-6f56f7ad-47dd-4d39-b8d0-e78a4b4b947c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496660314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2496660314
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1783662872
Short name T908
Test name
Test status
Simulation time 82038866 ps
CPU time 1.45 seconds
Started Jun 04 12:23:55 PM PDT 24
Finished Jun 04 12:23:59 PM PDT 24
Peak memory 197796 kb
Host smart-8905ccf5-3c2f-4b32-8d47-959c8417d44a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1783662872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1783662872
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.421260159
Short name T920
Test name
Test status
Simulation time 199182272 ps
CPU time 1.26 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:23:10 PM PDT 24
Peak memory 197852 kb
Host smart-56c0a01d-8a65-4436-bfa7-173ec937020e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421260159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.421260159
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2944303927
Short name T902
Test name
Test status
Simulation time 42114776 ps
CPU time 1.18 seconds
Started Jun 04 12:24:04 PM PDT 24
Finished Jun 04 12:24:07 PM PDT 24
Peak memory 196492 kb
Host smart-3352662f-fd87-4556-8a2a-431a8e1775ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2944303927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2944303927
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2315629138
Short name T925
Test name
Test status
Simulation time 21768261 ps
CPU time 0.81 seconds
Started Jun 04 12:23:54 PM PDT 24
Finished Jun 04 12:23:55 PM PDT 24
Peak memory 193368 kb
Host smart-f09fa2ec-c049-41e2-bda4-5cde248ac080
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315629138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2315629138
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1982690139
Short name T883
Test name
Test status
Simulation time 192379521 ps
CPU time 0.88 seconds
Started Jun 04 12:20:39 PM PDT 24
Finished Jun 04 12:20:41 PM PDT 24
Peak memory 195496 kb
Host smart-d585be97-7e2c-4a94-bdc2-6c1004a8727b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1982690139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1982690139
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1705392266
Short name T876
Test name
Test status
Simulation time 66531363 ps
CPU time 1.03 seconds
Started Jun 04 12:22:15 PM PDT 24
Finished Jun 04 12:22:17 PM PDT 24
Peak memory 195832 kb
Host smart-f00688d5-d851-4558-b552-a807023a6f3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705392266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1705392266
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3676487958
Short name T855
Test name
Test status
Simulation time 80807470 ps
CPU time 1.08 seconds
Started Jun 04 12:23:42 PM PDT 24
Finished Jun 04 12:23:45 PM PDT 24
Peak memory 195176 kb
Host smart-0655dbf5-e855-4fe3-80bf-c70131099dbf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3676487958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3676487958
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1514800870
Short name T850
Test name
Test status
Simulation time 412788800 ps
CPU time 1.27 seconds
Started Jun 04 12:23:13 PM PDT 24
Finished Jun 04 12:23:16 PM PDT 24
Peak memory 196524 kb
Host smart-63bd7e79-eead-474e-b8b4-a71462011741
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514800870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1514800870
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1296148043
Short name T897
Test name
Test status
Simulation time 33273264 ps
CPU time 0.82 seconds
Started Jun 04 12:19:26 PM PDT 24
Finished Jun 04 12:19:27 PM PDT 24
Peak memory 196148 kb
Host smart-0da94e8c-f340-4265-a5fd-55ac0eda90c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1296148043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1296148043
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1213744827
Short name T862
Test name
Test status
Simulation time 188647076 ps
CPU time 1.25 seconds
Started Jun 04 12:23:05 PM PDT 24
Finished Jun 04 12:23:08 PM PDT 24
Peak memory 196764 kb
Host smart-53749795-b9e6-4ef1-9f77-68370552240c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213744827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1213744827
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3008275000
Short name T934
Test name
Test status
Simulation time 71115231 ps
CPU time 0.78 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:31 PM PDT 24
Peak memory 196152 kb
Host smart-9d855a37-dcf4-46da-8d7c-2304dc959cdc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3008275000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3008275000
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2224862794
Short name T857
Test name
Test status
Simulation time 47729974 ps
CPU time 0.91 seconds
Started Jun 04 12:23:05 PM PDT 24
Finished Jun 04 12:23:08 PM PDT 24
Peak memory 196528 kb
Host smart-75ec2a32-b67e-4376-bdc1-ce6a893e3208
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224862794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2224862794
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2526245169
Short name T866
Test name
Test status
Simulation time 415581592 ps
CPU time 1.57 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:36 PM PDT 24
Peak memory 196540 kb
Host smart-15e07ebf-fdf7-4a6b-99c3-f732d31348a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2526245169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2526245169
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3378942207
Short name T859
Test name
Test status
Simulation time 230815873 ps
CPU time 1.21 seconds
Started Jun 04 12:23:05 PM PDT 24
Finished Jun 04 12:23:08 PM PDT 24
Peak memory 196140 kb
Host smart-83557085-0fdb-4b83-a1cf-d59ad3b54afe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378942207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3378942207
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3649138387
Short name T888
Test name
Test status
Simulation time 39196886 ps
CPU time 0.83 seconds
Started Jun 04 12:23:06 PM PDT 24
Finished Jun 04 12:23:09 PM PDT 24
Peak memory 195224 kb
Host smart-09d0b73a-a3af-4d07-bfd1-cccd43bd01fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3649138387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3649138387
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1917371172
Short name T929
Test name
Test status
Simulation time 203415771 ps
CPU time 0.99 seconds
Started Jun 04 12:23:13 PM PDT 24
Finished Jun 04 12:23:16 PM PDT 24
Peak memory 194644 kb
Host smart-3731e9a6-d246-4686-b65c-909c12bf6562
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917371172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1917371172
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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