Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3814367	1			T21	47		T22	43		T23	1
all_pins[1]	3814367	1			T21	47		T22	43		T23	1
all_pins[2]	3814367	1			T21	47		T22	43		T23	1
all_pins[3]	3814367	1			T21	47		T22	43		T23	1
all_pins[4]	3814367	1			T21	47		T22	43		T23	1
all_pins[5]	3814367	1			T21	47		T22	43		T23	1
all_pins[6]	3814367	1			T21	47		T22	43		T23	1
all_pins[7]	3814367	1			T21	47		T22	43		T23	1
all_pins[8]	3814367	1			T21	47		T22	43		T23	1
all_pins[9]	3814367	1			T21	47		T22	43		T23	1
all_pins[10]	3814367	1			T21	47		T22	43		T23	1
all_pins[11]	3814367	1			T21	47		T22	43		T23	1
all_pins[12]	3814367	1			T21	47		T22	43		T23	1
all_pins[13]	3814367	1			T21	47		T22	43		T23	1
all_pins[14]	3814367	1			T21	47		T22	43		T23	1
all_pins[15]	3814367	1			T21	47		T22	43		T23	1
all_pins[16]	3814367	1			T21	47		T22	43		T23	1
all_pins[17]	3814367	1			T21	47		T22	43		T23	1
all_pins[18]	3814367	1			T21	47		T22	43		T23	1
all_pins[19]	3814367	1			T21	47		T22	43		T23	1
all_pins[20]	3814367	1			T21	47		T22	43		T23	1
all_pins[21]	3814367	1			T21	47		T22	43		T23	1
all_pins[22]	3814367	1			T21	47		T22	43		T23	1
all_pins[23]	3814367	1			T21	47		T22	43		T23	1
all_pins[24]	3814367	1			T21	47		T22	43		T23	1
all_pins[25]	3814367	1			T21	47		T22	43		T23	1
all_pins[26]	3814367	1			T21	47		T22	43		T23	1
all_pins[27]	3814367	1			T21	47		T22	43		T23	1
all_pins[28]	3814367	1			T21	47		T22	43		T23	1
all_pins[29]	3814367	1			T21	47		T22	43		T23	1
all_pins[30]	3814367	1			T21	47		T22	43		T23	1
all_pins[31]	3814367	1			T21	47		T22	43		T23	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	75822730	1			T21	985		T22	697		T23	32
values[0x1]	46237014	1			T21	519		T22	679		T24	809
transitions[0x0=>0x1]	27701022	1			T21	333		T22	329		T24	402
transitions[0x1=>0x0]	27700870	1			T21	333		T22	328		T24	401

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2373919	1			T21	34		T22	23		T23	1
all_pins[0]	values[0x1]	1440448	1			T21	13		T22	20		T24	33
all_pins[0]	transitions[0x0=>0x1]	892444	1			T21	13		T22	3		T24	25
all_pins[0]	transitions[0x1=>0x0]	895058	1			T21	3		T22	17		T24	9
all_pins[1]	values[0x0]	2370161	1			T21	39		T22	25		T23	1
all_pins[1]	values[0x1]	1444206	1			T21	8		T22	18		T24	32
all_pins[1]	transitions[0x0=>0x1]	864884	1			T21	6		T22	12		T24	10
all_pins[1]	transitions[0x1=>0x0]	861126	1			T21	11		T22	14		T24	11
all_pins[2]	values[0x0]	2373541	1			T21	35		T22	30		T23	1
all_pins[2]	values[0x1]	1440826	1			T21	12		T22	13		T24	35
all_pins[2]	transitions[0x0=>0x1]	861862	1			T21	11		T22	7		T24	12
all_pins[2]	transitions[0x1=>0x0]	865242	1			T21	7		T22	12		T24	9
all_pins[3]	values[0x0]	2370143	1			T21	23		T22	20		T23	1
all_pins[3]	values[0x1]	1444224	1			T21	24		T22	23		T24	30
all_pins[3]	transitions[0x0=>0x1]	867208	1			T21	23		T22	17		T24	6
all_pins[3]	transitions[0x1=>0x0]	863810	1			T21	11		T22	7		T24	11
all_pins[4]	values[0x0]	2371294	1			T21	36		T22	26		T23	1
all_pins[4]	values[0x1]	1443073	1			T21	11		T22	17		T24	21
all_pins[4]	transitions[0x0=>0x1]	863520	1			T21	3		T22	10		T24	10
all_pins[4]	transitions[0x1=>0x0]	864671	1			T21	16		T22	16		T24	19
all_pins[5]	values[0x0]	2372799	1			T21	28		T22	16		T23	1
all_pins[5]	values[0x1]	1441568	1			T21	19		T22	27		T24	17
all_pins[5]	transitions[0x0=>0x1]	861745	1			T21	9		T22	16		T24	8
all_pins[5]	transitions[0x1=>0x0]	863250	1			T21	1		T22	6		T24	12
all_pins[6]	values[0x0]	2372298	1			T21	27		T22	23		T23	1
all_pins[6]	values[0x1]	1442069	1			T21	20		T22	20		T24	20
all_pins[6]	transitions[0x0=>0x1]	864242	1			T21	12		T22	3		T24	11
all_pins[6]	transitions[0x1=>0x0]	863741	1			T21	11		T22	10		T24	8
all_pins[7]	values[0x0]	2365739	1			T21	42		T22	23		T23	1
all_pins[7]	values[0x1]	1448628	1			T21	5		T22	20		T24	27
all_pins[7]	transitions[0x0=>0x1]	868392	1			T21	1		T22	11		T24	18
all_pins[7]	transitions[0x1=>0x0]	861833	1			T21	16		T22	11		T24	11
all_pins[8]	values[0x0]	2370962	1			T21	35		T22	15		T23	1
all_pins[8]	values[0x1]	1443405	1			T21	12		T22	28		T24	18
all_pins[8]	transitions[0x0=>0x1]	863077	1			T21	9		T22	17		T24	9
all_pins[8]	transitions[0x1=>0x0]	868300	1			T21	2		T22	9		T24	18
all_pins[9]	values[0x0]	2365035	1			T21	30		T22	22		T23	1
all_pins[9]	values[0x1]	1449332	1			T21	17		T22	21		T24	30
all_pins[9]	transitions[0x0=>0x1]	866110	1			T21	15		T22	5		T24	20
all_pins[9]	transitions[0x1=>0x0]	860183	1			T21	10		T22	12		T24	8
all_pins[10]	values[0x0]	2376310	1			T21	23		T22	23		T23	1
all_pins[10]	values[0x1]	1438057	1			T21	24		T22	20		T24	21
all_pins[10]	transitions[0x0=>0x1]	860386	1			T21	18		T22	11		T24	6
all_pins[10]	transitions[0x1=>0x0]	871661	1			T21	11		T22	12		T24	15
all_pins[11]	values[0x0]	2364192	1			T21	30		T22	22		T23	1
all_pins[11]	values[0x1]	1450175	1			T21	17		T22	21		T24	20
all_pins[11]	transitions[0x0=>0x1]	872052	1			T21	14		T22	7		T24	8
all_pins[11]	transitions[0x1=>0x0]	859934	1			T21	21		T22	6		T24	9
all_pins[12]	values[0x0]	2360563	1			T21	27		T22	18		T23	1
all_pins[12]	values[0x1]	1453804	1			T21	20		T22	25		T24	27
all_pins[12]	transitions[0x0=>0x1]	870214	1			T21	20		T22	12		T24	17
all_pins[12]	transitions[0x1=>0x0]	866585	1			T21	17		T22	8		T24	10
all_pins[13]	values[0x0]	2366200	1			T21	39		T22	28		T23	1
all_pins[13]	values[0x1]	1448167	1			T21	8		T22	15		T24	23
all_pins[13]	transitions[0x0=>0x1]	863654	1			T21	8		T22	7		T24	9
all_pins[13]	transitions[0x1=>0x0]	869291	1			T21	20		T22	17		T24	13
all_pins[14]	values[0x0]	2363649	1			T21	31		T22	26		T23	1
all_pins[14]	values[0x1]	1450718	1			T21	16		T22	17		T24	23
all_pins[14]	transitions[0x0=>0x1]	866297	1			T21	14		T22	11		T24	10
all_pins[14]	transitions[0x1=>0x0]	863746	1			T21	6		T22	9		T24	10
all_pins[15]	values[0x0]	2375999	1			T21	24		T22	23		T23	1
all_pins[15]	values[0x1]	1438368	1			T21	23		T22	20		T24	25
all_pins[15]	transitions[0x0=>0x1]	858205	1			T21	15		T22	13		T24	13
all_pins[15]	transitions[0x1=>0x0]	870555	1			T21	8		T22	10		T24	11
all_pins[16]	values[0x0]	2369664	1			T21	34		T22	19		T23	1
all_pins[16]	values[0x1]	1444703	1			T21	13		T22	24		T24	19
all_pins[16]	transitions[0x0=>0x1]	865599	1			T21	1		T22	13		T24	8
all_pins[16]	transitions[0x1=>0x0]	859264	1			T21	11		T22	9		T24	14
all_pins[17]	values[0x0]	2370906	1			T21	35		T22	20		T23	1
all_pins[17]	values[0x1]	1443461	1			T21	12		T22	23		T24	29
all_pins[17]	transitions[0x0=>0x1]	865418	1			T21	8		T22	6		T24	22
all_pins[17]	transitions[0x1=>0x0]	866660	1			T21	9		T22	7		T24	12
all_pins[18]	values[0x0]	2372572	1			T21	35		T22	21		T23	1
all_pins[18]	values[0x1]	1441795	1			T21	12		T22	22		T24	19
all_pins[18]	transitions[0x0=>0x1]	863808	1			T21	8		T22	12		T24	9
all_pins[18]	transitions[0x1=>0x0]	865474	1			T21	8		T22	13		T24	19
all_pins[19]	values[0x0]	2369824	1			T21	29		T22	20		T23	1
all_pins[19]	values[0x1]	1444543	1			T21	18		T22	23		T24	28
all_pins[19]	transitions[0x0=>0x1]	866991	1			T21	9		T22	6		T24	20
all_pins[19]	transitions[0x1=>0x0]	864243	1			T21	3		T22	5		T24	11
all_pins[20]	values[0x0]	2371087	1			T21	17		T22	27		T23	1
all_pins[20]	values[0x1]	1443280	1			T21	30		T22	16		T24	24
all_pins[20]	transitions[0x0=>0x1]	864345	1			T21	16		T22	8		T24	14
all_pins[20]	transitions[0x1=>0x0]	865608	1			T21	4		T22	15		T24	18
all_pins[21]	values[0x0]	2368527	1			T21	29		T22	19		T23	1
all_pins[21]	values[0x1]	1445840	1			T21	18		T22	24		T24	30
all_pins[21]	transitions[0x0=>0x1]	866732	1			T22	14		T24	20		T25	6
all_pins[21]	transitions[0x1=>0x0]	864172	1			T21	12		T22	6		T24	14
all_pins[22]	values[0x0]	2374259	1			T21	33		T22	28		T23	1
all_pins[22]	values[0x1]	1440108	1			T21	14		T22	15		T24	34
all_pins[22]	transitions[0x0=>0x1]	861997	1			T21	14		T22	8		T24	11
all_pins[22]	transitions[0x1=>0x0]	867729	1			T21	18		T22	17		T24	7
all_pins[23]	values[0x0]	2365046	1			T21	29		T22	19		T23	1
all_pins[23]	values[0x1]	1449321	1			T21	18		T22	24		T24	29
all_pins[23]	transitions[0x0=>0x1]	870297	1			T21	12		T22	14		T24	11
all_pins[23]	transitions[0x1=>0x0]	861084	1			T21	8		T22	5		T24	16
all_pins[24]	values[0x0]	2366327	1			T21	31		T22	21		T23	1
all_pins[24]	values[0x1]	1448040	1			T21	16		T22	22		T24	26
all_pins[24]	transitions[0x0=>0x1]	864029	1			T21	6		T22	9		T24	11
all_pins[24]	transitions[0x1=>0x0]	865310	1			T21	8		T22	11		T24	14
all_pins[25]	values[0x0]	2363359	1			T21	29		T22	21		T23	1
all_pins[25]	values[0x1]	1451008	1			T21	18		T22	22		T24	25
all_pins[25]	transitions[0x0=>0x1]	869258	1			T21	10		T22	11		T24	15
all_pins[25]	transitions[0x1=>0x0]	866290	1			T21	8		T22	11		T24	16
all_pins[26]	values[0x0]	2368954	1			T21	16		T22	21		T23	1
all_pins[26]	values[0x1]	1445413	1			T21	31		T22	22		T24	31
all_pins[26]	transitions[0x0=>0x1]	861470	1			T21	20		T22	11		T24	19
all_pins[26]	transitions[0x1=>0x0]	867065	1			T21	7		T22	11		T24	13
all_pins[27]	values[0x0]	2366288	1			T21	37		T22	15		T23	1
all_pins[27]	values[0x1]	1448079	1			T21	10		T22	28		T24	29
all_pins[27]	transitions[0x0=>0x1]	865966	1			T21	1		T22	12		T24	10
all_pins[27]	transitions[0x1=>0x0]	863300	1			T21	22		T22	6		T24	12
all_pins[28]	values[0x0]	2371360	1			T21	36		T22	24		T23	1
all_pins[28]	values[0x1]	1443007	1			T21	11		T22	19		T24	25
all_pins[28]	transitions[0x0=>0x1]	859319	1			T21	7		T22	9		T24	12
all_pins[28]	transitions[0x1=>0x0]	864391	1			T21	6		T22	18		T24	16
all_pins[29]	values[0x0]	2371586	1			T21	21		T22	26		T23	1
all_pins[29]	values[0x1]	1442781	1			T21	26		T22	17		T24	21
all_pins[29]	transitions[0x0=>0x1]	862527	1			T21	22		T22	8		T24	8
all_pins[29]	transitions[0x1=>0x0]	862753	1			T21	7		T22	10		T24	12
all_pins[30]	values[0x0]	2369014	1			T21	27		T22	25		T23	1
all_pins[30]	values[0x1]	1445353	1			T21	20		T22	18		T24	20
all_pins[30]	transitions[0x0=>0x1]	865655	1			T21	8		T22	7		T24	9
all_pins[30]	transitions[0x1=>0x0]	863083	1			T21	14		T22	6		T24	10
all_pins[31]	values[0x0]	2371153	1			T21	44		T22	8		T23	1
all_pins[31]	values[0x1]	1443214	1			T21	3		T22	35		T24	18
all_pins[31]	transitions[0x0=>0x1]	863319	1			T22	19		T24	11		T25	4
all_pins[31]	transitions[0x1=>0x0]	865458	1			T21	17		T22	2		T24	13