Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[1]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[2]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[3]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[4]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[5]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[6]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[7]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[8]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[9]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[10]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[11]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[12]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[13]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[14]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[15]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[16]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[17]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[18]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[19]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[20]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[21]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[22]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[23]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[24]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[25]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[26]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[27]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[28]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[29]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[30]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[31]	12671345	1			T21	25		T22	17009		T23	262

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242001094

1

T21

355

T22

270933

T23

6567

auto[1]

163481946

1

T21

445

T22

273355

T23

1817

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

326547451

1

T21

800

T22

544288

T23

7801

auto[1]

78935589

1

T23

583

T26

5774

T27

5267

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

303072769

1

T21

800

T22

544288

T23

4398

auto[1]

102410271

1

T23

3986

T26

5565

T27

9335

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4737379	1			T21	11		T22	8349		T23	82
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3500279	1			T21	14		T22	8660		T23	26
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1240242	1			T23	4		T26	86		T27	82
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1581229	1			T23	109		T26	86		T27	181
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	382376	1			T23	27		T27	28		T29	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1229840	1			T23	14		T26	66		T27	114
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4727690	1			T21	13		T22	6688		T23	97
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3499004	1			T21	12		T22	10321		T23	30
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1245330	1			T23	14		T26	96		T27	44
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1587433	1			T23	95		T26	94		T27	206
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	384150	1			T23	16		T27	29		T29	5
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1227738	1			T23	10		T26	85		T27	66
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4719261	1			T21	12		T22	7431		T23	93
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3505845	1			T21	13		T22	9578		T23	28
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1236969	1			T23	7		T26	95		T27	81
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1593818	1			T23	101		T26	66		T27	216
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	383632	1			T23	24		T27	17		T29	11
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1231820	1			T23	9		T26	98		T27	98
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4731000	1			T21	15		T22	8633		T23	60
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3497799	1			T21	10		T22	8376		T23	18
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1239549	1			T23	9		T26	92		T27	74
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1588808	1			T23	132		T26	88		T27	147
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	382825	1			T23	29		T27	14		T29	17
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1231364	1			T23	14		T26	80		T27	67
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4734848	1			T21	12		T22	7920		T23	88
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3489206	1			T21	13		T22	9089		T23	17
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1239445	1			T23	6		T26	83		T27	81
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1591493	1			T23	112		T26	98		T27	178
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	385116	1			T23	20		T27	25		T29	16
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1231237	1			T23	19		T26	74		T27	88
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4731753	1			T21	8		T22	8271		T23	105
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3491276	1			T21	17		T22	8738		T23	27
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1238669	1			T23	16		T26	82		T27	78
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1592241	1			T23	78		T26	82		T27	202
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	386644	1			T23	25		T27	22		T29	20
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1230762	1			T23	11		T26	78		T27	60
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4730354	1			T21	8		T22	7405		T23	96
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3492712	1			T21	17		T22	9604		T23	32
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1238763	1			T23	14		T26	92		T27	85
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1586261	1			T23	103		T26	86		T27	185
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	384609	1			T23	13		T27	32		T29	5
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1238646	1			T23	4		T26	101		T27	106
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4720142	1			T21	15		T22	8475		T23	123
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3510240	1			T21	10		T22	8534		T23	26
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1243558	1			T23	11		T26	96		T27	103
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1584815	1			T23	80		T26	60		T27	228
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	381743	1			T23	20		T27	26		T29	5
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1230847	1			T23	2		T26	100		T27	75
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4735931	1			T21	10		T22	9013		T23	111
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3495120	1			T21	15		T22	7996		T23	21
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1240325	1			T23	12		T26	75		T27	55
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1583084	1			T23	93		T26	106		T27	219
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	385305	1			T23	20		T27	21		T29	5
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1231580	1			T23	5		T26	98		T27	54
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4739764	1			T21	12		T22	8276		T23	107
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3489396	1			T21	13		T22	8733		T23	34
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1241834	1			T23	11		T26	115		T27	89
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1586263	1			T23	90		T26	78		T27	185
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	385241	1			T23	14		T27	32		T29	10
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1228847	1			T23	6		T26	94		T27	72
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4724190	1			T21	10		T22	8393		T23	121
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3498708	1			T21	15		T22	8616		T23	25
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1239672	1			T23	9		T26	73		T27	74
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1592845	1			T23	76		T26	100		T27	162
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	385274	1			T23	23		T27	17		T29	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1230656	1			T23	8		T26	88		T27	97
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4734966	1			T21	11		T22	8111		T23	134
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3499158	1			T21	14		T22	8898		T23	38
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1245731	1			T23	10		T26	96		T27	67
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1579438	1			T23	53		T26	86		T27	189
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	382484	1			T23	23		T27	46		T29	6
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1229568	1			T23	4		T26	85		T27	90
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4742686	1			T21	15		T22	9037		T23	135
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3494349	1			T21	10		T22	7972		T23	18
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1242308	1			T23	6		T26	74		T27	37
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1579520	1			T23	72		T26	78		T27	217
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	381777	1			T23	25		T27	34		T29	16
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1230705	1			T23	6		T26	106		T27	122
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4743690	1			T21	8		T22	9875		T23	68
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3488483	1			T21	17		T22	7134		T23	23
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1245713	1			T23	7		T26	112		T27	83
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1583207	1			T23	119		T26	74		T27	194
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	384732	1			T23	29		T27	33		T29	5
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1225520	1			T23	16		T26	85		T27	103
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4728277	1			T21	17		T22	8669		T23	73
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3499404	1			T21	8		T22	8340		T23	19
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1237440	1			T26	61		T27	77		T29	219
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1587455	1			T23	129		T26	92		T27	164
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	383425	1			T23	29		T27	22		T29	8
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1235344	1			T23	12		T26	84		T27	88
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4738756	1			T21	12		T22	8258		T23	124
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3488483	1			T21	13		T22	8751		T23	34
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1241498	1			T23	16		T26	104		T27	83
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1585710	1			T23	62		T26	90		T27	268
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	381996	1			T23	18		T27	34		T29	6
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1234902	1			T23	8		T26	101		T27	64
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4741421	1			T21	9		T22	8191		T23	72
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3494284	1			T21	16		T22	8818		T23	14
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1234871	1			T23	8		T26	122		T27	75
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1590167	1			T23	137		T26	50		T27	129
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	384069	1			T23	26		T27	22		T29	2
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1226533	1			T23	5		T26	110		T27	67
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4742456	1			T21	14		T22	8600		T23	62
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3497853	1			T21	11		T22	8409		T23	19
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1235705	1			T23	4		T26	79		T27	122
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1587627	1			T23	134		T26	110		T27	147
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	383438	1			T23	27		T27	17		T29	15
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1224266	1			T23	16		T26	82		T27	85
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4731264	1			T21	8		T22	8209		T23	68
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3496387	1			T21	17		T22	8800		T23	15
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1236617	1			T23	2		T26	102		T27	92
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1594703	1			T23	145		T26	74		T27	209
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	384874	1			T23	26		T27	26		T29	6
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1227500	1			T23	6		T26	82		T27	78
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4746199	1			T21	7		T22	8976		T23	121
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3493019	1			T21	18		T22	8033		T23	37
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1234661	1			T23	8		T26	70		T27	93
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1587220	1			T23	81		T26	82		T27	134
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	384025	1			T23	11		T27	10		T29	22
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1226221	1			T23	4		T26	78		T27	55
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4738276	1			T21	8		T22	7964		T23	170
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3503742	1			T21	17		T22	9045		T23	32
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1232999	1			T23	8		T26	92		T27	112
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1590570	1			T23	45		T26	76		T27	173
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	384329	1			T23	7		T27	19		T29	9
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1221429	1			T26	104		T27	57		T29	193
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4735802	1			T21	10		T22	8996		T23	92
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3502599	1			T21	15		T22	8013		T23	30
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1240337	1			T23	16		T26	96		T27	75
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1582329	1			T23	96		T26	78		T27	215
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	382102	1			T23	24		T27	27		T29	9
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1228176	1			T23	4		T26	113		T27	120
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4735689	1			T21	13		T22	8652		T23	157
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3495736	1			T21	12		T22	8357		T23	31
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1233761	1			T23	7		T26	78		T27	74
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1591677	1			T23	44		T26	108		T27	193
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	386023	1			T23	9		T27	49		T29	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1228459	1			T23	14		T26	75		T27	97
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4753202	1			T21	11		T22	9233		T23	176
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3490915	1			T21	14		T22	7776		T23	43
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1236230	1			T23	14		T26	102		T27	97
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1589313	1			T23	18		T26	101		T27	153
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	381636	1			T23	2		T27	34		T29	4
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1220049	1			T23	9		T26	74		T27	89
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4737675	1			T21	13		T22	8223		T23	84
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3494557	1			T21	12		T22	8786		T23	34
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1234524	1			T23	13		T26	108		T27	97
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1596861	1			T23	107		T26	82		T27	207
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	382803	1			T23	18		T27	24		T29	15
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1224925	1			T23	6		T26	77		T27	97
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4723435	1			T21	14		T22	8324		T23	54
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3512858	1			T21	11		T22	8685		T23	22
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1243047	1			T23	5		T26	91		T27	70
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1587486	1			T23	138		T26	94		T27	145
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	383384	1			T23	28		T27	10		T29	8
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1221135	1			T23	15		T26	70		T27	71
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4738349	1			T21	5		T22	8674		T23	83
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3496926	1			T21	20		T22	8335		T23	35
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1232996	1			T23	16		T26	77		T27	59
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1588370	1			T23	93		T26	72		T27	217
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	384440	1			T23	27		T27	8		T29	8
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1230264	1			T23	8		T26	120		T27	42
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4743861	1			T21	10		T22	8894		T23	53
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3491466	1			T21	15		T22	8115		T23	23
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1232274	1			T23	6		T26	96		T27	118
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1594128	1			T23	139		T26	90		T27	123
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	383657	1			T23	30		T27	11		T29	11
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1225959	1			T23	11		T26	105		T27	88
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4745269	1			T21	8		T22	9116		T23	93
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3489240	1			T21	17		T22	7893		T23	18
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1234030	1			T23	4		T26	97		T27	113
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1591981	1			T23	102		T26	68		T27	146
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	385891	1			T23	30		T27	13		T29	10
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1224934	1			T23	15		T26	108		T27	85
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4742034	1			T21	7		T22	9109		T23	70
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3497896	1			T21	18		T22	7900		T23	20
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1235831	1			T23	6		T26	83		T27	61
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1588701	1			T23	130		T26	82		T27	212
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	383603	1			T23	25		T27	28		T29	11
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1223280	1			T23	11		T26	82		T27	134
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4723120	1			T21	15		T22	7495		T23	89
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3506984	1			T21	10		T22	9514		T23	20
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1237058	1			T23	14		T26	98		T27	47
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1595149	1			T23	99		T26	96		T27	202
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	383771	1			T23	31		T27	20		T29	12
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1225263	1			T23	9		T26	87		T27	71
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4744159	1			T21	14		T22	9473		T23	176
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3494120	1			T21	11		T22	7536		T23	50
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1239840	1			T23	19		T26	89		T27	113
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1586467	1			T23	16		T26	76		T27	155
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	380766	1			T23	1		T27	28		T29	16
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1225993	1			T26	72		T27	56		T29	147

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal