Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[1]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[2]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[3]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[4]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[5]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[6]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[7]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[8]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[9]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[10]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[11]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[12]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[13]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[14]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[15]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[16]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[17]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[18]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[19]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[20]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[21]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[22]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[23]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[24]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[25]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[26]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[27]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[28]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[29]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[30]	12671345	1			T21	25		T22	17009		T23	262
bins_for_gpio_bits[31]	12671345	1			T21	25		T22	17009		T23	262

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242001094

1

T21

355

T22

270933

T23

6567

auto[1]

163481946

1

T21

445

T22

273355

T23

1817

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241993414

1

T21

355

T22

270933

T23

6567

auto[1]

163489626

1

T21

445

T22

273355

T23

1817

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7338180	1			T21	11		T22	8349		T23	190
bins_for_gpio_bits[0]	auto[0]	auto[1]	220457	1			T23	5		T26	21		T27	18
bins_for_gpio_bits[0]	auto[1]	auto[0]	220670	1			T23	5		T26	21		T27	19
bins_for_gpio_bits[0]	auto[1]	auto[1]	4892038	1			T21	14		T22	8660		T23	62
bins_for_gpio_bits[1]	auto[0]	auto[0]	7339788	1			T21	13		T22	6688		T23	202
bins_for_gpio_bits[1]	auto[0]	auto[1]	220405	1			T23	4		T26	18		T27	14
bins_for_gpio_bits[1]	auto[1]	auto[0]	220665	1			T23	4		T26	19		T27	14
bins_for_gpio_bits[1]	auto[1]	auto[1]	4890487	1			T21	12		T22	10321		T23	52
bins_for_gpio_bits[2]	auto[0]	auto[0]	7329373	1			T21	12		T22	7431		T23	198
bins_for_gpio_bits[2]	auto[0]	auto[1]	220435	1			T23	3		T26	20		T27	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	220675	1			T23	3		T26	20		T27	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	4900862	1			T21	13		T22	9578		T23	58
bins_for_gpio_bits[3]	auto[0]	auto[0]	7338667	1			T21	15		T22	8633		T23	197
bins_for_gpio_bits[3]	auto[0]	auto[1]	220452	1			T23	4		T26	16		T27	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	220690	1			T23	4		T26	16		T27	11
bins_for_gpio_bits[3]	auto[1]	auto[1]	4891536	1			T21	10		T22	8376		T23	57
bins_for_gpio_bits[4]	auto[0]	auto[0]	7344783	1			T21	12		T22	7920		T23	199
bins_for_gpio_bits[4]	auto[0]	auto[1]	220764	1			T23	7		T26	21		T27	13
bins_for_gpio_bits[4]	auto[1]	auto[0]	221003	1			T23	7		T26	21		T27	14
bins_for_gpio_bits[4]	auto[1]	auto[1]	4884795	1			T21	13		T22	9089		T23	49
bins_for_gpio_bits[5]	auto[0]	auto[0]	7341857	1			T21	8		T22	8271		T23	196
bins_for_gpio_bits[5]	auto[0]	auto[1]	220544	1			T23	3		T26	19		T27	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	220806	1			T23	3		T26	19		T27	11
bins_for_gpio_bits[5]	auto[1]	auto[1]	4888138	1			T21	17		T22	8738		T23	60
bins_for_gpio_bits[6]	auto[0]	auto[0]	7334625	1			T21	8		T22	7405		T23	211
bins_for_gpio_bits[6]	auto[0]	auto[1]	220520	1			T23	2		T26	19		T27	17
bins_for_gpio_bits[6]	auto[1]	auto[0]	220753	1			T23	2		T26	20		T27	17
bins_for_gpio_bits[6]	auto[1]	auto[1]	4895447	1			T21	17		T22	9604		T23	47
bins_for_gpio_bits[7]	auto[0]	auto[0]	7327645	1			T21	15		T22	8475		T23	213
bins_for_gpio_bits[7]	auto[0]	auto[1]	220648	1			T23	1		T26	25		T27	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	220870	1			T23	1		T26	25		T27	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	4902182	1			T21	10		T22	8534		T23	47
bins_for_gpio_bits[8]	auto[0]	auto[0]	7338815	1			T21	10		T22	9013		T23	214
bins_for_gpio_bits[8]	auto[0]	auto[1]	220310	1			T23	2		T26	26		T27	8
bins_for_gpio_bits[8]	auto[1]	auto[0]	220525	1			T23	2		T26	26		T27	8
bins_for_gpio_bits[8]	auto[1]	auto[1]	4891695	1			T21	15		T22	7996		T23	44
bins_for_gpio_bits[9]	auto[0]	auto[0]	7347588	1			T21	12		T22	8276		T23	206
bins_for_gpio_bits[9]	auto[0]	auto[1]	220015	1			T23	2		T26	24		T27	11
bins_for_gpio_bits[9]	auto[1]	auto[0]	220273	1			T23	2		T26	24		T27	11
bins_for_gpio_bits[9]	auto[1]	auto[1]	4883469	1			T21	13		T22	8733		T23	52
bins_for_gpio_bits[10]	auto[0]	auto[0]	7335804	1			T21	10		T22	8393		T23	202
bins_for_gpio_bits[10]	auto[0]	auto[1]	220646	1			T23	4		T26	21		T27	14
bins_for_gpio_bits[10]	auto[1]	auto[0]	220903	1			T23	4		T26	21		T27	14
bins_for_gpio_bits[10]	auto[1]	auto[1]	4893992	1			T21	15		T22	8616		T23	52
bins_for_gpio_bits[11]	auto[0]	auto[0]	7339445	1			T21	11		T22	8111		T23	195
bins_for_gpio_bits[11]	auto[0]	auto[1]	220434	1			T23	2		T26	24		T27	18
bins_for_gpio_bits[11]	auto[1]	auto[0]	220690	1			T23	2		T26	25		T27	18
bins_for_gpio_bits[11]	auto[1]	auto[1]	4890776	1			T21	14		T22	8898		T23	63
bins_for_gpio_bits[12]	auto[0]	auto[0]	7343795	1			T21	15		T22	9037		T23	210
bins_for_gpio_bits[12]	auto[0]	auto[1]	220465	1			T23	3		T26	27		T27	16
bins_for_gpio_bits[12]	auto[1]	auto[0]	220719	1			T23	3		T26	27		T27	17
bins_for_gpio_bits[12]	auto[1]	auto[1]	4886366	1			T21	10		T22	7972		T23	46
bins_for_gpio_bits[13]	auto[0]	auto[0]	7352489	1			T21	8		T22	9875		T23	188
bins_for_gpio_bits[13]	auto[0]	auto[1]	219914	1			T23	6		T26	23		T27	15
bins_for_gpio_bits[13]	auto[1]	auto[0]	220121	1			T23	6		T26	24		T27	15
bins_for_gpio_bits[13]	auto[1]	auto[1]	4878821	1			T21	17		T22	7134		T23	62
bins_for_gpio_bits[14]	auto[0]	auto[0]	7332167	1			T21	17		T22	8669		T23	198
bins_for_gpio_bits[14]	auto[0]	auto[1]	220788	1			T23	4		T26	21		T27	12
bins_for_gpio_bits[14]	auto[1]	auto[0]	221005	1			T23	4		T26	21		T27	13
bins_for_gpio_bits[14]	auto[1]	auto[1]	4897385	1			T21	8		T22	8340		T23	56
bins_for_gpio_bits[15]	auto[0]	auto[0]	7345061	1			T21	12		T22	8258		T23	200
bins_for_gpio_bits[15]	auto[0]	auto[1]	220683	1			T23	2		T26	19		T27	12
bins_for_gpio_bits[15]	auto[1]	auto[0]	220903	1			T23	2		T26	20		T27	12
bins_for_gpio_bits[15]	auto[1]	auto[1]	4884698	1			T21	13		T22	8751		T23	58
bins_for_gpio_bits[16]	auto[0]	auto[0]	7346344	1			T21	9		T22	8191		T23	215
bins_for_gpio_bits[16]	auto[0]	auto[1]	219853	1			T23	2		T26	25		T27	11
bins_for_gpio_bits[16]	auto[1]	auto[0]	220115	1			T23	2		T26	25		T27	12
bins_for_gpio_bits[16]	auto[1]	auto[1]	4885033	1			T21	16		T22	8818		T23	43
bins_for_gpio_bits[17]	auto[0]	auto[0]	7345393	1			T21	14		T22	8600		T23	194
bins_for_gpio_bits[17]	auto[0]	auto[1]	220171	1			T23	6		T26	23		T27	16
bins_for_gpio_bits[17]	auto[1]	auto[0]	220395	1			T23	6		T26	23		T27	16
bins_for_gpio_bits[17]	auto[1]	auto[1]	4885386	1			T21	11		T22	8409		T23	56
bins_for_gpio_bits[18]	auto[0]	auto[0]	7341431	1			T21	8		T22	8209		T23	212
bins_for_gpio_bits[18]	auto[0]	auto[1]	220856	1			T23	3		T26	24		T27	14
bins_for_gpio_bits[18]	auto[1]	auto[0]	221153	1			T23	3		T26	24		T27	14
bins_for_gpio_bits[18]	auto[1]	auto[1]	4887905	1			T21	17		T22	8800		T23	44
bins_for_gpio_bits[19]	auto[0]	auto[0]	7347635	1			T21	7		T22	8976		T23	208
bins_for_gpio_bits[19]	auto[0]	auto[1]	220220	1			T23	2		T26	22		T27	9
bins_for_gpio_bits[19]	auto[1]	auto[0]	220445	1			T23	2		T26	22		T27	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	4883045	1			T21	18		T22	8033		T23	50
bins_for_gpio_bits[20]	auto[0]	auto[0]	7341424	1			T21	8		T22	7964		T23	223
bins_for_gpio_bits[20]	auto[0]	auto[1]	220146	1			T26	21		T27	12		T29	28
bins_for_gpio_bits[20]	auto[1]	auto[0]	220421	1			T26	21		T27	12		T29	28
bins_for_gpio_bits[20]	auto[1]	auto[1]	4889354	1			T21	17		T22	9045		T23	39
bins_for_gpio_bits[21]	auto[0]	auto[0]	7337999	1			T21	10		T22	8996		T23	203
bins_for_gpio_bits[21]	auto[0]	auto[1]	220209	1			T23	1		T26	28		T27	17
bins_for_gpio_bits[21]	auto[1]	auto[0]	220469	1			T23	1		T26	29		T27	17
bins_for_gpio_bits[21]	auto[1]	auto[1]	4892668	1			T21	15		T22	8013		T23	57
bins_for_gpio_bits[22]	auto[0]	auto[0]	7340641	1			T21	13		T22	8652		T23	205
bins_for_gpio_bits[22]	auto[0]	auto[1]	220274	1			T23	3		T26	16		T27	18
bins_for_gpio_bits[22]	auto[1]	auto[0]	220486	1			T23	3		T26	17		T27	18
bins_for_gpio_bits[22]	auto[1]	auto[1]	4889944	1			T21	12		T22	8357		T23	51
bins_for_gpio_bits[23]	auto[0]	auto[0]	7358304	1			T21	11		T22	9233		T23	206
bins_for_gpio_bits[23]	auto[0]	auto[1]	220190	1			T23	2		T26	24		T27	17
bins_for_gpio_bits[23]	auto[1]	auto[0]	220441	1			T23	2		T26	24		T27	18
bins_for_gpio_bits[23]	auto[1]	auto[1]	4872410	1			T21	14		T22	7776		T23	52
bins_for_gpio_bits[24]	auto[0]	auto[0]	7348209	1			T21	13		T22	8223		T23	201
bins_for_gpio_bits[24]	auto[0]	auto[1]	220605	1			T23	3		T26	22		T27	18
bins_for_gpio_bits[24]	auto[1]	auto[0]	220851	1			T23	3		T26	23		T27	18
bins_for_gpio_bits[24]	auto[1]	auto[1]	4881680	1			T21	12		T22	8786		T23	55
bins_for_gpio_bits[25]	auto[0]	auto[0]	7333576	1			T21	14		T22	8324		T23	193
bins_for_gpio_bits[25]	auto[0]	auto[1]	220184	1			T23	4		T26	20		T27	15
bins_for_gpio_bits[25]	auto[1]	auto[0]	220392	1			T23	4		T26	20		T27	15
bins_for_gpio_bits[25]	auto[1]	auto[1]	4897193	1			T21	11		T22	8685		T23	61
bins_for_gpio_bits[26]	auto[0]	auto[0]	7338926	1			T21	5		T22	8674		T23	189
bins_for_gpio_bits[26]	auto[0]	auto[1]	220577	1			T23	3		T26	23		T27	7
bins_for_gpio_bits[26]	auto[1]	auto[0]	220789	1			T23	3		T26	23		T27	7
bins_for_gpio_bits[26]	auto[1]	auto[1]	4891053	1			T21	20		T22	8335		T23	67
bins_for_gpio_bits[27]	auto[0]	auto[0]	7348973	1			T21	10		T22	8894		T23	194
bins_for_gpio_bits[27]	auto[0]	auto[1]	221047	1			T23	4		T26	24		T27	13
bins_for_gpio_bits[27]	auto[1]	auto[0]	221290	1			T23	4		T26	25		T27	13
bins_for_gpio_bits[27]	auto[1]	auto[1]	4880035	1			T21	15		T22	8115		T23	60
bins_for_gpio_bits[28]	auto[0]	auto[0]	7351084	1			T21	8		T22	9116		T23	194
bins_for_gpio_bits[28]	auto[0]	auto[1]	219967	1			T23	5		T26	22		T27	19
bins_for_gpio_bits[28]	auto[1]	auto[0]	220196	1			T23	5		T26	22		T27	19
bins_for_gpio_bits[28]	auto[1]	auto[1]	4880098	1			T21	17		T22	7893		T23	58
bins_for_gpio_bits[29]	auto[0]	auto[0]	7346018	1			T21	7		T22	9109		T23	203
bins_for_gpio_bits[29]	auto[0]	auto[1]	220302	1			T23	3		T26	22		T27	16
bins_for_gpio_bits[29]	auto[1]	auto[0]	220548	1			T23	3		T26	22		T27	16
bins_for_gpio_bits[29]	auto[1]	auto[1]	4884477	1			T21	18		T22	7900		T23	53
bins_for_gpio_bits[30]	auto[0]	auto[0]	7334335	1			T21	15		T22	7495		T23	198
bins_for_gpio_bits[30]	auto[0]	auto[1]	220719	1			T23	4		T26	23		T27	11
bins_for_gpio_bits[30]	auto[1]	auto[0]	220992	1			T23	4		T26	24		T27	11
bins_for_gpio_bits[30]	auto[1]	auto[1]	4895299	1			T21	10		T22	9514		T23	56
bins_for_gpio_bits[31]	auto[0]	auto[0]	7349779	1			T21	14		T22	9473		T23	211
bins_for_gpio_bits[31]	auto[0]	auto[1]	220461	1			T26	20		T27	11		T29	24
bins_for_gpio_bits[31]	auto[1]	auto[0]	220687	1			T26	20		T27	12		T29	24
bins_for_gpio_bits[31]	auto[1]	auto[1]	4880418	1			T21	11		T22	7536		T23	51