Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7494651 |
1 |
|
|
T21 |
46 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5364019 |
1 |
|
|
T21 |
23 |
|
T28 |
866 |
|
T29 |
362 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12168299 |
1 |
|
|
T21 |
69 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
690371 |
1 |
|
|
T28 |
187 |
|
T29 |
22 |
|
T61 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468890 |
1 |
|
|
T21 |
51 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5389780 |
1 |
|
|
T21 |
18 |
|
T28 |
1027 |
|
T29 |
575 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2345487 |
1 |
|
|
T21 |
11 |
|
T28 |
567 |
|
T29 |
325 |
| auto[1] |
auto[0] |
auto[1] |
344420 |
1 |
|
|
T28 |
133 |
|
T29 |
13 |
|
T61 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2353922 |
1 |
|
|
T21 |
7 |
|
T28 |
273 |
|
T29 |
228 |
| auto[1] |
auto[1] |
auto[1] |
345951 |
1 |
|
|
T28 |
54 |
|
T29 |
9 |
|
T61 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7510278 |
1 |
|
|
T21 |
40 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5348392 |
1 |
|
|
T21 |
29 |
|
T28 |
1293 |
|
T29 |
547 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12171622 |
1 |
|
|
T21 |
67 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
687048 |
1 |
|
|
T21 |
2 |
|
T28 |
167 |
|
T29 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7500098 |
1 |
|
|
T21 |
38 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5358572 |
1 |
|
|
T21 |
31 |
|
T28 |
931 |
|
T29 |
359 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2350020 |
1 |
|
|
T21 |
16 |
|
T28 |
318 |
|
T29 |
147 |
| auto[1] |
auto[0] |
auto[1] |
345820 |
1 |
|
|
T21 |
1 |
|
T28 |
74 |
|
T29 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2321504 |
1 |
|
|
T21 |
13 |
|
T28 |
446 |
|
T29 |
199 |
| auto[1] |
auto[1] |
auto[1] |
341228 |
1 |
|
|
T21 |
1 |
|
T28 |
93 |
|
T29 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7507146 |
1 |
|
|
T21 |
18 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5351524 |
1 |
|
|
T21 |
51 |
|
T28 |
1009 |
|
T29 |
415 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12174903 |
1 |
|
|
T21 |
67 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
683767 |
1 |
|
|
T21 |
2 |
|
T28 |
196 |
|
T29 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7515694 |
1 |
|
|
T21 |
37 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5342976 |
1 |
|
|
T21 |
32 |
|
T28 |
1021 |
|
T29 |
505 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2333403 |
1 |
|
|
T21 |
13 |
|
T28 |
441 |
|
T29 |
299 |
| auto[1] |
auto[0] |
auto[1] |
342304 |
1 |
|
|
T28 |
102 |
|
T29 |
10 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2325806 |
1 |
|
|
T21 |
17 |
|
T28 |
384 |
|
T29 |
187 |
| auto[1] |
auto[1] |
auto[1] |
341463 |
1 |
|
|
T21 |
2 |
|
T28 |
94 |
|
T29 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7477681 |
1 |
|
|
T21 |
46 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5380989 |
1 |
|
|
T21 |
23 |
|
T28 |
1135 |
|
T29 |
568 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12170785 |
1 |
|
|
T21 |
66 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
687885 |
1 |
|
|
T21 |
3 |
|
T28 |
227 |
|
T29 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7493316 |
1 |
|
|
T21 |
26 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5365354 |
1 |
|
|
T21 |
43 |
|
T28 |
1196 |
|
T29 |
574 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2314452 |
1 |
|
|
T21 |
30 |
|
T28 |
531 |
|
T29 |
174 |
| auto[1] |
auto[0] |
auto[1] |
338942 |
1 |
|
|
T21 |
3 |
|
T28 |
123 |
|
T29 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2363017 |
1 |
|
|
T21 |
10 |
|
T28 |
438 |
|
T29 |
378 |
| auto[1] |
auto[1] |
auto[1] |
348943 |
1 |
|
|
T28 |
104 |
|
T29 |
15 |
|
T61 |
36 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7464490 |
1 |
|
|
T21 |
36 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5394180 |
1 |
|
|
T21 |
33 |
|
T28 |
1121 |
|
T29 |
460 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12171675 |
1 |
|
|
T21 |
68 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
686995 |
1 |
|
|
T21 |
1 |
|
T28 |
259 |
|
T29 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7493982 |
1 |
|
|
T21 |
31 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5364688 |
1 |
|
|
T21 |
38 |
|
T28 |
1408 |
|
T29 |
445 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2333813 |
1 |
|
|
T21 |
19 |
|
T28 |
591 |
|
T29 |
172 |
| auto[1] |
auto[0] |
auto[1] |
342677 |
1 |
|
|
T21 |
1 |
|
T28 |
143 |
|
T29 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2343880 |
1 |
|
|
T21 |
18 |
|
T28 |
558 |
|
T29 |
259 |
| auto[1] |
auto[1] |
auto[1] |
344318 |
1 |
|
|
T28 |
116 |
|
T29 |
10 |
|
T61 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7490856 |
1 |
|
|
T21 |
53 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5367814 |
1 |
|
|
T21 |
16 |
|
T28 |
1406 |
|
T29 |
458 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12175010 |
1 |
|
|
T21 |
68 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
683660 |
1 |
|
|
T21 |
1 |
|
T28 |
230 |
|
T29 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7517697 |
1 |
|
|
T21 |
29 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5340973 |
1 |
|
|
T21 |
40 |
|
T28 |
1225 |
|
T29 |
464 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2330720 |
1 |
|
|
T21 |
27 |
|
T28 |
378 |
|
T29 |
215 |
| auto[1] |
auto[0] |
auto[1] |
341779 |
1 |
|
|
T28 |
84 |
|
T29 |
9 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2326593 |
1 |
|
|
T21 |
12 |
|
T28 |
617 |
|
T29 |
229 |
| auto[1] |
auto[1] |
auto[1] |
341881 |
1 |
|
|
T21 |
1 |
|
T28 |
146 |
|
T29 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479348 |
1 |
|
|
T21 |
34 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5379322 |
1 |
|
|
T21 |
35 |
|
T28 |
961 |
|
T29 |
566 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12169240 |
1 |
|
|
T21 |
69 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
689430 |
1 |
|
|
T28 |
220 |
|
T29 |
17 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479897 |
1 |
|
|
T21 |
28 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5378773 |
1 |
|
|
T21 |
41 |
|
T28 |
1159 |
|
T29 |
361 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2337630 |
1 |
|
|
T21 |
22 |
|
T28 |
523 |
|
T29 |
112 |
| auto[1] |
auto[0] |
auto[1] |
342723 |
1 |
|
|
T28 |
119 |
|
T29 |
7 |
|
T61 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2351713 |
1 |
|
|
T21 |
19 |
|
T28 |
416 |
|
T29 |
232 |
| auto[1] |
auto[1] |
auto[1] |
346707 |
1 |
|
|
T28 |
101 |
|
T29 |
10 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7520479 |
1 |
|
|
T21 |
35 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5338191 |
1 |
|
|
T21 |
34 |
|
T28 |
1322 |
|
T29 |
556 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12174279 |
1 |
|
|
T21 |
68 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
684391 |
1 |
|
|
T21 |
1 |
|
T28 |
207 |
|
T29 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7513498 |
1 |
|
|
T21 |
36 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5345172 |
1 |
|
|
T21 |
33 |
|
T28 |
1159 |
|
T29 |
538 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2351768 |
1 |
|
|
T21 |
8 |
|
T28 |
397 |
|
T29 |
203 |
| auto[1] |
auto[0] |
auto[1] |
345387 |
1 |
|
|
T28 |
92 |
|
T29 |
7 |
|
T61 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2309013 |
1 |
|
|
T21 |
24 |
|
T28 |
555 |
|
T29 |
315 |
| auto[1] |
auto[1] |
auto[1] |
339004 |
1 |
|
|
T21 |
1 |
|
T28 |
115 |
|
T29 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7485909 |
1 |
|
|
T21 |
45 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5372761 |
1 |
|
|
T21 |
24 |
|
T28 |
1095 |
|
T29 |
490 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12174496 |
1 |
|
|
T21 |
68 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
684174 |
1 |
|
|
T21 |
1 |
|
T28 |
214 |
|
T29 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7499754 |
1 |
|
|
T21 |
58 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5358916 |
1 |
|
|
T21 |
11 |
|
T28 |
1203 |
|
T29 |
416 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2332326 |
1 |
|
|
T21 |
5 |
|
T28 |
586 |
|
T29 |
184 |
| auto[1] |
auto[0] |
auto[1] |
340790 |
1 |
|
|
T28 |
130 |
|
T29 |
4 |
|
T61 |
28 |
| auto[1] |
auto[1] |
auto[0] |
2342416 |
1 |
|
|
T21 |
5 |
|
T28 |
403 |
|
T29 |
220 |
| auto[1] |
auto[1] |
auto[1] |
343384 |
1 |
|
|
T21 |
1 |
|
T28 |
84 |
|
T29 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7483161 |
1 |
|
|
T21 |
29 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5375509 |
1 |
|
|
T21 |
40 |
|
T28 |
939 |
|
T29 |
470 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12170804 |
1 |
|
|
T21 |
69 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
687866 |
1 |
|
|
T28 |
280 |
|
T29 |
28 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7481184 |
1 |
|
|
T21 |
41 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5377486 |
1 |
|
|
T21 |
28 |
|
T28 |
1430 |
|
T29 |
521 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2319039 |
1 |
|
|
T21 |
10 |
|
T28 |
640 |
|
T29 |
212 |
| auto[1] |
auto[0] |
auto[1] |
338989 |
1 |
|
|
T28 |
161 |
|
T29 |
13 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2370581 |
1 |
|
|
T21 |
18 |
|
T28 |
510 |
|
T29 |
281 |
| auto[1] |
auto[1] |
auto[1] |
348877 |
1 |
|
|
T28 |
119 |
|
T29 |
15 |
|
T61 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7507285 |
1 |
|
|
T21 |
52 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5351385 |
1 |
|
|
T21 |
17 |
|
T28 |
882 |
|
T29 |
509 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12174204 |
1 |
|
|
T21 |
67 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
684466 |
1 |
|
|
T21 |
2 |
|
T28 |
249 |
|
T29 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7504234 |
1 |
|
|
T21 |
29 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5354436 |
1 |
|
|
T21 |
40 |
|
T28 |
1325 |
|
T29 |
370 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2336925 |
1 |
|
|
T21 |
27 |
|
T28 |
646 |
|
T29 |
120 |
| auto[1] |
auto[0] |
auto[1] |
342867 |
1 |
|
|
T21 |
1 |
|
T28 |
150 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2333045 |
1 |
|
|
T21 |
11 |
|
T28 |
430 |
|
T29 |
234 |
| auto[1] |
auto[1] |
auto[1] |
341599 |
1 |
|
|
T21 |
1 |
|
T28 |
99 |
|
T29 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7487930 |
1 |
|
|
T21 |
37 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5370740 |
1 |
|
|
T21 |
32 |
|
T28 |
1135 |
|
T29 |
434 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12176396 |
1 |
|
|
T21 |
68 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
682274 |
1 |
|
|
T21 |
1 |
|
T28 |
207 |
|
T29 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7526591 |
1 |
|
|
T21 |
25 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5332079 |
1 |
|
|
T21 |
44 |
|
T28 |
1155 |
|
T29 |
513 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2325651 |
1 |
|
|
T21 |
19 |
|
T28 |
459 |
|
T29 |
222 |
| auto[1] |
auto[0] |
auto[1] |
341163 |
1 |
|
|
T21 |
1 |
|
T28 |
101 |
|
T29 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2324154 |
1 |
|
|
T21 |
24 |
|
T28 |
489 |
|
T29 |
272 |
| auto[1] |
auto[1] |
auto[1] |
341111 |
1 |
|
|
T28 |
106 |
|
T29 |
11 |
|
T61 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7512306 |
1 |
|
|
T21 |
50 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5346364 |
1 |
|
|
T21 |
19 |
|
T28 |
828 |
|
T29 |
375 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12172015 |
1 |
|
|
T21 |
67 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
686655 |
1 |
|
|
T21 |
2 |
|
T28 |
242 |
|
T29 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7492210 |
1 |
|
|
T21 |
37 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5366460 |
1 |
|
|
T21 |
32 |
|
T28 |
1213 |
|
T29 |
404 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2337897 |
1 |
|
|
T21 |
18 |
|
T28 |
617 |
|
T29 |
239 |
| auto[1] |
auto[0] |
auto[1] |
342787 |
1 |
|
|
T21 |
1 |
|
T28 |
153 |
|
T29 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2341908 |
1 |
|
|
T21 |
12 |
|
T28 |
354 |
|
T29 |
148 |
| auto[1] |
auto[1] |
auto[1] |
343868 |
1 |
|
|
T21 |
1 |
|
T28 |
89 |
|
T29 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7536164 |
1 |
|
|
T21 |
19 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5322506 |
1 |
|
|
T21 |
50 |
|
T28 |
1362 |
|
T29 |
451 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12170934 |
1 |
|
|
T21 |
67 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
687736 |
1 |
|
|
T21 |
2 |
|
T28 |
165 |
|
T29 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7490086 |
1 |
|
|
T21 |
36 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5368584 |
1 |
|
|
T21 |
33 |
|
T28 |
890 |
|
T29 |
521 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2364596 |
1 |
|
|
T21 |
6 |
|
T28 |
254 |
|
T29 |
261 |
| auto[1] |
auto[0] |
auto[1] |
347681 |
1 |
|
|
T28 |
61 |
|
T29 |
11 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2316252 |
1 |
|
|
T21 |
25 |
|
T28 |
471 |
|
T29 |
239 |
| auto[1] |
auto[1] |
auto[1] |
340055 |
1 |
|
|
T21 |
2 |
|
T28 |
104 |
|
T29 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7504961 |
1 |
|
|
T21 |
40 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5353709 |
1 |
|
|
T21 |
29 |
|
T28 |
1066 |
|
T29 |
459 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12170135 |
1 |
|
|
T21 |
69 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
688535 |
1 |
|
|
T28 |
198 |
|
T29 |
17 |
|
T30 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7485198 |
1 |
|
|
T21 |
58 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5373472 |
1 |
|
|
T21 |
11 |
|
T28 |
1094 |
|
T29 |
485 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2360269 |
1 |
|
|
T21 |
7 |
|
T28 |
450 |
|
T29 |
219 |
| auto[1] |
auto[0] |
auto[1] |
346168 |
1 |
|
|
T28 |
93 |
|
T29 |
5 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2324668 |
1 |
|
|
T21 |
4 |
|
T28 |
446 |
|
T29 |
249 |
| auto[1] |
auto[1] |
auto[1] |
342367 |
1 |
|
|
T28 |
105 |
|
T29 |
12 |
|
T61 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7484992 |
1 |
|
|
T21 |
47 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5373678 |
1 |
|
|
T21 |
22 |
|
T28 |
826 |
|
T29 |
513 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12170755 |
1 |
|
|
T21 |
69 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
687915 |
1 |
|
|
T28 |
202 |
|
T29 |
12 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7484465 |
1 |
|
|
T21 |
48 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5374205 |
1 |
|
|
T21 |
21 |
|
T28 |
1077 |
|
T29 |
368 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2331882 |
1 |
|
|
T21 |
7 |
|
T28 |
576 |
|
T29 |
179 |
| auto[1] |
auto[0] |
auto[1] |
340139 |
1 |
|
|
T28 |
139 |
|
T29 |
7 |
|
T61 |
46 |
| auto[1] |
auto[1] |
auto[0] |
2354408 |
1 |
|
|
T21 |
14 |
|
T28 |
299 |
|
T29 |
177 |
| auto[1] |
auto[1] |
auto[1] |
347776 |
1 |
|
|
T28 |
63 |
|
T29 |
5 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7514710 |
1 |
|
|
T21 |
10 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5343960 |
1 |
|
|
T21 |
59 |
|
T28 |
1099 |
|
T29 |
359 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12173208 |
1 |
|
|
T21 |
69 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
685462 |
1 |
|
|
T28 |
214 |
|
T29 |
22 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7494847 |
1 |
|
|
T21 |
47 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5363823 |
1 |
|
|
T21 |
22 |
|
T28 |
1114 |
|
T29 |
541 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2355787 |
1 |
|
|
T21 |
4 |
|
T28 |
467 |
|
T29 |
326 |
| auto[1] |
auto[0] |
auto[1] |
345386 |
1 |
|
|
T28 |
114 |
|
T29 |
12 |
|
T61 |
54 |
| auto[1] |
auto[1] |
auto[0] |
2322574 |
1 |
|
|
T21 |
18 |
|
T28 |
433 |
|
T29 |
193 |
| auto[1] |
auto[1] |
auto[1] |
340076 |
1 |
|
|
T28 |
100 |
|
T29 |
10 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7480768 |
1 |
|
|
T21 |
25 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5377902 |
1 |
|
|
T21 |
44 |
|
T28 |
1169 |
|
T29 |
403 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12174443 |
1 |
|
|
T21 |
68 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
684227 |
1 |
|
|
T21 |
1 |
|
T28 |
169 |
|
T29 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7507958 |
1 |
|
|
T21 |
33 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5350712 |
1 |
|
|
T21 |
36 |
|
T28 |
853 |
|
T29 |
441 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2320215 |
1 |
|
|
T21 |
10 |
|
T28 |
306 |
|
T29 |
196 |
| auto[1] |
auto[0] |
auto[1] |
339396 |
1 |
|
|
T21 |
1 |
|
T28 |
73 |
|
T29 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2346270 |
1 |
|
|
T21 |
25 |
|
T28 |
378 |
|
T29 |
227 |
| auto[1] |
auto[1] |
auto[1] |
344831 |
1 |
|
|
T28 |
96 |
|
T29 |
11 |
|
T61 |
44 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7487841 |
1 |
|
|
T21 |
42 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5370829 |
1 |
|
|
T21 |
27 |
|
T28 |
938 |
|
T29 |
591 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12172665 |
1 |
|
|
T21 |
68 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
686005 |
1 |
|
|
T21 |
1 |
|
T28 |
205 |
|
T29 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7500072 |
1 |
|
|
T21 |
33 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5358598 |
1 |
|
|
T21 |
36 |
|
T28 |
1178 |
|
T29 |
388 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2338183 |
1 |
|
|
T21 |
18 |
|
T28 |
506 |
|
T29 |
134 |
| auto[1] |
auto[0] |
auto[1] |
342244 |
1 |
|
|
T21 |
1 |
|
T28 |
110 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2334410 |
1 |
|
|
T21 |
17 |
|
T28 |
467 |
|
T29 |
244 |
| auto[1] |
auto[1] |
auto[1] |
343761 |
1 |
|
|
T28 |
95 |
|
T29 |
5 |
|
T61 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7519870 |
1 |
|
|
T21 |
6 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5338800 |
1 |
|
|
T21 |
63 |
|
T28 |
1040 |
|
T29 |
334 |