Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7540537 |
1 |
|
|
T21 |
40 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5318133 |
1 |
|
|
T21 |
29 |
|
T28 |
1000 |
|
T29 |
365 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12178238 |
1 |
|
|
T21 |
68 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
680432 |
1 |
|
|
T21 |
1 |
|
T28 |
234 |
|
T29 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7526196 |
1 |
|
|
T21 |
30 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5332474 |
1 |
|
|
T21 |
39 |
|
T28 |
1277 |
|
T29 |
475 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2345034 |
1 |
|
|
T21 |
20 |
|
T28 |
605 |
|
T29 |
281 |
| auto[1] |
auto[0] |
auto[1] |
343064 |
1 |
|
|
T28 |
138 |
|
T29 |
11 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2307008 |
1 |
|
|
T21 |
18 |
|
T28 |
438 |
|
T29 |
176 |
| auto[1] |
auto[1] |
auto[1] |
337368 |
1 |
|
|
T21 |
1 |
|
T28 |
96 |
|
T29 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |