Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7496789 |
1 |
|
|
T21 |
29 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5361881 |
1 |
|
|
T21 |
40 |
|
T28 |
1252 |
|
T29 |
502 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12172478 |
1 |
|
|
T21 |
67 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
686192 |
1 |
|
|
T21 |
2 |
|
T28 |
222 |
|
T29 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7500006 |
1 |
|
|
T21 |
33 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5358664 |
1 |
|
|
T21 |
36 |
|
T28 |
1152 |
|
T29 |
548 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2337377 |
1 |
|
|
T21 |
11 |
|
T28 |
388 |
|
T29 |
262 |
| auto[1] |
auto[0] |
auto[1] |
343342 |
1 |
|
|
T21 |
1 |
|
T28 |
89 |
|
T29 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2335095 |
1 |
|
|
T21 |
23 |
|
T28 |
542 |
|
T29 |
273 |
| auto[1] |
auto[1] |
auto[1] |
342850 |
1 |
|
|
T21 |
1 |
|
T28 |
133 |
|
T29 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |