Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7494651 |
1 |
|
|
T21 |
46 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5364019 |
1 |
|
|
T21 |
23 |
|
T28 |
866 |
|
T29 |
362 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10668668 |
1 |
|
|
T21 |
65 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2190002 |
1 |
|
|
T21 |
4 |
|
T28 |
616 |
|
T29 |
93 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7518684 |
1 |
|
|
T21 |
54 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5339986 |
1 |
|
|
T21 |
15 |
|
T28 |
1208 |
|
T29 |
385 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1575337 |
1 |
|
|
T21 |
1 |
|
T28 |
367 |
|
T29 |
133 |
| auto[1] |
auto[0] |
auto[1] |
1097165 |
1 |
|
|
T21 |
3 |
|
T28 |
383 |
|
T29 |
66 |
| auto[1] |
auto[1] |
auto[0] |
1574647 |
1 |
|
|
T21 |
10 |
|
T28 |
225 |
|
T29 |
159 |
| auto[1] |
auto[1] |
auto[1] |
1092837 |
1 |
|
|
T21 |
1 |
|
T28 |
233 |
|
T29 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |