Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7510278 |
1 |
|
|
T21 |
40 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5348392 |
1 |
|
|
T21 |
29 |
|
T28 |
1293 |
|
T29 |
547 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10663631 |
1 |
|
|
T21 |
61 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2195039 |
1 |
|
|
T21 |
8 |
|
T28 |
439 |
|
T29 |
105 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7494052 |
1 |
|
|
T21 |
53 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5364618 |
1 |
|
|
T21 |
16 |
|
T28 |
885 |
|
T29 |
359 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1590711 |
1 |
|
|
T21 |
2 |
|
T28 |
228 |
|
T29 |
118 |
| auto[1] |
auto[0] |
auto[1] |
1097853 |
1 |
|
|
T21 |
3 |
|
T28 |
218 |
|
T29 |
50 |
| auto[1] |
auto[1] |
auto[0] |
1578868 |
1 |
|
|
T21 |
6 |
|
T28 |
218 |
|
T29 |
136 |
| auto[1] |
auto[1] |
auto[1] |
1097186 |
1 |
|
|
T21 |
5 |
|
T28 |
221 |
|
T29 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |