Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7507146 |
1 |
|
|
T21 |
18 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5351524 |
1 |
|
|
T21 |
51 |
|
T28 |
1009 |
|
T29 |
415 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10653509 |
1 |
|
|
T21 |
55 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2205161 |
1 |
|
|
T21 |
14 |
|
T28 |
364 |
|
T29 |
66 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7504210 |
1 |
|
|
T21 |
43 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5354460 |
1 |
|
|
T21 |
26 |
|
T28 |
711 |
|
T29 |
413 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1575900 |
1 |
|
|
T21 |
3 |
|
T28 |
197 |
|
T29 |
217 |
| auto[1] |
auto[0] |
auto[1] |
1107480 |
1 |
|
|
T28 |
218 |
|
T29 |
38 |
|
T61 |
34 |
| auto[1] |
auto[1] |
auto[0] |
1573399 |
1 |
|
|
T21 |
9 |
|
T28 |
150 |
|
T29 |
130 |
| auto[1] |
auto[1] |
auto[1] |
1097681 |
1 |
|
|
T21 |
14 |
|
T28 |
146 |
|
T29 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |