Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7477681 |
1 |
|
|
T21 |
46 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5380989 |
1 |
|
|
T21 |
23 |
|
T28 |
1135 |
|
T29 |
568 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10655637 |
1 |
|
|
T21 |
65 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2203033 |
1 |
|
|
T21 |
4 |
|
T28 |
663 |
|
T29 |
96 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7489002 |
1 |
|
|
T21 |
51 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5369668 |
1 |
|
|
T21 |
18 |
|
T28 |
1343 |
|
T29 |
506 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1574928 |
1 |
|
|
T21 |
11 |
|
T28 |
306 |
|
T29 |
96 |
| auto[1] |
auto[0] |
auto[1] |
1095212 |
1 |
|
|
T21 |
4 |
|
T28 |
289 |
|
T29 |
18 |
| auto[1] |
auto[1] |
auto[0] |
1591707 |
1 |
|
|
T21 |
3 |
|
T28 |
374 |
|
T29 |
314 |
| auto[1] |
auto[1] |
auto[1] |
1107821 |
1 |
|
|
T28 |
374 |
|
T29 |
78 |
|
T61 |
39 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |