Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12178493 |
1 |
|
|
T21 |
67 |
|
T22 |
17009 |
|
T23 |
142 |
auto[1] |
680177 |
1 |
|
|
T21 |
2 |
|
T28 |
205 |
|
T29 |
24 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7533595 |
1 |
|
|
T21 |
45 |
|
T22 |
17009 |
|
T23 |
142 |
auto[1] |
5325075 |
1 |
|
|
T21 |
24 |
|
T28 |
1090 |
|
T29 |
552 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2334491 |
1 |
|
|
T21 |
1 |
|
T28 |
584 |
|
T29 |
342 |
auto[1] |
auto[0] |
auto[1] |
341897 |
1 |
|
|
T21 |
1 |
|
T28 |
137 |
|
T29 |
16 |
auto[1] |
auto[1] |
auto[0] |
2310407 |
1 |
|
|
T21 |
21 |
|
T28 |
301 |
|
T29 |
186 |
auto[1] |
auto[1] |
auto[1] |
338280 |
1 |
|
|
T21 |
1 |
|
T28 |
68 |
|
T29 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |