Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7490856 |
1 |
|
|
T21 |
53 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5367814 |
1 |
|
|
T21 |
16 |
|
T28 |
1406 |
|
T29 |
458 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10679139 |
1 |
|
|
T21 |
66 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2179531 |
1 |
|
|
T21 |
3 |
|
T28 |
491 |
|
T29 |
170 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7533771 |
1 |
|
|
T21 |
66 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5324899 |
1 |
|
|
T21 |
3 |
|
T28 |
961 |
|
T29 |
544 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1568849 |
1 |
|
|
T28 |
176 |
|
T29 |
177 |
|
T30 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1087127 |
1 |
|
|
T21 |
3 |
|
T28 |
180 |
|
T29 |
64 |
| auto[1] |
auto[1] |
auto[0] |
1576519 |
1 |
|
|
T28 |
294 |
|
T29 |
197 |
|
T61 |
8 |
| auto[1] |
auto[1] |
auto[1] |
1092404 |
1 |
|
|
T28 |
311 |
|
T29 |
106 |
|
T61 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |