Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479348 |
1 |
|
|
T21 |
34 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5379322 |
1 |
|
|
T21 |
35 |
|
T28 |
961 |
|
T29 |
566 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10664873 |
1 |
|
|
T21 |
63 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2193797 |
1 |
|
|
T21 |
6 |
|
T28 |
507 |
|
T29 |
169 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7529011 |
1 |
|
|
T21 |
60 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5329659 |
1 |
|
|
T21 |
9 |
|
T28 |
1019 |
|
T29 |
540 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1560533 |
1 |
|
|
T28 |
231 |
|
T29 |
128 |
|
T61 |
26 |
| auto[1] |
auto[0] |
auto[1] |
1092365 |
1 |
|
|
T28 |
220 |
|
T29 |
67 |
|
T61 |
24 |
| auto[1] |
auto[1] |
auto[0] |
1575329 |
1 |
|
|
T21 |
3 |
|
T28 |
281 |
|
T29 |
243 |
| auto[1] |
auto[1] |
auto[1] |
1101432 |
1 |
|
|
T21 |
6 |
|
T28 |
287 |
|
T29 |
102 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |