Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7520479 |
1 |
|
|
T21 |
35 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5338191 |
1 |
|
|
T21 |
34 |
|
T28 |
1322 |
|
T29 |
556 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10656927 |
1 |
|
|
T21 |
53 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2201743 |
1 |
|
|
T21 |
16 |
|
T28 |
540 |
|
T29 |
94 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7500171 |
1 |
|
|
T21 |
34 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5358499 |
1 |
|
|
T21 |
35 |
|
T28 |
1114 |
|
T29 |
475 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1575506 |
1 |
|
|
T21 |
13 |
|
T28 |
297 |
|
T29 |
154 |
| auto[1] |
auto[0] |
auto[1] |
1103518 |
1 |
|
|
T21 |
11 |
|
T28 |
218 |
|
T29 |
41 |
| auto[1] |
auto[1] |
auto[0] |
1581250 |
1 |
|
|
T21 |
6 |
|
T28 |
277 |
|
T29 |
227 |
| auto[1] |
auto[1] |
auto[1] |
1098225 |
1 |
|
|
T21 |
5 |
|
T28 |
322 |
|
T29 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |