Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7485909 |
1 |
|
|
T21 |
45 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5372761 |
1 |
|
|
T21 |
24 |
|
T28 |
1095 |
|
T29 |
490 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10669776 |
1 |
|
|
T21 |
43 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2188894 |
1 |
|
|
T21 |
26 |
|
T28 |
705 |
|
T29 |
88 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7525248 |
1 |
|
|
T21 |
27 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5333422 |
1 |
|
|
T21 |
42 |
|
T28 |
1370 |
|
T29 |
479 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1564069 |
1 |
|
|
T21 |
5 |
|
T28 |
392 |
|
T29 |
191 |
| auto[1] |
auto[0] |
auto[1] |
1087295 |
1 |
|
|
T21 |
24 |
|
T28 |
387 |
|
T29 |
41 |
| auto[1] |
auto[1] |
auto[0] |
1580459 |
1 |
|
|
T21 |
11 |
|
T28 |
273 |
|
T29 |
200 |
| auto[1] |
auto[1] |
auto[1] |
1101599 |
1 |
|
|
T21 |
2 |
|
T28 |
318 |
|
T29 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |