Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7483161 |
1 |
|
|
T21 |
29 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5375509 |
1 |
|
|
T21 |
40 |
|
T28 |
939 |
|
T29 |
470 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10658429 |
1 |
|
|
T21 |
58 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2200241 |
1 |
|
|
T21 |
11 |
|
T28 |
531 |
|
T29 |
182 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7493296 |
1 |
|
|
T21 |
32 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5365374 |
1 |
|
|
T21 |
37 |
|
T28 |
1086 |
|
T29 |
528 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1568591 |
1 |
|
|
T21 |
12 |
|
T28 |
354 |
|
T29 |
183 |
| auto[1] |
auto[0] |
auto[1] |
1097297 |
1 |
|
|
T21 |
10 |
|
T28 |
331 |
|
T29 |
82 |
| auto[1] |
auto[1] |
auto[0] |
1596542 |
1 |
|
|
T21 |
14 |
|
T28 |
201 |
|
T29 |
163 |
| auto[1] |
auto[1] |
auto[1] |
1102944 |
1 |
|
|
T21 |
1 |
|
T28 |
200 |
|
T29 |
100 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |