Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7507285 |
1 |
|
|
T21 |
52 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5351385 |
1 |
|
|
T21 |
17 |
|
T28 |
882 |
|
T29 |
509 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10658132 |
1 |
|
|
T21 |
52 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2200538 |
1 |
|
|
T21 |
17 |
|
T28 |
601 |
|
T29 |
90 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7494031 |
1 |
|
|
T21 |
47 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5364639 |
1 |
|
|
T21 |
22 |
|
T28 |
1214 |
|
T29 |
441 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1590837 |
1 |
|
|
T21 |
4 |
|
T28 |
334 |
|
T29 |
153 |
| auto[1] |
auto[0] |
auto[1] |
1103951 |
1 |
|
|
T21 |
14 |
|
T28 |
368 |
|
T29 |
43 |
| auto[1] |
auto[1] |
auto[0] |
1573264 |
1 |
|
|
T21 |
1 |
|
T28 |
279 |
|
T29 |
198 |
| auto[1] |
auto[1] |
auto[1] |
1096587 |
1 |
|
|
T21 |
3 |
|
T28 |
233 |
|
T29 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |