Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7487930 |
1 |
|
|
T21 |
37 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5370740 |
1 |
|
|
T21 |
32 |
|
T28 |
1135 |
|
T29 |
434 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10659094 |
1 |
|
|
T21 |
64 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2199576 |
1 |
|
|
T21 |
5 |
|
T28 |
500 |
|
T29 |
73 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7487907 |
1 |
|
|
T21 |
45 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5370763 |
1 |
|
|
T21 |
24 |
|
T28 |
1015 |
|
T29 |
407 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1581074 |
1 |
|
|
T21 |
4 |
|
T28 |
340 |
|
T29 |
152 |
| auto[1] |
auto[0] |
auto[1] |
1100993 |
1 |
|
|
T21 |
5 |
|
T28 |
311 |
|
T29 |
18 |
| auto[1] |
auto[1] |
auto[0] |
1590113 |
1 |
|
|
T21 |
15 |
|
T28 |
175 |
|
T29 |
182 |
| auto[1] |
auto[1] |
auto[1] |
1098583 |
1 |
|
|
T28 |
189 |
|
T29 |
55 |
|
T61 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |