Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7512306 |
1 |
|
|
T21 |
50 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5346364 |
1 |
|
|
T21 |
19 |
|
T28 |
828 |
|
T29 |
375 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10656144 |
1 |
|
|
T21 |
63 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2202526 |
1 |
|
|
T21 |
6 |
|
T28 |
591 |
|
T29 |
95 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7504732 |
1 |
|
|
T21 |
63 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5353938 |
1 |
|
|
T21 |
6 |
|
T28 |
1216 |
|
T29 |
465 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1586288 |
1 |
|
|
T28 |
461 |
|
T29 |
210 |
|
T30 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1108918 |
1 |
|
|
T28 |
446 |
|
T29 |
39 |
|
T30 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1565124 |
1 |
|
|
T28 |
164 |
|
T29 |
160 |
|
T61 |
62 |
| auto[1] |
auto[1] |
auto[1] |
1093608 |
1 |
|
|
T21 |
6 |
|
T28 |
145 |
|
T29 |
56 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |