Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7536164 |
1 |
|
|
T21 |
19 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5322506 |
1 |
|
|
T21 |
50 |
|
T28 |
1362 |
|
T29 |
451 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10669780 |
1 |
|
|
T21 |
48 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2188890 |
1 |
|
|
T21 |
21 |
|
T28 |
479 |
|
T29 |
124 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7528965 |
1 |
|
|
T21 |
35 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5329705 |
1 |
|
|
T21 |
34 |
|
T28 |
979 |
|
T29 |
499 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1580145 |
1 |
|
|
T28 |
218 |
|
T29 |
162 |
|
T61 |
66 |
| auto[1] |
auto[0] |
auto[1] |
1101194 |
1 |
|
|
T21 |
7 |
|
T28 |
193 |
|
T29 |
75 |
| auto[1] |
auto[1] |
auto[0] |
1560670 |
1 |
|
|
T21 |
13 |
|
T28 |
282 |
|
T29 |
213 |
| auto[1] |
auto[1] |
auto[1] |
1087696 |
1 |
|
|
T21 |
14 |
|
T28 |
286 |
|
T29 |
49 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |