Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7504961 |
1 |
|
|
T21 |
40 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5353709 |
1 |
|
|
T21 |
29 |
|
T28 |
1066 |
|
T29 |
459 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10649961 |
1 |
|
|
T21 |
62 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2208709 |
1 |
|
|
T21 |
7 |
|
T28 |
554 |
|
T29 |
70 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7484525 |
1 |
|
|
T21 |
54 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5374145 |
1 |
|
|
T21 |
15 |
|
T28 |
1138 |
|
T29 |
400 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1587888 |
1 |
|
|
T21 |
8 |
|
T28 |
343 |
|
T29 |
159 |
| auto[1] |
auto[0] |
auto[1] |
1106757 |
1 |
|
|
T21 |
2 |
|
T28 |
301 |
|
T29 |
36 |
| auto[1] |
auto[1] |
auto[0] |
1577548 |
1 |
|
|
T28 |
241 |
|
T29 |
171 |
|
T61 |
47 |
| auto[1] |
auto[1] |
auto[1] |
1101952 |
1 |
|
|
T21 |
5 |
|
T28 |
253 |
|
T29 |
34 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |