Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7514464 |
1 |
|
|
T21 |
27 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5344206 |
1 |
|
|
T21 |
42 |
|
T28 |
999 |
|
T29 |
521 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12174097 |
1 |
|
|
T21 |
68 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
684573 |
1 |
|
|
T21 |
1 |
|
T28 |
166 |
|
T29 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7507227 |
1 |
|
|
T21 |
52 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5351443 |
1 |
|
|
T21 |
17 |
|
T28 |
919 |
|
T29 |
460 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2337977 |
1 |
|
|
T21 |
4 |
|
T28 |
386 |
|
T29 |
157 |
| auto[1] |
auto[0] |
auto[1] |
342949 |
1 |
|
|
T28 |
82 |
|
T29 |
8 |
|
T61 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2328893 |
1 |
|
|
T21 |
12 |
|
T28 |
367 |
|
T29 |
284 |
| auto[1] |
auto[1] |
auto[1] |
341624 |
1 |
|
|
T21 |
1 |
|
T28 |
84 |
|
T29 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |