Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7484992 |
1 |
|
|
T21 |
47 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5373678 |
1 |
|
|
T21 |
22 |
|
T28 |
826 |
|
T29 |
513 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10650647 |
1 |
|
|
T21 |
51 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2208023 |
1 |
|
|
T21 |
18 |
|
T28 |
711 |
|
T29 |
126 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7488267 |
1 |
|
|
T21 |
35 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5370403 |
1 |
|
|
T21 |
34 |
|
T28 |
1444 |
|
T29 |
447 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1581131 |
1 |
|
|
T21 |
8 |
|
T28 |
442 |
|
T29 |
144 |
| auto[1] |
auto[0] |
auto[1] |
1103074 |
1 |
|
|
T21 |
7 |
|
T28 |
461 |
|
T29 |
64 |
| auto[1] |
auto[1] |
auto[0] |
1581249 |
1 |
|
|
T21 |
8 |
|
T28 |
291 |
|
T29 |
177 |
| auto[1] |
auto[1] |
auto[1] |
1104949 |
1 |
|
|
T21 |
11 |
|
T28 |
250 |
|
T29 |
62 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |