Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7480768 |
1 |
|
|
T21 |
25 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5377902 |
1 |
|
|
T21 |
44 |
|
T28 |
1169 |
|
T29 |
403 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10658882 |
1 |
|
|
T21 |
59 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
2199788 |
1 |
|
|
T21 |
10 |
|
T28 |
613 |
|
T29 |
83 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7502671 |
1 |
|
|
T21 |
45 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5355999 |
1 |
|
|
T21 |
24 |
|
T28 |
1207 |
|
T29 |
368 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1579545 |
1 |
|
|
T21 |
2 |
|
T28 |
286 |
|
T29 |
138 |
| auto[1] |
auto[0] |
auto[1] |
1099080 |
1 |
|
|
T21 |
10 |
|
T28 |
263 |
|
T29 |
43 |
| auto[1] |
auto[1] |
auto[0] |
1576666 |
1 |
|
|
T21 |
12 |
|
T28 |
308 |
|
T29 |
147 |
| auto[1] |
auto[1] |
auto[1] |
1100708 |
1 |
|
|
T28 |
350 |
|
T29 |
40 |
|
T61 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |