Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7492598 |
1 |
|
|
T21 |
44 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5366072 |
1 |
|
|
T21 |
25 |
|
T28 |
1033 |
|
T29 |
406 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12176950 |
1 |
|
|
T21 |
67 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
681720 |
1 |
|
|
T21 |
2 |
|
T28 |
224 |
|
T29 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7527571 |
1 |
|
|
T21 |
47 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5331099 |
1 |
|
|
T21 |
22 |
|
T28 |
1225 |
|
T29 |
465 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2323512 |
1 |
|
|
T21 |
17 |
|
T28 |
531 |
|
T29 |
240 |
| auto[1] |
auto[0] |
auto[1] |
340331 |
1 |
|
|
T21 |
1 |
|
T28 |
116 |
|
T29 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2325867 |
1 |
|
|
T21 |
3 |
|
T28 |
470 |
|
T29 |
207 |
| auto[1] |
auto[1] |
auto[1] |
341389 |
1 |
|
|
T21 |
1 |
|
T28 |
108 |
|
T29 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |