Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7493959 |
1 |
|
|
T21 |
11 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5364711 |
1 |
|
|
T21 |
58 |
|
T28 |
1300 |
|
T29 |
302 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12175525 |
1 |
|
|
T21 |
67 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
683145 |
1 |
|
|
T21 |
2 |
|
T28 |
245 |
|
T29 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7517714 |
1 |
|
|
T21 |
50 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5340956 |
1 |
|
|
T21 |
19 |
|
T28 |
1281 |
|
T29 |
440 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2336805 |
1 |
|
|
T21 |
1 |
|
T28 |
421 |
|
T29 |
275 |
| auto[1] |
auto[0] |
auto[1] |
342118 |
1 |
|
|
T28 |
107 |
|
T29 |
11 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2321006 |
1 |
|
|
T21 |
16 |
|
T28 |
615 |
|
T29 |
148 |
| auto[1] |
auto[1] |
auto[1] |
341027 |
1 |
|
|
T21 |
2 |
|
T28 |
138 |
|
T29 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |