Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7482739 |
1 |
|
|
T21 |
21 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5375931 |
1 |
|
|
T21 |
48 |
|
T28 |
1371 |
|
T29 |
391 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12175622 |
1 |
|
|
T21 |
69 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
683048 |
1 |
|
|
T28 |
150 |
|
T29 |
22 |
|
T30 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7520549 |
1 |
|
|
T21 |
31 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5338121 |
1 |
|
|
T21 |
38 |
|
T28 |
861 |
|
T29 |
448 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2329811 |
1 |
|
|
T21 |
7 |
|
T28 |
263 |
|
T29 |
244 |
| auto[1] |
auto[0] |
auto[1] |
342122 |
1 |
|
|
T28 |
61 |
|
T29 |
14 |
|
T30 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2325262 |
1 |
|
|
T21 |
31 |
|
T28 |
448 |
|
T29 |
182 |
| auto[1] |
auto[1] |
auto[1] |
340926 |
1 |
|
|
T28 |
89 |
|
T29 |
8 |
|
T61 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |