Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7510663 |
1 |
|
|
T21 |
35 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5348007 |
1 |
|
|
T21 |
34 |
|
T28 |
1188 |
|
T29 |
445 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12173445 |
1 |
|
|
T21 |
69 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
685225 |
1 |
|
|
T28 |
206 |
|
T29 |
14 |
|
T30 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7499645 |
1 |
|
|
T21 |
62 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5359025 |
1 |
|
|
T21 |
7 |
|
T28 |
1127 |
|
T29 |
467 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2352587 |
1 |
|
|
T21 |
7 |
|
T28 |
406 |
|
T29 |
233 |
| auto[1] |
auto[0] |
auto[1] |
345186 |
1 |
|
|
T28 |
90 |
|
T29 |
8 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2321213 |
1 |
|
|
T28 |
515 |
|
T29 |
220 |
|
T61 |
49 |
| auto[1] |
auto[1] |
auto[1] |
340039 |
1 |
|
|
T28 |
116 |
|
T29 |
6 |
|
T61 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |