Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7509715 |
1 |
|
|
T21 |
44 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5348955 |
1 |
|
|
T21 |
25 |
|
T28 |
1118 |
|
T29 |
434 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12172278 |
1 |
|
|
T21 |
68 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
686392 |
1 |
|
|
T21 |
1 |
|
T28 |
170 |
|
T29 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7487964 |
1 |
|
|
T21 |
47 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5370706 |
1 |
|
|
T21 |
22 |
|
T28 |
876 |
|
T29 |
406 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2345652 |
1 |
|
|
T21 |
17 |
|
T28 |
378 |
|
T29 |
199 |
| auto[1] |
auto[0] |
auto[1] |
342229 |
1 |
|
|
T21 |
1 |
|
T28 |
92 |
|
T29 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2338662 |
1 |
|
|
T21 |
4 |
|
T28 |
328 |
|
T29 |
192 |
| auto[1] |
auto[1] |
auto[1] |
344163 |
1 |
|
|
T28 |
78 |
|
T29 |
12 |
|
T61 |
34 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |