Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7503567 |
1 |
|
|
T21 |
48 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5355103 |
1 |
|
|
T21 |
21 |
|
T28 |
1214 |
|
T29 |
548 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12178191 |
1 |
|
|
T21 |
67 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
680479 |
1 |
|
|
T21 |
2 |
|
T28 |
199 |
|
T29 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7543066 |
1 |
|
|
T21 |
18 |
|
T22 |
17009 |
|
T23 |
142 |
| auto[1] |
5315604 |
1 |
|
|
T21 |
51 |
|
T28 |
1091 |
|
T29 |
407 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2320350 |
1 |
|
|
T21 |
32 |
|
T28 |
324 |
|
T29 |
158 |
| auto[1] |
auto[0] |
auto[1] |
340900 |
1 |
|
|
T21 |
1 |
|
T28 |
74 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2314775 |
1 |
|
|
T21 |
17 |
|
T28 |
568 |
|
T29 |
238 |
| auto[1] |
auto[1] |
auto[1] |
339579 |
1 |
|
|
T21 |
1 |
|
T28 |
125 |
|
T29 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |