Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 941
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T761 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2513687599 Jun 05 05:13:28 PM PDT 24 Jun 05 05:13:32 PM PDT 24 1294495294 ps
T762 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2325951718 Jun 05 05:13:54 PM PDT 24 Jun 05 05:13:56 PM PDT 24 20194325 ps
T763 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1844253807 Jun 05 05:13:56 PM PDT 24 Jun 05 05:13:58 PM PDT 24 12336997 ps
T764 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3512313101 Jun 05 05:13:54 PM PDT 24 Jun 05 05:13:55 PM PDT 24 14943218 ps
T765 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3532596284 Jun 05 05:13:37 PM PDT 24 Jun 05 05:13:38 PM PDT 24 21817681 ps
T114 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3665395644 Jun 05 05:13:33 PM PDT 24 Jun 05 05:13:35 PM PDT 24 41231423 ps
T110 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3074880172 Jun 05 05:13:27 PM PDT 24 Jun 05 05:13:28 PM PDT 24 160880964 ps
T766 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1063220339 Jun 05 05:13:12 PM PDT 24 Jun 05 05:13:15 PM PDT 24 389829290 ps
T767 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3145774488 Jun 05 05:13:13 PM PDT 24 Jun 05 05:13:15 PM PDT 24 23797914 ps
T768 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1695135685 Jun 05 05:13:33 PM PDT 24 Jun 05 05:13:35 PM PDT 24 97683587 ps
T769 /workspace/coverage/cover_reg_top/44.gpio_intr_test.2820445078 Jun 05 05:14:02 PM PDT 24 Jun 05 05:14:03 PM PDT 24 175661936 ps
T770 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.374024212 Jun 05 05:13:15 PM PDT 24 Jun 05 05:13:16 PM PDT 24 81057938 ps
T771 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.221200717 Jun 05 05:13:20 PM PDT 24 Jun 05 05:13:21 PM PDT 24 83484590 ps
T46 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.92265753 Jun 05 05:13:54 PM PDT 24 Jun 05 05:13:56 PM PDT 24 265511981 ps
T111 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1568986403 Jun 05 05:13:34 PM PDT 24 Jun 05 05:13:36 PM PDT 24 77986581 ps
T98 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1063041559 Jun 05 05:13:55 PM PDT 24 Jun 05 05:13:57 PM PDT 24 35867229 ps
T99 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.933093120 Jun 05 05:13:46 PM PDT 24 Jun 05 05:13:47 PM PDT 24 11167908 ps
T772 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1708967986 Jun 05 05:13:55 PM PDT 24 Jun 05 05:13:57 PM PDT 24 14351483 ps
T773 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2061576071 Jun 05 05:13:34 PM PDT 24 Jun 05 05:13:38 PM PDT 24 49501931 ps
T774 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.833532497 Jun 05 05:13:54 PM PDT 24 Jun 05 05:13:56 PM PDT 24 285802819 ps
T775 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2786428068 Jun 05 05:13:56 PM PDT 24 Jun 05 05:13:58 PM PDT 24 12806230 ps
T776 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3017242181 Jun 05 05:13:57 PM PDT 24 Jun 05 05:13:59 PM PDT 24 23043504 ps
T777 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3218323535 Jun 05 05:13:54 PM PDT 24 Jun 05 05:13:59 PM PDT 24 275738430 ps
T778 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2409403351 Jun 05 05:13:21 PM PDT 24 Jun 05 05:13:22 PM PDT 24 14928334 ps
T779 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1168297306 Jun 05 05:13:58 PM PDT 24 Jun 05 05:13:59 PM PDT 24 23132797 ps
T780 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4276071182 Jun 05 05:13:56 PM PDT 24 Jun 05 05:13:58 PM PDT 24 25813938 ps
T781 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2412862291 Jun 05 05:13:24 PM PDT 24 Jun 05 05:13:25 PM PDT 24 234206934 ps
T47 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.4110175605 Jun 05 05:13:56 PM PDT 24 Jun 05 05:13:59 PM PDT 24 95199800 ps
T782 /workspace/coverage/cover_reg_top/42.gpio_intr_test.164996750 Jun 05 05:13:53 PM PDT 24 Jun 05 05:13:54 PM PDT 24 57738242 ps
T783 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2800332284 Jun 05 05:13:43 PM PDT 24 Jun 05 05:13:45 PM PDT 24 19290787 ps
T784 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1313729459 Jun 05 05:13:20 PM PDT 24 Jun 05 05:13:22 PM PDT 24 25899448 ps
T785 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2395678234 Jun 05 05:14:03 PM PDT 24 Jun 05 05:14:04 PM PDT 24 13747076 ps
T786 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3749938988 Jun 05 05:13:56 PM PDT 24 Jun 05 05:13:58 PM PDT 24 125215823 ps
T787 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.158115711 Jun 05 05:13:12 PM PDT 24 Jun 05 05:13:14 PM PDT 24 857771382 ps
T788 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2403407081 Jun 05 05:13:57 PM PDT 24 Jun 05 05:13:59 PM PDT 24 44101446 ps
T789 /workspace/coverage/cover_reg_top/2.gpio_intr_test.633864786 Jun 05 05:13:13 PM PDT 24 Jun 05 05:13:14 PM PDT 24 33326338 ps
T790 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.827986462 Jun 05 05:13:53 PM PDT 24 Jun 05 05:13:55 PM PDT 24 36626175 ps
T791 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.61288019 Jun 05 05:13:29 PM PDT 24 Jun 05 05:13:30 PM PDT 24 21498760 ps
T792 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1079382124 Jun 05 05:13:14 PM PDT 24 Jun 05 05:13:16 PM PDT 24 82034750 ps
T793 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.975033813 Jun 05 05:13:33 PM PDT 24 Jun 05 05:13:34 PM PDT 24 158853195 ps
T794 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1711803280 Jun 05 05:13:43 PM PDT 24 Jun 05 05:13:44 PM PDT 24 12534719 ps
T795 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2769275084 Jun 05 05:13:13 PM PDT 24 Jun 05 05:13:14 PM PDT 24 60760992 ps
T796 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2372034154 Jun 05 05:13:21 PM PDT 24 Jun 05 05:13:22 PM PDT 24 24653088 ps
T797 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3534789495 Jun 05 05:13:54 PM PDT 24 Jun 05 05:13:57 PM PDT 24 382078640 ps
T798 /workspace/coverage/cover_reg_top/35.gpio_intr_test.190433629 Jun 05 05:13:54 PM PDT 24 Jun 05 05:13:56 PM PDT 24 49147675 ps
T799 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3188876058 Jun 05 05:13:53 PM PDT 24 Jun 05 05:13:54 PM PDT 24 73525792 ps
T800 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2332701502 Jun 05 05:13:43 PM PDT 24 Jun 05 05:13:45 PM PDT 24 19333703 ps
T801 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3409256628 Jun 05 05:13:52 PM PDT 24 Jun 05 05:13:55 PM PDT 24 32671439 ps
T802 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3967388046 Jun 05 05:13:56 PM PDT 24 Jun 05 05:13:59 PM PDT 24 286912648 ps
T803 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.584378507 Jun 05 05:13:36 PM PDT 24 Jun 05 05:13:37 PM PDT 24 33130909 ps
T804 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.450465139 Jun 05 05:13:42 PM PDT 24 Jun 05 05:13:45 PM PDT 24 104080571 ps
T805 /workspace/coverage/cover_reg_top/49.gpio_intr_test.202615262 Jun 05 05:14:02 PM PDT 24 Jun 05 05:14:04 PM PDT 24 13533388 ps
T806 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.734063618 Jun 05 05:13:53 PM PDT 24 Jun 05 05:13:55 PM PDT 24 64620622 ps
T807 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3987438020 Jun 05 05:13:42 PM PDT 24 Jun 05 05:13:44 PM PDT 24 32140890 ps
T808 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2143916760 Jun 05 05:13:20 PM PDT 24 Jun 05 05:13:23 PM PDT 24 143726646 ps
T809 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3400150129 Jun 05 05:13:27 PM PDT 24 Jun 05 05:13:29 PM PDT 24 18796804 ps
T810 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1187874273 Jun 05 05:13:07 PM PDT 24 Jun 05 05:13:08 PM PDT 24 42263716 ps
T100 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.620039412 Jun 05 05:13:06 PM PDT 24 Jun 05 05:13:07 PM PDT 24 13144251 ps
T811 /workspace/coverage/cover_reg_top/32.gpio_intr_test.951665295 Jun 05 05:13:59 PM PDT 24 Jun 05 05:14:00 PM PDT 24 23966563 ps
T812 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1937905087 Jun 05 05:13:42 PM PDT 24 Jun 05 05:13:43 PM PDT 24 23164266 ps
T813 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2498848717 Jun 05 05:13:32 PM PDT 24 Jun 05 05:13:33 PM PDT 24 25684533 ps
T814 /workspace/coverage/cover_reg_top/0.gpio_intr_test.4010180385 Jun 05 05:13:08 PM PDT 24 Jun 05 05:13:09 PM PDT 24 18263585 ps
T815 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1385133376 Jun 05 05:13:44 PM PDT 24 Jun 05 05:13:45 PM PDT 24 17190407 ps
T816 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.659253361 Jun 05 05:13:23 PM PDT 24 Jun 05 05:13:25 PM PDT 24 72213593 ps
T817 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.176535718 Jun 05 05:13:55 PM PDT 24 Jun 05 05:13:57 PM PDT 24 20322101 ps
T818 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1683263198 Jun 05 05:13:29 PM PDT 24 Jun 05 05:13:30 PM PDT 24 21907779 ps
T819 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3190662030 Jun 05 05:13:35 PM PDT 24 Jun 05 05:13:36 PM PDT 24 86139814 ps
T820 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4244132342 Jun 05 05:13:56 PM PDT 24 Jun 05 05:13:58 PM PDT 24 44277711 ps
T821 /workspace/coverage/cover_reg_top/9.gpio_intr_test.284815540 Jun 05 05:13:35 PM PDT 24 Jun 05 05:13:36 PM PDT 24 22641042 ps
T822 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.4289281779 Jun 05 05:13:28 PM PDT 24 Jun 05 05:13:29 PM PDT 24 36956290 ps
T823 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.762244535 Jun 05 05:13:21 PM PDT 24 Jun 05 05:13:22 PM PDT 24 234726170 ps
T824 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2719838430 Jun 05 05:13:34 PM PDT 24 Jun 05 05:13:36 PM PDT 24 33408869 ps
T825 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1796246563 Jun 05 05:13:57 PM PDT 24 Jun 05 05:13:59 PM PDT 24 27544386 ps
T102 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1469476948 Jun 05 05:13:14 PM PDT 24 Jun 05 05:13:18 PM PDT 24 257696244 ps
T826 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.365776115 Jun 05 05:13:42 PM PDT 24 Jun 05 05:13:44 PM PDT 24 45453359 ps
T827 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3581931858 Jun 05 05:13:11 PM PDT 24 Jun 05 05:13:14 PM PDT 24 2789254329 ps
T828 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2286605006 Jun 05 05:13:21 PM PDT 24 Jun 05 05:13:23 PM PDT 24 110524736 ps
T101 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.367034570 Jun 05 05:13:21 PM PDT 24 Jun 05 05:13:22 PM PDT 24 21803891 ps
T829 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3988522146 Jun 05 05:13:55 PM PDT 24 Jun 05 05:13:57 PM PDT 24 14360451 ps
T830 /workspace/coverage/cover_reg_top/41.gpio_intr_test.95823729 Jun 05 05:13:53 PM PDT 24 Jun 05 05:13:55 PM PDT 24 20787314 ps
T831 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3829190942 Jun 05 05:13:54 PM PDT 24 Jun 05 05:13:57 PM PDT 24 41166386 ps
T832 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.572217531 Jun 05 05:13:24 PM PDT 24 Jun 05 05:13:25 PM PDT 24 377581533 ps
T833 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3320239251 Jun 05 05:13:09 PM PDT 24 Jun 05 05:13:10 PM PDT 24 27546446 ps
T834 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3994458475 Jun 05 05:13:54 PM PDT 24 Jun 05 05:13:57 PM PDT 24 50500359 ps
T835 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1145088692 Jun 05 05:13:20 PM PDT 24 Jun 05 05:13:22 PM PDT 24 136552045 ps
T836 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1838523216 Jun 05 05:13:21 PM PDT 24 Jun 05 05:13:22 PM PDT 24 49818089 ps
T837 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.324037338 Jun 05 05:13:20 PM PDT 24 Jun 05 05:13:22 PM PDT 24 220561783 ps
T838 /workspace/coverage/cover_reg_top/19.gpio_intr_test.555190770 Jun 05 05:13:56 PM PDT 24 Jun 05 05:13:58 PM PDT 24 21674534 ps
T839 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1295805752 Jun 05 05:13:35 PM PDT 24 Jun 05 05:13:38 PM PDT 24 69634156 ps
T840 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3528929331 Jun 05 05:13:55 PM PDT 24 Jun 05 05:13:57 PM PDT 24 45170826 ps
T841 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2435442889 Jun 05 05:13:58 PM PDT 24 Jun 05 05:13:59 PM PDT 24 38284844 ps
T842 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2138142681 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:22 PM PDT 24 356987796 ps
T843 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1431112213 Jun 05 04:20:14 PM PDT 24 Jun 05 04:20:16 PM PDT 24 276422675 ps
T844 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2759021654 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:23 PM PDT 24 102187819 ps
T845 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4094180922 Jun 05 04:20:15 PM PDT 24 Jun 05 04:20:17 PM PDT 24 57711801 ps
T846 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1971960300 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:23 PM PDT 24 216288557 ps
T847 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2275110560 Jun 05 04:20:22 PM PDT 24 Jun 05 04:20:24 PM PDT 24 227981688 ps
T848 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2048968124 Jun 05 04:20:25 PM PDT 24 Jun 05 04:20:27 PM PDT 24 62047465 ps
T849 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2778981216 Jun 05 04:20:12 PM PDT 24 Jun 05 04:20:14 PM PDT 24 151262365 ps
T850 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2007114897 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:23 PM PDT 24 60001535 ps
T851 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3436639448 Jun 05 04:20:31 PM PDT 24 Jun 05 04:20:34 PM PDT 24 218920677 ps
T852 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3729116367 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:26 PM PDT 24 146963968 ps
T853 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3431879812 Jun 05 04:20:10 PM PDT 24 Jun 05 04:20:12 PM PDT 24 261155408 ps
T854 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.957731718 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:27 PM PDT 24 55434883 ps
T855 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4098880012 Jun 05 04:20:14 PM PDT 24 Jun 05 04:20:16 PM PDT 24 148720519 ps
T856 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2122141908 Jun 05 04:20:22 PM PDT 24 Jun 05 04:20:25 PM PDT 24 100068240 ps
T857 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1292862619 Jun 05 04:20:26 PM PDT 24 Jun 05 04:20:28 PM PDT 24 76748731 ps
T858 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2730757449 Jun 05 04:20:26 PM PDT 24 Jun 05 04:20:28 PM PDT 24 143893538 ps
T859 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2705688659 Jun 05 04:20:10 PM PDT 24 Jun 05 04:20:12 PM PDT 24 151533888 ps
T860 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2576931689 Jun 05 04:20:15 PM PDT 24 Jun 05 04:20:17 PM PDT 24 292718894 ps
T861 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.323612527 Jun 05 04:20:22 PM PDT 24 Jun 05 04:20:24 PM PDT 24 221935702 ps
T862 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2723278354 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:26 PM PDT 24 45926809 ps
T863 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2419800720 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:25 PM PDT 24 295964187 ps
T864 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.356992613 Jun 05 04:20:10 PM PDT 24 Jun 05 04:20:11 PM PDT 24 758623030 ps
T865 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3879461411 Jun 05 04:20:10 PM PDT 24 Jun 05 04:20:13 PM PDT 24 522123120 ps
T866 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3556768756 Jun 05 04:20:14 PM PDT 24 Jun 05 04:20:16 PM PDT 24 201084305 ps
T867 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1057630128 Jun 05 04:20:09 PM PDT 24 Jun 05 04:20:10 PM PDT 24 144870053 ps
T868 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3263662827 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:26 PM PDT 24 54573535 ps
T869 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3244177373 Jun 05 04:20:08 PM PDT 24 Jun 05 04:20:10 PM PDT 24 1016153987 ps
T870 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2556347386 Jun 05 04:20:15 PM PDT 24 Jun 05 04:20:16 PM PDT 24 109256836 ps
T871 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1046533732 Jun 05 04:20:25 PM PDT 24 Jun 05 04:20:27 PM PDT 24 188276730 ps
T872 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.280247114 Jun 05 04:20:13 PM PDT 24 Jun 05 04:20:15 PM PDT 24 39539713 ps
T873 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1118786859 Jun 05 04:20:15 PM PDT 24 Jun 05 04:20:16 PM PDT 24 140375048 ps
T874 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3960271093 Jun 05 04:20:12 PM PDT 24 Jun 05 04:20:14 PM PDT 24 45520201 ps
T875 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2179418259 Jun 05 04:20:08 PM PDT 24 Jun 05 04:20:10 PM PDT 24 1397230293 ps
T876 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1339985143 Jun 05 04:20:32 PM PDT 24 Jun 05 04:20:34 PM PDT 24 29533995 ps
T877 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.844248230 Jun 05 04:20:25 PM PDT 24 Jun 05 04:20:28 PM PDT 24 196433786 ps
T878 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2214599561 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:25 PM PDT 24 74293954 ps
T879 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3396037146 Jun 05 04:20:20 PM PDT 24 Jun 05 04:20:22 PM PDT 24 180257102 ps
T880 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3977690278 Jun 05 04:20:32 PM PDT 24 Jun 05 04:20:34 PM PDT 24 129742963 ps
T881 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.790266805 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:26 PM PDT 24 149761248 ps
T882 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3785210002 Jun 05 04:20:20 PM PDT 24 Jun 05 04:20:22 PM PDT 24 93714499 ps
T883 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4172328803 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:25 PM PDT 24 203186851 ps
T884 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.649344099 Jun 05 04:20:22 PM PDT 24 Jun 05 04:20:24 PM PDT 24 211436485 ps
T885 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.521432638 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:26 PM PDT 24 270844349 ps
T886 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3065185300 Jun 05 04:20:11 PM PDT 24 Jun 05 04:20:13 PM PDT 24 45478247 ps
T887 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1462430700 Jun 05 04:20:10 PM PDT 24 Jun 05 04:20:13 PM PDT 24 98815801 ps
T888 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.305236785 Jun 05 04:20:11 PM PDT 24 Jun 05 04:20:13 PM PDT 24 31907532 ps
T889 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2173336609 Jun 05 04:20:11 PM PDT 24 Jun 05 04:20:13 PM PDT 24 644106861 ps
T890 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2426996089 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:26 PM PDT 24 110452514 ps
T891 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3701641848 Jun 05 04:20:22 PM PDT 24 Jun 05 04:20:24 PM PDT 24 154948264 ps
T892 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1805377497 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:23 PM PDT 24 154468102 ps
T893 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.494748195 Jun 05 04:20:31 PM PDT 24 Jun 05 04:20:32 PM PDT 24 145246116 ps
T894 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2867618293 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:23 PM PDT 24 37282638 ps
T895 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3972128757 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:23 PM PDT 24 97322709 ps
T896 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2664891149 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:23 PM PDT 24 65663475 ps
T897 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3829714565 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:23 PM PDT 24 111121119 ps
T898 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1506561402 Jun 05 04:20:20 PM PDT 24 Jun 05 04:20:22 PM PDT 24 52536126 ps
T899 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3320826395 Jun 05 04:20:26 PM PDT 24 Jun 05 04:20:28 PM PDT 24 57195739 ps
T900 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2640891031 Jun 05 04:20:22 PM PDT 24 Jun 05 04:20:25 PM PDT 24 271484526 ps
T901 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.684327851 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:26 PM PDT 24 69877952 ps
T902 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1132820222 Jun 05 04:20:13 PM PDT 24 Jun 05 04:20:14 PM PDT 24 78789606 ps
T903 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.607365146 Jun 05 04:20:13 PM PDT 24 Jun 05 04:20:15 PM PDT 24 151296411 ps
T904 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.362222082 Jun 05 04:20:19 PM PDT 24 Jun 05 04:20:21 PM PDT 24 951076305 ps
T905 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.678581933 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:26 PM PDT 24 118584612 ps
T906 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3640874379 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:26 PM PDT 24 50365592 ps
T907 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4061246858 Jun 05 04:20:09 PM PDT 24 Jun 05 04:20:11 PM PDT 24 47207812 ps
T908 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3990792064 Jun 05 04:20:10 PM PDT 24 Jun 05 04:20:13 PM PDT 24 52075283 ps
T909 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2637641713 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:26 PM PDT 24 438887204 ps
T910 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2020476006 Jun 05 04:20:22 PM PDT 24 Jun 05 04:20:25 PM PDT 24 93872559 ps
T911 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3860186062 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:27 PM PDT 24 194345472 ps
T912 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2868175581 Jun 05 04:20:26 PM PDT 24 Jun 05 04:20:28 PM PDT 24 500549029 ps
T913 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1023110965 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:26 PM PDT 24 143460910 ps
T914 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2125857219 Jun 05 04:20:13 PM PDT 24 Jun 05 04:20:15 PM PDT 24 325576356 ps
T915 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1301483871 Jun 05 04:20:15 PM PDT 24 Jun 05 04:20:17 PM PDT 24 119829100 ps
T916 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.918220817 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:27 PM PDT 24 137516026 ps
T917 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3968522472 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:27 PM PDT 24 190432615 ps
T918 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.721800215 Jun 05 04:20:15 PM PDT 24 Jun 05 04:20:17 PM PDT 24 83913661 ps
T919 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1480841645 Jun 05 04:20:10 PM PDT 24 Jun 05 04:20:13 PM PDT 24 225814239 ps
T920 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2985730503 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:23 PM PDT 24 198048265 ps
T921 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1729670376 Jun 05 04:20:27 PM PDT 24 Jun 05 04:20:29 PM PDT 24 75060947 ps
T922 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.639094403 Jun 05 04:20:34 PM PDT 24 Jun 05 04:20:36 PM PDT 24 57459731 ps
T923 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.156951084 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:24 PM PDT 24 292630775 ps
T924 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3270628841 Jun 05 04:20:15 PM PDT 24 Jun 05 04:20:17 PM PDT 24 225292106 ps
T925 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.61343006 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:26 PM PDT 24 181124657 ps
T926 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2087206808 Jun 05 04:20:10 PM PDT 24 Jun 05 04:20:12 PM PDT 24 295915926 ps
T927 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2536600716 Jun 05 04:20:09 PM PDT 24 Jun 05 04:20:11 PM PDT 24 165714592 ps
T928 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3633605399 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:23 PM PDT 24 69498009 ps
T929 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.919742524 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:25 PM PDT 24 169835502 ps
T930 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4185739944 Jun 05 04:20:24 PM PDT 24 Jun 05 04:20:27 PM PDT 24 397159676 ps
T931 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.291288955 Jun 05 04:20:15 PM PDT 24 Jun 05 04:20:16 PM PDT 24 49511070 ps
T932 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2436667099 Jun 05 04:20:23 PM PDT 24 Jun 05 04:20:25 PM PDT 24 1075385843 ps
T933 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3107907142 Jun 05 04:20:11 PM PDT 24 Jun 05 04:20:13 PM PDT 24 26384888 ps
T934 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.897761132 Jun 05 04:20:13 PM PDT 24 Jun 05 04:20:15 PM PDT 24 86380710 ps
T935 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.553050965 Jun 05 04:20:10 PM PDT 24 Jun 05 04:20:13 PM PDT 24 53235177 ps
T936 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1546057406 Jun 05 04:20:35 PM PDT 24 Jun 05 04:20:37 PM PDT 24 110606031 ps
T937 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3770724816 Jun 05 04:20:22 PM PDT 24 Jun 05 04:20:24 PM PDT 24 25509636 ps
T938 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.498540480 Jun 05 04:20:12 PM PDT 24 Jun 05 04:20:14 PM PDT 24 218247515 ps
T939 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.59875944 Jun 05 04:20:14 PM PDT 24 Jun 05 04:20:16 PM PDT 24 146321012 ps
T940 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3896345978 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:22 PM PDT 24 130895862 ps
T941 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3107798903 Jun 05 04:20:21 PM PDT 24 Jun 05 04:20:24 PM PDT 24 95128439 ps

Test location /workspace/coverage/default/20.gpio_full_random.118872902
Short name T30
Test name
Test status
Simulation time 78004140 ps
CPU time 0.7 seconds
Started Jun 05 05:14:58 PM PDT 24
Finished Jun 05 05:14:59 PM PDT 24
Peak memory 195492 kb
Host smart-4b47e2f0-a07d-47d8-b488-ce21f8f0c999
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118872902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.118872902
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2015241393
Short name T24
Test name
Test status
Simulation time 155187716 ps
CPU time 1.8 seconds
Started Jun 05 05:16:44 PM PDT 24
Finished Jun 05 05:16:46 PM PDT 24
Peak memory 198104 kb
Host smart-f67d8ef0-8403-431a-a90f-c3ee8dc34adb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015241393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2015241393
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1403450571
Short name T1
Test name
Test status
Simulation time 12461463812 ps
CPU time 114.52 seconds
Started Jun 05 05:15:40 PM PDT 24
Finished Jun 05 05:17:35 PM PDT 24
Peak memory 198240 kb
Host smart-fc8aeab0-cc82-48c4-8921-206c945b9646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403450571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1403450571
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3273809124
Short name T31
Test name
Test status
Simulation time 191243317679 ps
CPU time 2505.39 seconds
Started Jun 05 05:15:46 PM PDT 24
Finished Jun 05 05:57:33 PM PDT 24
Peak memory 198260 kb
Host smart-f68bec13-3345-43cc-b70a-5e890a485a5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3273809124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3273809124
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3788267832
Short name T38
Test name
Test status
Simulation time 707968218 ps
CPU time 1.09 seconds
Started Jun 05 05:14:02 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 215020 kb
Host smart-cf0bbf89-df0e-47ab-bbcc-8c571b149d01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788267832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3788267832
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3257723605
Short name T91
Test name
Test status
Simulation time 46818701 ps
CPU time 0.75 seconds
Started Jun 05 05:13:18 PM PDT 24
Finished Jun 05 05:13:20 PM PDT 24
Peak memory 196032 kb
Host smart-cf0948e6-dbe3-43da-a4fc-02048407accb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257723605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3257723605
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1479965673
Short name T50
Test name
Test status
Simulation time 73257956 ps
CPU time 1.19 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 198016 kb
Host smart-58482df0-eb4f-4751-8995-cc0cf33516d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479965673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1479965673
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3713915196
Short name T41
Test name
Test status
Simulation time 25601633 ps
CPU time 0.58 seconds
Started Jun 05 05:14:26 PM PDT 24
Finished Jun 05 05:14:27 PM PDT 24
Peak memory 193896 kb
Host smart-88b72062-bbe8-49b1-be03-b81484e3bd5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713915196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3713915196
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.767699866
Short name T108
Test name
Test status
Simulation time 58311986 ps
CPU time 0.68 seconds
Started Jun 05 05:13:12 PM PDT 24
Finished Jun 05 05:13:13 PM PDT 24
Peak memory 195356 kb
Host smart-87581c87-3258-4571-be75-53a199feb07d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767699866 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.767699866
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3968733240
Short name T48
Test name
Test status
Simulation time 355698491 ps
CPU time 0.95 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 197924 kb
Host smart-37a0132c-7aa6-4598-917b-020c5dbab6e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968733240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3968733240
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.4110175605
Short name T47
Test name
Test status
Simulation time 95199800 ps
CPU time 1.45 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 198008 kb
Host smart-f01615ec-f41b-4274-8034-61341a64158a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110175605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.4110175605
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3648321980
Short name T90
Test name
Test status
Simulation time 24632572 ps
CPU time 0.79 seconds
Started Jun 05 05:13:08 PM PDT 24
Finished Jun 05 05:13:09 PM PDT 24
Peak memory 195788 kb
Host smart-3a331cf4-2c2f-4679-922c-61028008d05f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648321980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3648321980
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1469476948
Short name T102
Test name
Test status
Simulation time 257696244 ps
CPU time 3.38 seconds
Started Jun 05 05:13:14 PM PDT 24
Finished Jun 05 05:13:18 PM PDT 24
Peak memory 197908 kb
Host smart-8e52d551-efd8-461f-a4e2-9e10fc92ffe6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469476948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1469476948
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3320239251
Short name T833
Test name
Test status
Simulation time 27546446 ps
CPU time 0.66 seconds
Started Jun 05 05:13:09 PM PDT 24
Finished Jun 05 05:13:10 PM PDT 24
Peak memory 195288 kb
Host smart-bbd1acd4-bb94-4abe-808e-0eaf077f94ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320239251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3320239251
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1187874273
Short name T810
Test name
Test status
Simulation time 42263716 ps
CPU time 1.01 seconds
Started Jun 05 05:13:07 PM PDT 24
Finished Jun 05 05:13:08 PM PDT 24
Peak memory 197996 kb
Host smart-0d1ebf5f-d95e-42fb-90e5-6a00a54ffed6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187874273 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1187874273
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.620039412
Short name T100
Test name
Test status
Simulation time 13144251 ps
CPU time 0.64 seconds
Started Jun 05 05:13:06 PM PDT 24
Finished Jun 05 05:13:07 PM PDT 24
Peak memory 194328 kb
Host smart-67bb4ac7-baf3-40a4-90a3-5a024da5d9e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620039412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.620039412
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.4010180385
Short name T814
Test name
Test status
Simulation time 18263585 ps
CPU time 0.57 seconds
Started Jun 05 05:13:08 PM PDT 24
Finished Jun 05 05:13:09 PM PDT 24
Peak memory 193648 kb
Host smart-71210b2a-24b1-4c52-962c-aa927f3a072b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010180385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.4010180385
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4269966914
Short name T757
Test name
Test status
Simulation time 133217816 ps
CPU time 2.75 seconds
Started Jun 05 05:13:10 PM PDT 24
Finished Jun 05 05:13:13 PM PDT 24
Peak memory 198012 kb
Host smart-b1622268-5cff-4446-a152-a9dd6beabf5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269966914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.4269966914
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.158115711
Short name T787
Test name
Test status
Simulation time 857771382 ps
CPU time 1.49 seconds
Started Jun 05 05:13:12 PM PDT 24
Finished Jun 05 05:13:14 PM PDT 24
Peak memory 197964 kb
Host smart-b6e6cebc-a095-42f8-af38-58b8d6145fd4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158115711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.158115711
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1227055724
Short name T97
Test name
Test status
Simulation time 39888396 ps
CPU time 0.85 seconds
Started Jun 05 05:13:13 PM PDT 24
Finished Jun 05 05:13:14 PM PDT 24
Peak memory 195868 kb
Host smart-948bddbb-4880-4bed-953a-1b7b92dc4510
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227055724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1227055724
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3581931858
Short name T827
Test name
Test status
Simulation time 2789254329 ps
CPU time 2.51 seconds
Started Jun 05 05:13:11 PM PDT 24
Finished Jun 05 05:13:14 PM PDT 24
Peak memory 197980 kb
Host smart-00d9f8d0-c04d-4394-bf5e-4b29801c5f10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581931858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3581931858
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.916992410
Short name T94
Test name
Test status
Simulation time 30314294 ps
CPU time 0.67 seconds
Started Jun 05 05:13:14 PM PDT 24
Finished Jun 05 05:13:15 PM PDT 24
Peak memory 194800 kb
Host smart-efcaba8e-3563-485c-984a-090fe07e1eb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916992410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.916992410
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1079382124
Short name T792
Test name
Test status
Simulation time 82034750 ps
CPU time 1.18 seconds
Started Jun 05 05:13:14 PM PDT 24
Finished Jun 05 05:13:16 PM PDT 24
Peak memory 198048 kb
Host smart-05181e52-c19f-44a2-a27e-3761c9550345
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079382124 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1079382124
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3728974983
Short name T92
Test name
Test status
Simulation time 12835769 ps
CPU time 0.62 seconds
Started Jun 05 05:13:13 PM PDT 24
Finished Jun 05 05:13:14 PM PDT 24
Peak memory 193532 kb
Host smart-22020d80-2c4d-4aa6-8c70-53d214a2d594
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728974983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3728974983
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.220348295
Short name T733
Test name
Test status
Simulation time 36409386 ps
CPU time 0.57 seconds
Started Jun 05 05:13:12 PM PDT 24
Finished Jun 05 05:13:14 PM PDT 24
Peak memory 194308 kb
Host smart-10cc0eb0-4770-4ec7-8116-7f71dbe467f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220348295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.220348295
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1547752598
Short name T89
Test name
Test status
Simulation time 111795484 ps
CPU time 0.75 seconds
Started Jun 05 05:13:12 PM PDT 24
Finished Jun 05 05:13:14 PM PDT 24
Peak memory 196908 kb
Host smart-065cc21b-be5e-4f16-8f01-f90ec5b6695d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547752598 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1547752598
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3145774488
Short name T767
Test name
Test status
Simulation time 23797914 ps
CPU time 1.15 seconds
Started Jun 05 05:13:13 PM PDT 24
Finished Jun 05 05:13:15 PM PDT 24
Peak memory 198044 kb
Host smart-05f05648-ae23-4728-aa56-25595e575cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145774488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3145774488
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.871576976
Short name T43
Test name
Test status
Simulation time 129126054 ps
CPU time 1 seconds
Started Jun 05 05:13:11 PM PDT 24
Finished Jun 05 05:13:13 PM PDT 24
Peak memory 197300 kb
Host smart-0d517a91-bb02-4530-9c0c-7f27526917d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871576976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.871576976
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1695135685
Short name T768
Test name
Test status
Simulation time 97683587 ps
CPU time 1.3 seconds
Started Jun 05 05:13:33 PM PDT 24
Finished Jun 05 05:13:35 PM PDT 24
Peak memory 198032 kb
Host smart-cac7991f-ffa4-411b-908b-75412f0f17aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695135685 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1695135685
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3190662030
Short name T819
Test name
Test status
Simulation time 86139814 ps
CPU time 0.62 seconds
Started Jun 05 05:13:35 PM PDT 24
Finished Jun 05 05:13:36 PM PDT 24
Peak memory 194592 kb
Host smart-6c82ddce-b770-49ec-920b-f3027b52eb30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190662030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3190662030
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1339197961
Short name T737
Test name
Test status
Simulation time 13666162 ps
CPU time 0.6 seconds
Started Jun 05 05:13:36 PM PDT 24
Finished Jun 05 05:13:37 PM PDT 24
Peak memory 193652 kb
Host smart-681a1745-9b31-4cf3-b35b-6024b33945d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339197961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1339197961
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1568986403
Short name T111
Test name
Test status
Simulation time 77986581 ps
CPU time 0.92 seconds
Started Jun 05 05:13:34 PM PDT 24
Finished Jun 05 05:13:36 PM PDT 24
Peak memory 197656 kb
Host smart-b66cc2aa-d1cf-4dd4-acc0-a64c86e84c72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568986403 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1568986403
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1295805752
Short name T839
Test name
Test status
Simulation time 69634156 ps
CPU time 1.91 seconds
Started Jun 05 05:13:35 PM PDT 24
Finished Jun 05 05:13:38 PM PDT 24
Peak memory 197996 kb
Host smart-d41ee5d0-c14d-464b-9ff3-3ac15348b8bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295805752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1295805752
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1407491022
Short name T35
Test name
Test status
Simulation time 261637521 ps
CPU time 0.9 seconds
Started Jun 05 05:13:35 PM PDT 24
Finished Jun 05 05:13:37 PM PDT 24
Peak memory 197016 kb
Host smart-c4795e2a-896d-4c69-a61e-4bab52773725
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407491022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1407491022
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3668695964
Short name T725
Test name
Test status
Simulation time 45832011 ps
CPU time 1.05 seconds
Started Jun 05 05:13:42 PM PDT 24
Finished Jun 05 05:13:44 PM PDT 24
Peak memory 197904 kb
Host smart-474c4ce9-9a8f-443b-af72-2b8fe35c3e82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668695964 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3668695964
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.919948005
Short name T95
Test name
Test status
Simulation time 13172232 ps
CPU time 0.63 seconds
Started Jun 05 05:13:47 PM PDT 24
Finished Jun 05 05:13:48 PM PDT 24
Peak memory 195212 kb
Host smart-944244c3-f26c-4566-93d4-1e721ab75909
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919948005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.919948005
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3987438020
Short name T807
Test name
Test status
Simulation time 32140890 ps
CPU time 0.56 seconds
Started Jun 05 05:13:42 PM PDT 24
Finished Jun 05 05:13:44 PM PDT 24
Peak memory 193656 kb
Host smart-e34987b0-5ec4-4a6b-8488-83cb73ed9e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987438020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3987438020
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1388632692
Short name T106
Test name
Test status
Simulation time 24371454 ps
CPU time 0.64 seconds
Started Jun 05 05:13:43 PM PDT 24
Finished Jun 05 05:13:44 PM PDT 24
Peak memory 194788 kb
Host smart-21019d60-3771-41fc-abab-4b3fa455ac54
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388632692 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1388632692
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3116128350
Short name T719
Test name
Test status
Simulation time 109821330 ps
CPU time 2.42 seconds
Started Jun 05 05:13:42 PM PDT 24
Finished Jun 05 05:13:46 PM PDT 24
Peak memory 197984 kb
Host smart-dc0aef2e-fc50-4732-9634-cafde4dae85b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116128350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3116128350
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3264384460
Short name T51
Test name
Test status
Simulation time 75109256 ps
CPU time 1.19 seconds
Started Jun 05 05:13:42 PM PDT 24
Finished Jun 05 05:13:43 PM PDT 24
Peak memory 198020 kb
Host smart-92c5d026-8eb7-4488-9060-9516c6d79000
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264384460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3264384460
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1937905087
Short name T812
Test name
Test status
Simulation time 23164266 ps
CPU time 0.8 seconds
Started Jun 05 05:13:42 PM PDT 24
Finished Jun 05 05:13:43 PM PDT 24
Peak memory 197928 kb
Host smart-28a67930-4ba6-4fc9-9b58-9472a2f287dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937905087 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1937905087
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1711803280
Short name T794
Test name
Test status
Simulation time 12534719 ps
CPU time 0.64 seconds
Started Jun 05 05:13:43 PM PDT 24
Finished Jun 05 05:13:44 PM PDT 24
Peak memory 195540 kb
Host smart-edaa02f0-42ee-4fb7-9192-7d58100680d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711803280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1711803280
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1562281489
Short name T720
Test name
Test status
Simulation time 77055327 ps
CPU time 0.58 seconds
Started Jun 05 05:13:44 PM PDT 24
Finished Jun 05 05:13:45 PM PDT 24
Peak memory 193596 kb
Host smart-653e524b-b177-488a-ba28-af1c58f59f27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562281489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1562281489
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.365776115
Short name T826
Test name
Test status
Simulation time 45453359 ps
CPU time 0.71 seconds
Started Jun 05 05:13:42 PM PDT 24
Finished Jun 05 05:13:44 PM PDT 24
Peak memory 195164 kb
Host smart-8367fe85-f501-4956-bc77-8ab5450139a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365776115 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.365776115
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2780670460
Short name T760
Test name
Test status
Simulation time 470973570 ps
CPU time 2.18 seconds
Started Jun 05 05:13:47 PM PDT 24
Finished Jun 05 05:13:50 PM PDT 24
Peak memory 198076 kb
Host smart-03c56c40-2db2-42e4-9230-11ba3be60b85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780670460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2780670460
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.450465139
Short name T804
Test name
Test status
Simulation time 104080571 ps
CPU time 1.4 seconds
Started Jun 05 05:13:42 PM PDT 24
Finished Jun 05 05:13:45 PM PDT 24
Peak memory 198028 kb
Host smart-0d6af325-8c15-4db7-98c2-2a4ee480505a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450465139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.450465139
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1385133376
Short name T815
Test name
Test status
Simulation time 17190407 ps
CPU time 0.91 seconds
Started Jun 05 05:13:44 PM PDT 24
Finished Jun 05 05:13:45 PM PDT 24
Peak memory 197884 kb
Host smart-31d3c4a7-9f6a-4e2d-a090-65d4bf0a5f21
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385133376 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1385133376
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.933093120
Short name T99
Test name
Test status
Simulation time 11167908 ps
CPU time 0.61 seconds
Started Jun 05 05:13:46 PM PDT 24
Finished Jun 05 05:13:47 PM PDT 24
Peak memory 194624 kb
Host smart-dde57993-66b1-4591-9247-7fda02996593
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933093120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.933093120
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.813022883
Short name T736
Test name
Test status
Simulation time 18588370 ps
CPU time 0.63 seconds
Started Jun 05 05:13:53 PM PDT 24
Finished Jun 05 05:13:54 PM PDT 24
Peak memory 193728 kb
Host smart-808bc250-7360-4c23-98d5-d943da30922d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813022883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.813022883
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2800332284
Short name T783
Test name
Test status
Simulation time 19290787 ps
CPU time 0.68 seconds
Started Jun 05 05:13:43 PM PDT 24
Finished Jun 05 05:13:45 PM PDT 24
Peak memory 194840 kb
Host smart-a0473c34-f719-4300-99d5-4b7317d01f9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800332284 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2800332284
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2332701502
Short name T800
Test name
Test status
Simulation time 19333703 ps
CPU time 0.99 seconds
Started Jun 05 05:13:43 PM PDT 24
Finished Jun 05 05:13:45 PM PDT 24
Peak memory 197936 kb
Host smart-33cae0be-1058-46ad-a85c-fe532b44fbd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332701502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2332701502
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.607823240
Short name T36
Test name
Test status
Simulation time 144675567 ps
CPU time 1.45 seconds
Started Jun 05 05:13:41 PM PDT 24
Finished Jun 05 05:13:43 PM PDT 24
Peak memory 198004 kb
Host smart-beb44afa-5ffd-4ac5-8daf-7a13012581ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607823240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.607823240
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3409256628
Short name T801
Test name
Test status
Simulation time 32671439 ps
CPU time 1.41 seconds
Started Jun 05 05:13:52 PM PDT 24
Finished Jun 05 05:13:55 PM PDT 24
Peak memory 197992 kb
Host smart-9f446e74-38a5-4361-b37e-1363cbbd95de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409256628 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3409256628
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4150391375
Short name T96
Test name
Test status
Simulation time 33760359 ps
CPU time 0.58 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 193972 kb
Host smart-b1129ce4-2203-4e7e-9398-7cff216c005a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150391375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.4150391375
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4244132342
Short name T820
Test name
Test status
Simulation time 44277711 ps
CPU time 0.57 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 193644 kb
Host smart-46bd18c3-49c7-4e04-95d4-a9c686b69158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244132342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4244132342
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.827986462
Short name T790
Test name
Test status
Simulation time 36626175 ps
CPU time 0.67 seconds
Started Jun 05 05:13:53 PM PDT 24
Finished Jun 05 05:13:55 PM PDT 24
Peak memory 195072 kb
Host smart-cd083eec-48ed-4d16-bb8a-4f9601ccc38b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827986462 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.827986462
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2396945295
Short name T739
Test name
Test status
Simulation time 41994854 ps
CPU time 2.24 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 198032 kb
Host smart-919de082-a6db-447d-8e1b-1d8db52abaa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396945295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2396945295
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2325951718
Short name T762
Test name
Test status
Simulation time 20194325 ps
CPU time 0.83 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:56 PM PDT 24
Peak memory 197788 kb
Host smart-c6e4abd9-a20c-4b8f-b73a-cc4611cdf7bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325951718 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2325951718
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3683759357
Short name T741
Test name
Test status
Simulation time 16672593 ps
CPU time 0.59 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:55 PM PDT 24
Peak memory 194748 kb
Host smart-7dd7bb22-f779-48fb-8d12-5f916d9bbb88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683759357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3683759357
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4041343752
Short name T724
Test name
Test status
Simulation time 14636619 ps
CPU time 0.65 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 193720 kb
Host smart-ab391d52-40c3-481b-babf-8bd344ed93c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041343752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4041343752
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1463775124
Short name T105
Test name
Test status
Simulation time 14278578 ps
CPU time 0.67 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:55 PM PDT 24
Peak memory 194796 kb
Host smart-9666d83b-2ea1-408b-8418-11b6c6f72254
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463775124 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1463775124
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.833532497
Short name T774
Test name
Test status
Simulation time 285802819 ps
CPU time 1.5 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:56 PM PDT 24
Peak memory 197936 kb
Host smart-9da603eb-a82f-4349-a607-c47369035d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833532497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.833532497
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3534789495
Short name T797
Test name
Test status
Simulation time 382078640 ps
CPU time 1.4 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 198024 kb
Host smart-3f7dc2d5-7efc-4296-8c1e-c8822d67dd1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534789495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3534789495
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2659033691
Short name T740
Test name
Test status
Simulation time 212366185 ps
CPU time 1.03 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 197996 kb
Host smart-b527984b-1789-4d7e-85f1-84683fc45d4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659033691 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2659033691
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3512313101
Short name T764
Test name
Test status
Simulation time 14943218 ps
CPU time 0.64 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:55 PM PDT 24
Peak memory 195540 kb
Host smart-2b5b466c-0c80-44dd-80f9-2ef39ab63506
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512313101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3512313101
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.629486748
Short name T756
Test name
Test status
Simulation time 18795515 ps
CPU time 0.59 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:56 PM PDT 24
Peak memory 193660 kb
Host smart-9a5f1713-698c-41d3-816f-fa081f6077a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629486748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.629486748
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.748126520
Short name T109
Test name
Test status
Simulation time 65256584 ps
CPU time 0.65 seconds
Started Jun 05 05:13:53 PM PDT 24
Finished Jun 05 05:13:55 PM PDT 24
Peak memory 194624 kb
Host smart-7145bb8d-425f-463e-a6b8-4c1fbe538b94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748126520 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.748126520
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2805108817
Short name T755
Test name
Test status
Simulation time 89202025 ps
CPU time 1.85 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 198024 kb
Host smart-32672911-e2a8-41b9-952c-759e5ac8a79b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805108817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2805108817
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.92265753
Short name T46
Test name
Test status
Simulation time 265511981 ps
CPU time 1.12 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:56 PM PDT 24
Peak memory 197984 kb
Host smart-4524a988-fd5c-488b-a261-883f69c282ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92265753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.gpio_tl_intg_err.92265753
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.734063618
Short name T806
Test name
Test status
Simulation time 64620622 ps
CPU time 1.59 seconds
Started Jun 05 05:13:53 PM PDT 24
Finished Jun 05 05:13:55 PM PDT 24
Peak memory 198128 kb
Host smart-b2642a22-22eb-4f65-802c-66c1ddfccb28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734063618 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.734063618
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4276071182
Short name T780
Test name
Test status
Simulation time 25813938 ps
CPU time 0.68 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 194968 kb
Host smart-1ffdeac8-7234-4ab9-87b1-15c5765b3891
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276071182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.4276071182
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3017242181
Short name T776
Test name
Test status
Simulation time 23043504 ps
CPU time 0.61 seconds
Started Jun 05 05:13:57 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 193736 kb
Host smart-8a4e34bb-3b3b-4db5-ba0a-b3de7951a540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017242181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3017242181
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1156228297
Short name T103
Test name
Test status
Simulation time 106279887 ps
CPU time 0.8 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 195976 kb
Host smart-88e7c2ef-f7d5-4ae4-a000-5dff42644967
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156228297 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1156228297
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3218323535
Short name T777
Test name
Test status
Simulation time 275738430 ps
CPU time 3.44 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 198072 kb
Host smart-c0b76797-27df-4da7-91a8-583e76605ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218323535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3218323535
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.720579881
Short name T751
Test name
Test status
Simulation time 31287287 ps
CPU time 0.86 seconds
Started Jun 05 05:13:57 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 197960 kb
Host smart-3d0c9881-984f-4673-aa23-663300a460a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720579881 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.720579881
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2423262667
Short name T88
Test name
Test status
Simulation time 86799500 ps
CPU time 0.64 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 194876 kb
Host smart-f435c74f-9c19-4423-a9b4-ffada47ebfdd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423262667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2423262667
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3609589118
Short name T728
Test name
Test status
Simulation time 142187209 ps
CPU time 0.59 seconds
Started Jun 05 05:13:58 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 193692 kb
Host smart-42cec280-54cd-4657-bc0a-eebe7f7a4711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609589118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3609589118
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3829190942
Short name T831
Test name
Test status
Simulation time 41166386 ps
CPU time 0.91 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 196124 kb
Host smart-bcb949ea-e369-4113-adf4-126d22ec0884
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829190942 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3829190942
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.993281435
Short name T732
Test name
Test status
Simulation time 460397780 ps
CPU time 2.34 seconds
Started Jun 05 05:13:57 PM PDT 24
Finished Jun 05 05:14:01 PM PDT 24
Peak memory 198060 kb
Host smart-d9a49ef1-86c6-4ccc-994e-3ec0d621e155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993281435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.993281435
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3994458475
Short name T834
Test name
Test status
Simulation time 50500359 ps
CPU time 0.98 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 197840 kb
Host smart-f41d373d-d1e3-4003-bdab-5a505ad2f512
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994458475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3994458475
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.176535718
Short name T817
Test name
Test status
Simulation time 20322101 ps
CPU time 0.73 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 196928 kb
Host smart-dc7fc34d-894e-466f-afa4-9841aa30104a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176535718 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.176535718
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1063041559
Short name T98
Test name
Test status
Simulation time 35867229 ps
CPU time 0.63 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 194800 kb
Host smart-17577205-fe66-4aa2-8156-58a57abde2b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063041559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1063041559
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.555190770
Short name T838
Test name
Test status
Simulation time 21674534 ps
CPU time 0.6 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 193668 kb
Host smart-69a6a839-473d-4c09-8fac-aef53502885c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555190770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.555190770
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3749938988
Short name T786
Test name
Test status
Simulation time 125215823 ps
CPU time 0.82 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 196916 kb
Host smart-4c54c411-944c-4aae-b8f9-4b997e714cd5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749938988 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3749938988
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3967388046
Short name T802
Test name
Test status
Simulation time 286912648 ps
CPU time 1.75 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 198004 kb
Host smart-39af0456-9682-4c7e-b04c-00e0cfcb7b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967388046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3967388046
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1145088692
Short name T835
Test name
Test status
Simulation time 136552045 ps
CPU time 1.4 seconds
Started Jun 05 05:13:20 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 196812 kb
Host smart-10ca1ac8-7136-431f-a837-df43d11e6eb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145088692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1145088692
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.775897449
Short name T93
Test name
Test status
Simulation time 15814901 ps
CPU time 0.65 seconds
Started Jun 05 05:13:23 PM PDT 24
Finished Jun 05 05:13:25 PM PDT 24
Peak memory 194968 kb
Host smart-eef06fd5-e3ed-4669-bb93-c4b30b5a1003
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775897449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.775897449
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.374024212
Short name T770
Test name
Test status
Simulation time 81057938 ps
CPU time 1.14 seconds
Started Jun 05 05:13:15 PM PDT 24
Finished Jun 05 05:13:16 PM PDT 24
Peak memory 198076 kb
Host smart-8e6410ef-0e82-4f3c-8595-7de26e1398c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374024212 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.374024212
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.4266888255
Short name T726
Test name
Test status
Simulation time 18375875 ps
CPU time 0.6 seconds
Started Jun 05 05:13:12 PM PDT 24
Finished Jun 05 05:13:13 PM PDT 24
Peak memory 193836 kb
Host smart-18b776d1-efeb-4754-ae87-f1dc01c91c4e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266888255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.4266888255
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.633864786
Short name T789
Test name
Test status
Simulation time 33326338 ps
CPU time 0.66 seconds
Started Jun 05 05:13:13 PM PDT 24
Finished Jun 05 05:13:14 PM PDT 24
Peak memory 193700 kb
Host smart-13a99f94-beea-4cca-905c-1d74aaa7e11d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633864786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.633864786
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2769275084
Short name T795
Test name
Test status
Simulation time 60760992 ps
CPU time 0.8 seconds
Started Jun 05 05:13:13 PM PDT 24
Finished Jun 05 05:13:14 PM PDT 24
Peak memory 196236 kb
Host smart-b63dc75f-457d-4ad1-846b-d4ed85dbb093
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769275084 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2769275084
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1063220339
Short name T766
Test name
Test status
Simulation time 389829290 ps
CPU time 2.3 seconds
Started Jun 05 05:13:12 PM PDT 24
Finished Jun 05 05:13:15 PM PDT 24
Peak memory 198140 kb
Host smart-31a15228-9859-4057-b05a-cf17e398e00b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063220339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1063220339
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3609887873
Short name T44
Test name
Test status
Simulation time 47519578 ps
CPU time 0.89 seconds
Started Jun 05 05:13:12 PM PDT 24
Finished Jun 05 05:13:13 PM PDT 24
Peak memory 196948 kb
Host smart-13cf5474-d402-46b4-8076-29eb1f659db6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609887873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3609887873
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1844253807
Short name T763
Test name
Test status
Simulation time 12336997 ps
CPU time 0.58 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 193652 kb
Host smart-1edc9514-2b54-4721-a127-272b3420a30c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844253807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1844253807
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.4200644626
Short name T721
Test name
Test status
Simulation time 24804390 ps
CPU time 0.64 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 193732 kb
Host smart-d74b4571-ef23-4b47-9709-eeeee8933ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200644626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.4200644626
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1796246563
Short name T825
Test name
Test status
Simulation time 27544386 ps
CPU time 0.64 seconds
Started Jun 05 05:13:57 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 193744 kb
Host smart-6e0b3dce-180c-4b15-b23f-fd8f69fe9212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796246563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1796246563
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2300259999
Short name T759
Test name
Test status
Simulation time 21732398 ps
CPU time 0.62 seconds
Started Jun 05 05:13:57 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 193696 kb
Host smart-8e2610bb-a935-48a4-accf-47d21ad92389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300259999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2300259999
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2403407081
Short name T788
Test name
Test status
Simulation time 44101446 ps
CPU time 0.6 seconds
Started Jun 05 05:13:57 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 193580 kb
Host smart-288ce13e-82e4-4080-a074-8691928f14c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403407081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2403407081
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2786428068
Short name T775
Test name
Test status
Simulation time 12806230 ps
CPU time 0.63 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 193588 kb
Host smart-7c25eeef-7b7a-4551-ba75-f8a53788b2ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786428068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2786428068
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3528929331
Short name T840
Test name
Test status
Simulation time 45170826 ps
CPU time 0.61 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 193680 kb
Host smart-7a919fbb-b91b-4176-a595-9490b9a3d7e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528929331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3528929331
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1708967986
Short name T772
Test name
Test status
Simulation time 14351483 ps
CPU time 0.6 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 193740 kb
Host smart-c4b9276f-c26b-4526-8f04-0e8b5aff5fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708967986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1708967986
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2088223389
Short name T745
Test name
Test status
Simulation time 133319115 ps
CPU time 0.6 seconds
Started Jun 05 05:13:57 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 193700 kb
Host smart-7fb6628d-e7e4-442f-893d-5d2b6d70eb80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088223389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2088223389
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1168297306
Short name T779
Test name
Test status
Simulation time 23132797 ps
CPU time 0.59 seconds
Started Jun 05 05:13:58 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 193808 kb
Host smart-6ad0c49e-8350-497c-8e1f-971f46893bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168297306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1168297306
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2286605006
Short name T828
Test name
Test status
Simulation time 110524736 ps
CPU time 0.82 seconds
Started Jun 05 05:13:21 PM PDT 24
Finished Jun 05 05:13:23 PM PDT 24
Peak memory 195936 kb
Host smart-fece6a13-fc63-4246-b988-9d05ae31606f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286605006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2286605006
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2126172767
Short name T750
Test name
Test status
Simulation time 97268947 ps
CPU time 1.49 seconds
Started Jun 05 05:13:22 PM PDT 24
Finished Jun 05 05:13:24 PM PDT 24
Peak memory 196568 kb
Host smart-b9f5fe3c-6731-49e9-b042-2f92cd4dd75b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126172767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2126172767
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.423824064
Short name T758
Test name
Test status
Simulation time 39754439 ps
CPU time 0.61 seconds
Started Jun 05 05:13:19 PM PDT 24
Finished Jun 05 05:13:20 PM PDT 24
Peak memory 194208 kb
Host smart-57a44b5c-6bf8-4a2d-91f6-d6c057963c88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423824064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.423824064
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.221200717
Short name T771
Test name
Test status
Simulation time 83484590 ps
CPU time 0.76 seconds
Started Jun 05 05:13:20 PM PDT 24
Finished Jun 05 05:13:21 PM PDT 24
Peak memory 197360 kb
Host smart-af59fe17-096e-482c-980d-804f64b7d16c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221200717 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.221200717
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2372034154
Short name T796
Test name
Test status
Simulation time 24653088 ps
CPU time 0.61 seconds
Started Jun 05 05:13:21 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 194520 kb
Host smart-9a6f26ee-b2fd-49c0-9287-bbb2b2a5098c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372034154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2372034154
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1495611162
Short name T723
Test name
Test status
Simulation time 51613102 ps
CPU time 0.58 seconds
Started Jun 05 05:13:19 PM PDT 24
Finished Jun 05 05:13:20 PM PDT 24
Peak memory 193676 kb
Host smart-2a45f29e-097d-4e82-b076-cdeaf5c5d937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495611162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1495611162
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.762244535
Short name T823
Test name
Test status
Simulation time 234726170 ps
CPU time 0.76 seconds
Started Jun 05 05:13:21 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 196228 kb
Host smart-108b1e78-54f5-4ad8-afe3-9fe19b19e9e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762244535 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.762244535
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3089999348
Short name T730
Test name
Test status
Simulation time 560924825 ps
CPU time 2.21 seconds
Started Jun 05 05:13:24 PM PDT 24
Finished Jun 05 05:13:26 PM PDT 24
Peak memory 198080 kb
Host smart-fabd1c26-5070-4486-9f25-edb8734ba71f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089999348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3089999348
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.324037338
Short name T837
Test name
Test status
Simulation time 220561783 ps
CPU time 1.42 seconds
Started Jun 05 05:13:20 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 198028 kb
Host smart-6099318d-961f-4e39-ba35-60250c4ad5f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324037338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.324037338
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2322704268
Short name T729
Test name
Test status
Simulation time 15581330 ps
CPU time 0.64 seconds
Started Jun 05 05:13:58 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 194500 kb
Host smart-7156058f-2b98-422f-a0c9-e157e5777b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322704268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2322704268
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2435442889
Short name T841
Test name
Test status
Simulation time 38284844 ps
CPU time 0.58 seconds
Started Jun 05 05:13:58 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 194320 kb
Host smart-79b0bf33-a2a3-4ec3-bc9b-cbfcb9576232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435442889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2435442889
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.951665295
Short name T811
Test name
Test status
Simulation time 23966563 ps
CPU time 0.61 seconds
Started Jun 05 05:13:59 PM PDT 24
Finished Jun 05 05:14:00 PM PDT 24
Peak memory 193712 kb
Host smart-afcc7aac-f85b-4629-91ec-f1f7f36b408d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951665295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.951665295
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3188876058
Short name T799
Test name
Test status
Simulation time 73525792 ps
CPU time 0.63 seconds
Started Jun 05 05:13:53 PM PDT 24
Finished Jun 05 05:13:54 PM PDT 24
Peak memory 193760 kb
Host smart-0aac01df-e039-41b0-ba27-5af3c617a5d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188876058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3188876058
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3471825529
Short name T743
Test name
Test status
Simulation time 58646416 ps
CPU time 0.62 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:55 PM PDT 24
Peak memory 193648 kb
Host smart-32790b34-03c3-473f-a603-01bbb598d85b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471825529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3471825529
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.190433629
Short name T798
Test name
Test status
Simulation time 49147675 ps
CPU time 0.63 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:56 PM PDT 24
Peak memory 193620 kb
Host smart-239bf42e-6a7b-4b78-9815-89066c90710d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190433629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.190433629
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1840154035
Short name T722
Test name
Test status
Simulation time 12220036 ps
CPU time 0.6 seconds
Started Jun 05 05:13:53 PM PDT 24
Finished Jun 05 05:13:55 PM PDT 24
Peak memory 193648 kb
Host smart-1c762b87-dc13-464b-932c-3e335450c379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840154035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1840154035
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2782119897
Short name T744
Test name
Test status
Simulation time 55926737 ps
CPU time 0.59 seconds
Started Jun 05 05:13:56 PM PDT 24
Finished Jun 05 05:13:58 PM PDT 24
Peak memory 193644 kb
Host smart-4a98b6a1-9802-4238-8ba3-a31fd976f256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782119897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2782119897
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3988522146
Short name T829
Test name
Test status
Simulation time 14360451 ps
CPU time 0.62 seconds
Started Jun 05 05:13:55 PM PDT 24
Finished Jun 05 05:13:57 PM PDT 24
Peak memory 193616 kb
Host smart-8ee3b097-c32d-41b8-a7c5-db9cbc9e7570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988522146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3988522146
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.229370323
Short name T718
Test name
Test status
Simulation time 33999262 ps
CPU time 0.64 seconds
Started Jun 05 05:13:54 PM PDT 24
Finished Jun 05 05:13:56 PM PDT 24
Peak memory 194372 kb
Host smart-11d0bf78-2f0d-4fb7-88db-c7160e1b7383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229370323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.229370323
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.659253361
Short name T816
Test name
Test status
Simulation time 72213593 ps
CPU time 0.67 seconds
Started Jun 05 05:13:23 PM PDT 24
Finished Jun 05 05:13:25 PM PDT 24
Peak memory 195360 kb
Host smart-8890ef0c-b2a7-4487-b0cb-1d87b6ceb73d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659253361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.659253361
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.865316316
Short name T113
Test name
Test status
Simulation time 73987882 ps
CPU time 2.25 seconds
Started Jun 05 05:13:23 PM PDT 24
Finished Jun 05 05:13:26 PM PDT 24
Peak memory 197900 kb
Host smart-6c7404d2-eddc-48a5-94a1-0e6c796455cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865316316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.865316316
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.864826098
Short name T742
Test name
Test status
Simulation time 46160454 ps
CPU time 0.64 seconds
Started Jun 05 05:13:21 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 194844 kb
Host smart-8df7d05c-8175-407c-a257-586b83e66896
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864826098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.864826098
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2412862291
Short name T781
Test name
Test status
Simulation time 234206934 ps
CPU time 0.91 seconds
Started Jun 05 05:13:24 PM PDT 24
Finished Jun 05 05:13:25 PM PDT 24
Peak memory 197984 kb
Host smart-896c3f6c-05c9-4631-8d7f-42199296d2a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412862291 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2412862291
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2409403351
Short name T778
Test name
Test status
Simulation time 14928334 ps
CPU time 0.61 seconds
Started Jun 05 05:13:21 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 194468 kb
Host smart-4b4e274b-ac57-42f7-8e08-6e0cae0b812b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409403351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2409403351
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.13607680
Short name T754
Test name
Test status
Simulation time 36822424 ps
CPU time 0.59 seconds
Started Jun 05 05:13:23 PM PDT 24
Finished Jun 05 05:13:24 PM PDT 24
Peak memory 193676 kb
Host smart-654e5766-fcb4-4dfa-9689-354e4364ce28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13607680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.13607680
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1313729459
Short name T784
Test name
Test status
Simulation time 25899448 ps
CPU time 0.74 seconds
Started Jun 05 05:13:20 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 196184 kb
Host smart-08dad4dd-c144-422a-9479-1d1308ff8ab1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313729459 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1313729459
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1556025298
Short name T748
Test name
Test status
Simulation time 98831061 ps
CPU time 2.68 seconds
Started Jun 05 05:13:22 PM PDT 24
Finished Jun 05 05:13:25 PM PDT 24
Peak memory 197984 kb
Host smart-7eb09d56-9ca0-433c-97db-05fb24febbe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556025298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1556025298
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.572217531
Short name T832
Test name
Test status
Simulation time 377581533 ps
CPU time 1.17 seconds
Started Jun 05 05:13:24 PM PDT 24
Finished Jun 05 05:13:25 PM PDT 24
Peak memory 198068 kb
Host smart-97a6271d-b2d8-48ba-943b-82fabce4147f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572217531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.572217531
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.324228494
Short name T735
Test name
Test status
Simulation time 16191824 ps
CPU time 0.63 seconds
Started Jun 05 05:13:57 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 193752 kb
Host smart-d2f0cf5b-b655-4012-a45c-ef430ba3dad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324228494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.324228494
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.95823729
Short name T830
Test name
Test status
Simulation time 20787314 ps
CPU time 0.61 seconds
Started Jun 05 05:13:53 PM PDT 24
Finished Jun 05 05:13:55 PM PDT 24
Peak memory 193688 kb
Host smart-461d523c-6c91-41b1-b394-a745a0666e2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95823729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.95823729
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.164996750
Short name T782
Test name
Test status
Simulation time 57738242 ps
CPU time 0.6 seconds
Started Jun 05 05:13:53 PM PDT 24
Finished Jun 05 05:13:54 PM PDT 24
Peak memory 194328 kb
Host smart-41bcd0fc-40cf-45fd-af61-ebd8b5bf8982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164996750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.164996750
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2737713987
Short name T727
Test name
Test status
Simulation time 52138976 ps
CPU time 0.61 seconds
Started Jun 05 05:14:01 PM PDT 24
Finished Jun 05 05:14:02 PM PDT 24
Peak memory 193656 kb
Host smart-3822c2d1-e127-4c8d-b646-de3b87c513f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737713987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2737713987
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2820445078
Short name T769
Test name
Test status
Simulation time 175661936 ps
CPU time 0.66 seconds
Started Jun 05 05:14:02 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 194576 kb
Host smart-433250fc-d667-419b-981c-028458d03fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820445078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2820445078
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.820535141
Short name T752
Test name
Test status
Simulation time 35720287 ps
CPU time 0.64 seconds
Started Jun 05 05:14:03 PM PDT 24
Finished Jun 05 05:14:05 PM PDT 24
Peak memory 194400 kb
Host smart-a89fbea9-ea78-42e2-a5f9-4b9964f5c079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820535141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.820535141
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1371540169
Short name T734
Test name
Test status
Simulation time 20001470 ps
CPU time 0.64 seconds
Started Jun 05 05:14:03 PM PDT 24
Finished Jun 05 05:14:05 PM PDT 24
Peak memory 194416 kb
Host smart-8715f241-7a5c-48e2-bbde-8122ef245f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371540169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1371540169
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4035621316
Short name T717
Test name
Test status
Simulation time 41273267 ps
CPU time 0.61 seconds
Started Jun 05 05:14:02 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 193652 kb
Host smart-cb8049d2-2ef6-4b43-aa00-1c0fd391b38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035621316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4035621316
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2395678234
Short name T785
Test name
Test status
Simulation time 13747076 ps
CPU time 0.6 seconds
Started Jun 05 05:14:03 PM PDT 24
Finished Jun 05 05:14:04 PM PDT 24
Peak memory 193632 kb
Host smart-40829e18-cacc-4827-b585-85e78ea04a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395678234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2395678234
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.202615262
Short name T805
Test name
Test status
Simulation time 13533388 ps
CPU time 0.6 seconds
Started Jun 05 05:14:02 PM PDT 24
Finished Jun 05 05:14:04 PM PDT 24
Peak memory 193676 kb
Host smart-7ef76836-5303-4843-a7c2-f75b880ae67b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202615262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.202615262
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1838523216
Short name T836
Test name
Test status
Simulation time 49818089 ps
CPU time 0.82 seconds
Started Jun 05 05:13:21 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 197984 kb
Host smart-22c0754b-f28a-4ebf-a3a5-5538b33537ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838523216 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1838523216
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.367034570
Short name T101
Test name
Test status
Simulation time 21803891 ps
CPU time 0.59 seconds
Started Jun 05 05:13:21 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 193572 kb
Host smart-44f8760c-a7c2-4129-ac93-5d0c5b229728
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367034570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.367034570
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.4066528208
Short name T753
Test name
Test status
Simulation time 11134476 ps
CPU time 0.61 seconds
Started Jun 05 05:13:23 PM PDT 24
Finished Jun 05 05:13:24 PM PDT 24
Peak memory 193764 kb
Host smart-72915c4d-40dc-44ac-b2df-0e8a60521371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066528208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.4066528208
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3700438379
Short name T107
Test name
Test status
Simulation time 40296472 ps
CPU time 0.83 seconds
Started Jun 05 05:13:21 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 196216 kb
Host smart-58249863-abbf-49a2-b3fe-4ae7e905f975
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700438379 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3700438379
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2143916760
Short name T808
Test name
Test status
Simulation time 143726646 ps
CPU time 2.67 seconds
Started Jun 05 05:13:20 PM PDT 24
Finished Jun 05 05:13:23 PM PDT 24
Peak memory 197972 kb
Host smart-0fc07f34-b6e5-4028-b684-f4a2f78b12e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143916760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2143916760
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2925219725
Short name T49
Test name
Test status
Simulation time 165996478 ps
CPU time 1.11 seconds
Started Jun 05 05:13:21 PM PDT 24
Finished Jun 05 05:13:22 PM PDT 24
Peak memory 198004 kb
Host smart-d02ae18f-e376-4f9f-968f-2f0140c369d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925219725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2925219725
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2719838430
Short name T824
Test name
Test status
Simulation time 33408869 ps
CPU time 1.51 seconds
Started Jun 05 05:13:34 PM PDT 24
Finished Jun 05 05:13:36 PM PDT 24
Peak memory 198128 kb
Host smart-8202f2c2-8dc8-446b-891f-7259b209ca4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719838430 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2719838430
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.4289281779
Short name T822
Test name
Test status
Simulation time 36956290 ps
CPU time 0.62 seconds
Started Jun 05 05:13:28 PM PDT 24
Finished Jun 05 05:13:29 PM PDT 24
Peak memory 193280 kb
Host smart-670f571b-8934-491a-9adf-2b660f3be941
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289281779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.4289281779
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2498848717
Short name T813
Test name
Test status
Simulation time 25684533 ps
CPU time 0.64 seconds
Started Jun 05 05:13:32 PM PDT 24
Finished Jun 05 05:13:33 PM PDT 24
Peak memory 193756 kb
Host smart-509f4904-4c1d-40dd-b836-28204c88ed75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498848717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2498848717
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1758576
Short name T104
Test name
Test status
Simulation time 52596307 ps
CPU time 0.76 seconds
Started Jun 05 05:13:28 PM PDT 24
Finished Jun 05 05:13:29 PM PDT 24
Peak memory 195932 kb
Host smart-2e6f702f-ff3f-4d40-8600-749de8c95a77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758576 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.gpio_same_csr_outstanding.1758576
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2513687599
Short name T761
Test name
Test status
Simulation time 1294495294 ps
CPU time 3.24 seconds
Started Jun 05 05:13:28 PM PDT 24
Finished Jun 05 05:13:32 PM PDT 24
Peak memory 198036 kb
Host smart-5cbb9aea-6eef-41b7-89c5-c87085ce0fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513687599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2513687599
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1923279246
Short name T45
Test name
Test status
Simulation time 82946460 ps
CPU time 1.16 seconds
Started Jun 05 05:13:27 PM PDT 24
Finished Jun 05 05:13:29 PM PDT 24
Peak memory 198028 kb
Host smart-92da0bcc-b26f-45cc-9e94-581032cd40d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923279246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1923279246
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2426731994
Short name T738
Test name
Test status
Simulation time 147007105 ps
CPU time 1 seconds
Started Jun 05 05:13:28 PM PDT 24
Finished Jun 05 05:13:29 PM PDT 24
Peak memory 197788 kb
Host smart-091ad6be-e1f3-472e-bda9-eb6afa6c8952
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426731994 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2426731994
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1683263198
Short name T818
Test name
Test status
Simulation time 21907779 ps
CPU time 0.62 seconds
Started Jun 05 05:13:29 PM PDT 24
Finished Jun 05 05:13:30 PM PDT 24
Peak memory 194956 kb
Host smart-3d2c39e7-478c-4c66-8f48-fcef3c33ed6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683263198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1683263198
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1678090828
Short name T747
Test name
Test status
Simulation time 27345157 ps
CPU time 0.61 seconds
Started Jun 05 05:13:28 PM PDT 24
Finished Jun 05 05:13:29 PM PDT 24
Peak memory 194320 kb
Host smart-b1e2e69b-2fba-448b-a5a2-f46dbade6b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678090828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1678090828
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.61288019
Short name T791
Test name
Test status
Simulation time 21498760 ps
CPU time 0.72 seconds
Started Jun 05 05:13:29 PM PDT 24
Finished Jun 05 05:13:30 PM PDT 24
Peak memory 194792 kb
Host smart-b9f6d0ec-da47-46e0-a425-b21f95c230ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61288019 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.gpio_same_csr_outstanding.61288019
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3400150129
Short name T809
Test name
Test status
Simulation time 18796804 ps
CPU time 0.93 seconds
Started Jun 05 05:13:27 PM PDT 24
Finished Jun 05 05:13:29 PM PDT 24
Peak memory 197948 kb
Host smart-248bd520-1831-4f0b-8c2e-65dbd7019638
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400150129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3400150129
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1044001038
Short name T37
Test name
Test status
Simulation time 78072284 ps
CPU time 1.23 seconds
Started Jun 05 05:13:29 PM PDT 24
Finished Jun 05 05:13:31 PM PDT 24
Peak memory 197576 kb
Host smart-fbd564ea-8de5-412d-917b-2c3a0b562ea1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044001038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1044001038
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.584378507
Short name T803
Test name
Test status
Simulation time 33130909 ps
CPU time 0.76 seconds
Started Jun 05 05:13:36 PM PDT 24
Finished Jun 05 05:13:37 PM PDT 24
Peak memory 197952 kb
Host smart-391abc07-768c-4211-b3bb-b4784827e424
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584378507 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.584378507
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3820597670
Short name T112
Test name
Test status
Simulation time 12976908 ps
CPU time 0.6 seconds
Started Jun 05 05:13:29 PM PDT 24
Finished Jun 05 05:13:30 PM PDT 24
Peak memory 194608 kb
Host smart-c16af873-47c7-4d14-b6a3-f80b78a6adbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820597670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3820597670
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1599892601
Short name T749
Test name
Test status
Simulation time 12932401 ps
CPU time 0.62 seconds
Started Jun 05 05:13:35 PM PDT 24
Finished Jun 05 05:13:36 PM PDT 24
Peak memory 194336 kb
Host smart-678e6d07-543d-443e-8127-228824c6bab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599892601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1599892601
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3074880172
Short name T110
Test name
Test status
Simulation time 160880964 ps
CPU time 0.75 seconds
Started Jun 05 05:13:27 PM PDT 24
Finished Jun 05 05:13:28 PM PDT 24
Peak memory 195832 kb
Host smart-07359e5b-a4f1-4e59-91ad-e27204595dc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074880172 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3074880172
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2061576071
Short name T773
Test name
Test status
Simulation time 49501931 ps
CPU time 2.65 seconds
Started Jun 05 05:13:34 PM PDT 24
Finished Jun 05 05:13:38 PM PDT 24
Peak memory 198012 kb
Host smart-285f608a-20ec-408f-b8c4-00705941b748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061576071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2061576071
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1702648927
Short name T34
Test name
Test status
Simulation time 90009517 ps
CPU time 0.9 seconds
Started Jun 05 05:13:34 PM PDT 24
Finished Jun 05 05:13:35 PM PDT 24
Peak memory 197340 kb
Host smart-9f46ad83-74b2-4997-b671-70733a19fe40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702648927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1702648927
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.923334367
Short name T746
Test name
Test status
Simulation time 32058145 ps
CPU time 1.59 seconds
Started Jun 05 05:13:33 PM PDT 24
Finished Jun 05 05:13:35 PM PDT 24
Peak memory 198128 kb
Host smart-0bdcb462-9e3e-4e0f-9755-a054ec90b20b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923334367 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.923334367
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3532596284
Short name T765
Test name
Test status
Simulation time 21817681 ps
CPU time 0.64 seconds
Started Jun 05 05:13:37 PM PDT 24
Finished Jun 05 05:13:38 PM PDT 24
Peak memory 194896 kb
Host smart-c0a6bba6-b8f5-468a-8f74-7a11380c60ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532596284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3532596284
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.284815540
Short name T821
Test name
Test status
Simulation time 22641042 ps
CPU time 0.63 seconds
Started Jun 05 05:13:35 PM PDT 24
Finished Jun 05 05:13:36 PM PDT 24
Peak memory 193868 kb
Host smart-05eb8e89-b3f0-4ac6-b982-db6773c18ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284815540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.284815540
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.975033813
Short name T793
Test name
Test status
Simulation time 158853195 ps
CPU time 0.77 seconds
Started Jun 05 05:13:33 PM PDT 24
Finished Jun 05 05:13:34 PM PDT 24
Peak memory 196168 kb
Host smart-228cb752-1c2c-4b88-8578-3d8d3fb5c369
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975033813 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.975033813
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.811392140
Short name T731
Test name
Test status
Simulation time 214620461 ps
CPU time 2.13 seconds
Started Jun 05 05:13:35 PM PDT 24
Finished Jun 05 05:13:37 PM PDT 24
Peak memory 198072 kb
Host smart-7612a357-e902-4f47-9da8-7b8744c09632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811392140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.811392140
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3665395644
Short name T114
Test name
Test status
Simulation time 41231423 ps
CPU time 0.84 seconds
Started Jun 05 05:13:33 PM PDT 24
Finished Jun 05 05:13:35 PM PDT 24
Peak memory 197936 kb
Host smart-38276e40-6d0d-4a20-8e4e-0b849a7ed4be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665395644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3665395644
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.845948839
Short name T565
Test name
Test status
Simulation time 21131891 ps
CPU time 0.62 seconds
Started Jun 05 05:14:03 PM PDT 24
Finished Jun 05 05:14:05 PM PDT 24
Peak memory 193880 kb
Host smart-be9b57fc-48dc-4132-91fe-9334acb133b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845948839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.845948839
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2368463347
Short name T401
Test name
Test status
Simulation time 67062422 ps
CPU time 0.64 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:06 PM PDT 24
Peak memory 194064 kb
Host smart-12cc01ad-ddd2-46f9-ab1f-c14eb1d443fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368463347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2368463347
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.4256902143
Short name T536
Test name
Test status
Simulation time 1325495857 ps
CPU time 20.05 seconds
Started Jun 05 05:14:03 PM PDT 24
Finished Jun 05 05:14:23 PM PDT 24
Peak memory 196876 kb
Host smart-af940209-9aef-49fb-b1a7-b714739bc499
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256902143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.4256902143
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2291936019
Short name T528
Test name
Test status
Simulation time 63588229 ps
CPU time 0.91 seconds
Started Jun 05 05:14:01 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 197284 kb
Host smart-a987fab3-867b-413d-9adc-5d8499626eb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291936019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2291936019
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2221643400
Short name T556
Test name
Test status
Simulation time 103028908 ps
CPU time 1.15 seconds
Started Jun 05 05:14:03 PM PDT 24
Finished Jun 05 05:14:05 PM PDT 24
Peak memory 196848 kb
Host smart-b92b8ef1-fb0c-430d-bd57-5fb0c4dcb3ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221643400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2221643400
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1106173219
Short name T496
Test name
Test status
Simulation time 228071756 ps
CPU time 2.38 seconds
Started Jun 05 05:14:07 PM PDT 24
Finished Jun 05 05:14:10 PM PDT 24
Peak memory 197960 kb
Host smart-d4a33c7e-9bfc-4f76-839d-f806ed14bd51
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106173219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1106173219
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1218947415
Short name T165
Test name
Test status
Simulation time 79789445 ps
CPU time 2.29 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:07 PM PDT 24
Peak memory 197256 kb
Host smart-3422d92b-617d-46f7-bb46-53c1e9fb0dd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218947415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1218947415
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3911769036
Short name T183
Test name
Test status
Simulation time 92418323 ps
CPU time 1.08 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:07 PM PDT 24
Peak memory 196688 kb
Host smart-a12bc5af-a283-4d4d-83bf-68e2637fcca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911769036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3911769036
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2815402120
Short name T257
Test name
Test status
Simulation time 111413667 ps
CPU time 1.03 seconds
Started Jun 05 05:14:03 PM PDT 24
Finished Jun 05 05:14:04 PM PDT 24
Peak memory 195856 kb
Host smart-b7150c78-ea44-43fe-8543-8ea3d878c71a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815402120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2815402120
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.4035663369
Short name T629
Test name
Test status
Simulation time 41556730 ps
CPU time 1.38 seconds
Started Jun 05 05:14:01 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 198044 kb
Host smart-10f1579f-2b54-4ca2-9a66-f9b3ac1fe533
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035663369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.4035663369
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1800446313
Short name T40
Test name
Test status
Simulation time 546384354 ps
CPU time 0.86 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:06 PM PDT 24
Peak memory 214000 kb
Host smart-820ac402-6a53-4c49-a201-c450a6ac2f3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800446313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1800446313
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.4261012845
Short name T150
Test name
Test status
Simulation time 53294368 ps
CPU time 0.86 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:06 PM PDT 24
Peak memory 195448 kb
Host smart-58649e20-98c8-4b32-8763-b9f4c23e208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261012845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.4261012845
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3342321550
Short name T511
Test name
Test status
Simulation time 241720525 ps
CPU time 1.34 seconds
Started Jun 05 05:14:01 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 196856 kb
Host smart-3bda839f-461b-4984-a289-8a5f7a3b7afd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342321550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3342321550
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1037078700
Short name T490
Test name
Test status
Simulation time 10897053617 ps
CPU time 36.8 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:43 PM PDT 24
Peak memory 198212 kb
Host smart-b7c69580-5720-404e-bd51-7e76879f2199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037078700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1037078700
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2012709461
Short name T379
Test name
Test status
Simulation time 22005613 ps
CPU time 0.59 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:06 PM PDT 24
Peak memory 193960 kb
Host smart-064f3d29-fad4-4eb3-89fb-ab1f8aee4584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012709461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2012709461
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.707542096
Short name T156
Test name
Test status
Simulation time 15960354 ps
CPU time 0.63 seconds
Started Jun 05 05:14:01 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 194748 kb
Host smart-56ac0367-defc-4098-b697-52be0bbcb738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707542096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.707542096
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.596935250
Short name T74
Test name
Test status
Simulation time 1637625808 ps
CPU time 13.18 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:18 PM PDT 24
Peak memory 198072 kb
Host smart-67dd065d-06f9-4f0f-8c4c-76edffbfeb76
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596935250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.596935250
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.563798881
Short name T414
Test name
Test status
Simulation time 51454176 ps
CPU time 0.92 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:06 PM PDT 24
Peak memory 197864 kb
Host smart-e030f35b-641e-4d72-b569-3d8698af63f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563798881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.563798881
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1683889589
Short name T222
Test name
Test status
Simulation time 60379325 ps
CPU time 0.67 seconds
Started Jun 05 05:14:08 PM PDT 24
Finished Jun 05 05:14:10 PM PDT 24
Peak memory 194448 kb
Host smart-70b8d636-9804-43e2-80d9-d53d780438d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683889589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1683889589
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3854651721
Short name T81
Test name
Test status
Simulation time 64567608 ps
CPU time 2.72 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:08 PM PDT 24
Peak memory 198092 kb
Host smart-41bd39d4-f7c3-4f2f-ad4e-6ec7a2a51c81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854651721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3854651721
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.957974627
Short name T349
Test name
Test status
Simulation time 228044964 ps
CPU time 2.79 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:07 PM PDT 24
Peak memory 197188 kb
Host smart-a8b97865-82ff-4bf8-bfb0-820e33894109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957974627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.957974627
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.549690745
Short name T144
Test name
Test status
Simulation time 80304501 ps
CPU time 0.87 seconds
Started Jun 05 05:14:08 PM PDT 24
Finished Jun 05 05:14:09 PM PDT 24
Peak memory 196528 kb
Host smart-32cb60c7-73a1-4a92-8d96-2b0360cb30df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549690745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.549690745
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.219410638
Short name T548
Test name
Test status
Simulation time 35904929 ps
CPU time 0.95 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:07 PM PDT 24
Peak memory 195868 kb
Host smart-4ee90057-98bc-4af4-8b2c-0f348e6ace9d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219410638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.219410638
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.4200189377
Short name T699
Test name
Test status
Simulation time 367160089 ps
CPU time 5.77 seconds
Started Jun 05 05:14:02 PM PDT 24
Finished Jun 05 05:14:08 PM PDT 24
Peak memory 198052 kb
Host smart-bbd26948-3d86-4703-9f1c-0417cc49e08b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200189377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.4200189377
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3293453392
Short name T52
Test name
Test status
Simulation time 72847382 ps
CPU time 0.92 seconds
Started Jun 05 05:14:03 PM PDT 24
Finished Jun 05 05:14:04 PM PDT 24
Peak memory 213852 kb
Host smart-b48f1f68-3202-4cf7-b51f-310bba75bf2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293453392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3293453392
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.517814805
Short name T553
Test name
Test status
Simulation time 109177274 ps
CPU time 1 seconds
Started Jun 05 05:14:02 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 196468 kb
Host smart-88eb9e16-8997-4d33-a116-a89498504f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517814805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.517814805
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2225075318
Short name T317
Test name
Test status
Simulation time 284083777 ps
CPU time 1.35 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:07 PM PDT 24
Peak memory 198032 kb
Host smart-f08137f5-4f09-4ab6-a4b7-4249b599bf0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225075318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2225075318
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3740654572
Short name T531
Test name
Test status
Simulation time 16095131682 ps
CPU time 63.53 seconds
Started Jun 05 05:14:03 PM PDT 24
Finished Jun 05 05:15:08 PM PDT 24
Peak memory 198156 kb
Host smart-35fe2114-546d-4180-b26d-ecd2c69849de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740654572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3740654572
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.768153908
Short name T689
Test name
Test status
Simulation time 87461716490 ps
CPU time 620.82 seconds
Started Jun 05 05:14:00 PM PDT 24
Finished Jun 05 05:24:21 PM PDT 24
Peak memory 198292 kb
Host smart-0ec499ea-1a4a-4593-b967-3f68ccc3bb94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=768153908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.768153908
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2515525419
Short name T54
Test name
Test status
Simulation time 46781498 ps
CPU time 0.68 seconds
Started Jun 05 05:14:26 PM PDT 24
Finished Jun 05 05:14:27 PM PDT 24
Peak memory 194940 kb
Host smart-0bbc50a6-8c4e-4ca7-83f5-afb28ec729b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515525419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2515525419
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3047824510
Short name T265
Test name
Test status
Simulation time 3064341024 ps
CPU time 21.91 seconds
Started Jun 05 05:14:26 PM PDT 24
Finished Jun 05 05:14:48 PM PDT 24
Peak memory 197076 kb
Host smart-8e7d84c0-4481-4ef1-9b96-c38b8232d337
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047824510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3047824510
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1677968296
Short name T438
Test name
Test status
Simulation time 83814453 ps
CPU time 0.72 seconds
Started Jun 05 05:14:26 PM PDT 24
Finished Jun 05 05:14:27 PM PDT 24
Peak memory 194832 kb
Host smart-30f2058f-5486-4c81-8b7b-13672cfae49a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677968296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1677968296
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3560854423
Short name T615
Test name
Test status
Simulation time 156683884 ps
CPU time 1.25 seconds
Started Jun 05 05:14:24 PM PDT 24
Finished Jun 05 05:14:25 PM PDT 24
Peak memory 196916 kb
Host smart-e23e5533-cc9e-4f07-adb6-944e86e942b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560854423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3560854423
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3285004827
Short name T668
Test name
Test status
Simulation time 127512092 ps
CPU time 2.1 seconds
Started Jun 05 05:14:24 PM PDT 24
Finished Jun 05 05:14:27 PM PDT 24
Peak memory 198104 kb
Host smart-32118161-e570-4f4c-891d-f9fce90833a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285004827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3285004827
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.507267843
Short name T620
Test name
Test status
Simulation time 135130784 ps
CPU time 1.52 seconds
Started Jun 05 05:14:26 PM PDT 24
Finished Jun 05 05:14:28 PM PDT 24
Peak memory 195904 kb
Host smart-4ff4164f-40ce-4254-bc36-c4706db4c555
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507267843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
507267843
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3114135786
Short name T193
Test name
Test status
Simulation time 24923794 ps
CPU time 1.02 seconds
Started Jun 05 05:14:25 PM PDT 24
Finished Jun 05 05:14:27 PM PDT 24
Peak memory 195968 kb
Host smart-bb42d198-358c-4ece-9f50-2811b40040c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114135786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3114135786
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4176906959
Short name T334
Test name
Test status
Simulation time 83940243 ps
CPU time 0.91 seconds
Started Jun 05 05:14:25 PM PDT 24
Finished Jun 05 05:14:27 PM PDT 24
Peak memory 195988 kb
Host smart-f6808cf0-e9c9-4684-91c9-3e70b944a8ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176906959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.4176906959
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1375857531
Short name T29
Test name
Test status
Simulation time 597500157 ps
CPU time 2.79 seconds
Started Jun 05 05:14:25 PM PDT 24
Finished Jun 05 05:14:28 PM PDT 24
Peak memory 198044 kb
Host smart-5dcfe7ea-ad4b-4465-ad1c-e4b469294d65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375857531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1375857531
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1179381845
Short name T229
Test name
Test status
Simulation time 51233353 ps
CPU time 1.38 seconds
Started Jun 05 05:14:28 PM PDT 24
Finished Jun 05 05:14:30 PM PDT 24
Peak memory 196928 kb
Host smart-8bf85ce6-b2ac-43bc-a83d-ef7099aa202f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179381845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1179381845
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.795344199
Short name T320
Test name
Test status
Simulation time 26015258 ps
CPU time 0.74 seconds
Started Jun 05 05:14:25 PM PDT 24
Finished Jun 05 05:14:26 PM PDT 24
Peak memory 195264 kb
Host smart-2e55fd96-1dcb-425a-b3dd-d134bacd8240
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795344199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.795344199
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2182621815
Short name T652
Test name
Test status
Simulation time 9126969687 ps
CPU time 144.27 seconds
Started Jun 05 05:14:25 PM PDT 24
Finished Jun 05 05:16:50 PM PDT 24
Peak memory 198192 kb
Host smart-752f00ae-8720-4304-adf5-f00e944c5d0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182621815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2182621815
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.341397200
Short name T33
Test name
Test status
Simulation time 253499321375 ps
CPU time 1669.3 seconds
Started Jun 05 05:14:23 PM PDT 24
Finished Jun 05 05:42:13 PM PDT 24
Peak memory 198268 kb
Host smart-5d4a76de-0d55-4621-8839-1ff491629544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=341397200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.341397200
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3427541895
Short name T655
Test name
Test status
Simulation time 14057518 ps
CPU time 0.59 seconds
Started Jun 05 05:14:33 PM PDT 24
Finished Jun 05 05:14:34 PM PDT 24
Peak memory 194664 kb
Host smart-901ffa20-42f2-4abf-be75-454b2756a53b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427541895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3427541895
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.909856707
Short name T238
Test name
Test status
Simulation time 47197947 ps
CPU time 0.86 seconds
Started Jun 05 05:14:25 PM PDT 24
Finished Jun 05 05:14:27 PM PDT 24
Peak memory 196240 kb
Host smart-7f864ba3-7e34-4c7f-bd8d-5e03ddba5d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909856707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.909856707
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1546719834
Short name T695
Test name
Test status
Simulation time 1465995150 ps
CPU time 17.36 seconds
Started Jun 05 05:14:35 PM PDT 24
Finished Jun 05 05:14:53 PM PDT 24
Peak memory 195504 kb
Host smart-82d5ca8c-f73b-4a36-a379-323b9ee4b81e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546719834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1546719834
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.853044538
Short name T138
Test name
Test status
Simulation time 49764087 ps
CPU time 0.84 seconds
Started Jun 05 05:14:35 PM PDT 24
Finished Jun 05 05:14:36 PM PDT 24
Peak memory 195916 kb
Host smart-4288c0fa-b335-49bb-a9cc-fc0f33776e13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853044538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.853044538
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.742389638
Short name T189
Test name
Test status
Simulation time 78336635 ps
CPU time 1.28 seconds
Started Jun 05 05:14:33 PM PDT 24
Finished Jun 05 05:14:35 PM PDT 24
Peak memory 196168 kb
Host smart-fc0e1ebe-2b02-4c21-8df0-671c68ed4955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742389638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.742389638
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3532791837
Short name T173
Test name
Test status
Simulation time 446646130 ps
CPU time 3.6 seconds
Started Jun 05 05:14:33 PM PDT 24
Finished Jun 05 05:14:37 PM PDT 24
Peak memory 198104 kb
Host smart-b3780b2b-a359-4bb0-b63d-89cafdaefcfd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532791837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3532791837
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3595608105
Short name T395
Test name
Test status
Simulation time 44304376 ps
CPU time 1.46 seconds
Started Jun 05 05:14:35 PM PDT 24
Finished Jun 05 05:14:37 PM PDT 24
Peak memory 196132 kb
Host smart-a70fb5aa-1462-4568-8b23-c4b21cea7a1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595608105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3595608105
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3538824797
Short name T636
Test name
Test status
Simulation time 68723796 ps
CPU time 0.93 seconds
Started Jun 05 05:14:26 PM PDT 24
Finished Jun 05 05:14:28 PM PDT 24
Peak memory 196080 kb
Host smart-c3acb7ec-8b15-4621-b857-6d990f72cb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538824797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3538824797
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2709021247
Short name T679
Test name
Test status
Simulation time 64801967 ps
CPU time 1.13 seconds
Started Jun 05 05:14:28 PM PDT 24
Finished Jun 05 05:14:30 PM PDT 24
Peak memory 197304 kb
Host smart-8dc8fed7-b49e-40c0-8f6f-02933a77dadc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709021247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2709021247
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1123577406
Short name T670
Test name
Test status
Simulation time 202382149 ps
CPU time 4.82 seconds
Started Jun 05 05:14:34 PM PDT 24
Finished Jun 05 05:14:39 PM PDT 24
Peak memory 197228 kb
Host smart-39636e65-db97-4d5e-8e02-cb547dc8c191
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123577406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1123577406
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3712816284
Short name T211
Test name
Test status
Simulation time 882888505 ps
CPU time 1.25 seconds
Started Jun 05 05:14:24 PM PDT 24
Finished Jun 05 05:14:26 PM PDT 24
Peak memory 197968 kb
Host smart-41897ec5-7532-44ef-ac29-7ea67f7d6d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712816284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3712816284
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.4144549576
Short name T146
Test name
Test status
Simulation time 75531392 ps
CPU time 1.34 seconds
Started Jun 05 05:14:26 PM PDT 24
Finished Jun 05 05:14:28 PM PDT 24
Peak memory 196288 kb
Host smart-f30d3cef-cfb0-49f8-b47d-34d2867e4974
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144549576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.4144549576
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1499987087
Short name T651
Test name
Test status
Simulation time 2820205686 ps
CPU time 42.81 seconds
Started Jun 05 05:14:35 PM PDT 24
Finished Jun 05 05:15:19 PM PDT 24
Peak memory 198296 kb
Host smart-7955f4d8-37a0-45b8-8ae6-a1ab2b4e0e7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499987087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1499987087
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.2796462327
Short name T644
Test name
Test status
Simulation time 41208069355 ps
CPU time 774.25 seconds
Started Jun 05 05:14:33 PM PDT 24
Finished Jun 05 05:27:27 PM PDT 24
Peak memory 198268 kb
Host smart-02cd1c07-64be-4c9d-96da-9fe8b09c12ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2796462327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.2796462327
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3460514123
Short name T59
Test name
Test status
Simulation time 69518578 ps
CPU time 0.61 seconds
Started Jun 05 05:14:43 PM PDT 24
Finished Jun 05 05:14:45 PM PDT 24
Peak memory 194876 kb
Host smart-e46d5519-87b7-4895-9c47-6972f73db206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460514123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3460514123
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2415131572
Short name T352
Test name
Test status
Simulation time 47194856 ps
CPU time 0.72 seconds
Started Jun 05 05:14:44 PM PDT 24
Finished Jun 05 05:14:45 PM PDT 24
Peak memory 194300 kb
Host smart-171ed80c-79d9-4de3-b904-d4e3cd1f5715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415131572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2415131572
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1663760032
Short name T543
Test name
Test status
Simulation time 189337069 ps
CPU time 5.19 seconds
Started Jun 05 05:14:43 PM PDT 24
Finished Jun 05 05:14:49 PM PDT 24
Peak memory 196820 kb
Host smart-59169a64-a762-423d-840b-b92e71185bba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663760032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1663760032
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1440746505
Short name T707
Test name
Test status
Simulation time 217916132 ps
CPU time 0.72 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:14:43 PM PDT 24
Peak memory 194808 kb
Host smart-6cc3c04f-a6b4-4b86-a4c1-224e05b052b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440746505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1440746505
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3011619183
Short name T191
Test name
Test status
Simulation time 204222149 ps
CPU time 1.37 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:14:42 PM PDT 24
Peak memory 196548 kb
Host smart-b5718162-fe4a-4928-bd5c-5e6cbe29f448
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011619183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3011619183
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.992389985
Short name T513
Test name
Test status
Simulation time 25826780 ps
CPU time 1.13 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:41 PM PDT 24
Peak memory 196444 kb
Host smart-08267424-96b2-43a5-b877-9aeb4c114117
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992389985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.992389985
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2753821711
Short name T17
Test name
Test status
Simulation time 162080005 ps
CPU time 1.11 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:14:42 PM PDT 24
Peak memory 195496 kb
Host smart-fa480d11-1cbd-4bc3-aabf-05d97c3d1590
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753821711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2753821711
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.996089975
Short name T622
Test name
Test status
Simulation time 172006845 ps
CPU time 1.12 seconds
Started Jun 05 05:14:34 PM PDT 24
Finished Jun 05 05:14:35 PM PDT 24
Peak memory 195976 kb
Host smart-91b6c263-d00f-44e5-9dc4-a7d8b2278a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996089975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.996089975
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2255869947
Short name T492
Test name
Test status
Simulation time 19203380 ps
CPU time 0.68 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:41 PM PDT 24
Peak memory 194368 kb
Host smart-c8971b55-fb86-4d9b-9e2e-d67688608b2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255869947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2255869947
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3185200779
Short name T534
Test name
Test status
Simulation time 3564042683 ps
CPU time 5.33 seconds
Started Jun 05 05:14:38 PM PDT 24
Finished Jun 05 05:14:44 PM PDT 24
Peak memory 198232 kb
Host smart-6bddacb9-9b1f-4411-9601-6f9aa2671fa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185200779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3185200779
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1040174360
Short name T365
Test name
Test status
Simulation time 42211122 ps
CPU time 1.1 seconds
Started Jun 05 05:14:35 PM PDT 24
Finished Jun 05 05:14:37 PM PDT 24
Peak memory 195696 kb
Host smart-9c00a246-a540-4e81-bb97-ce9da146ad1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040174360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1040174360
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2857793626
Short name T578
Test name
Test status
Simulation time 40595151 ps
CPU time 1.07 seconds
Started Jun 05 05:14:33 PM PDT 24
Finished Jun 05 05:14:34 PM PDT 24
Peak memory 195796 kb
Host smart-370a3d7f-0e2a-4b5d-ab34-716587b635aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857793626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2857793626
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1450608611
Short name T328
Test name
Test status
Simulation time 14023252079 ps
CPU time 79.86 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:15:59 PM PDT 24
Peak memory 198212 kb
Host smart-1ab872b4-6dc7-4574-a679-06cef40e94b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450608611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1450608611
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.4111955748
Short name T690
Test name
Test status
Simulation time 15043577 ps
CPU time 0.58 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:40 PM PDT 24
Peak memory 193948 kb
Host smart-877a185f-9625-4522-864f-ff06fd64a941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111955748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.4111955748
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2201414298
Short name T332
Test name
Test status
Simulation time 28119928 ps
CPU time 0.85 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:14:42 PM PDT 24
Peak memory 195792 kb
Host smart-62a799cf-8fcd-4203-afff-bbc6c6cad907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201414298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2201414298
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2021682139
Short name T151
Test name
Test status
Simulation time 1533948173 ps
CPU time 25.71 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 197000 kb
Host smart-c75a58b4-6e5c-4739-b411-1393357d43e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021682139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2021682139
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.4172338064
Short name T7
Test name
Test status
Simulation time 276449598 ps
CPU time 0.98 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:14:43 PM PDT 24
Peak memory 197828 kb
Host smart-9c4e78e5-029d-48bd-b33b-3740a551fc0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172338064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.4172338064
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.4145367848
Short name T572
Test name
Test status
Simulation time 286109885 ps
CPU time 1.26 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:14:44 PM PDT 24
Peak memory 196704 kb
Host smart-bdaf872a-af2b-4c92-ac75-fed4d50e39dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145367848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.4145367848
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3733581076
Short name T342
Test name
Test status
Simulation time 25439541 ps
CPU time 1.25 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:14:44 PM PDT 24
Peak memory 197484 kb
Host smart-7438e98b-f36b-411d-800e-3fa360165887
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733581076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3733581076
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.924549413
Short name T367
Test name
Test status
Simulation time 1152645906 ps
CPU time 2.99 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:14:45 PM PDT 24
Peak memory 197340 kb
Host smart-887438c6-ed9b-4874-a0ab-6c2ae0424fb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924549413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
924549413
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.770985728
Short name T326
Test name
Test status
Simulation time 117196754 ps
CPU time 1.21 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:41 PM PDT 24
Peak memory 197168 kb
Host smart-015f5214-accd-4721-8784-023369532fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770985728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.770985728
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.976112474
Short name T137
Test name
Test status
Simulation time 88238751 ps
CPU time 0.77 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:14:43 PM PDT 24
Peak memory 196152 kb
Host smart-ab6a82fc-2c3d-48b4-b13c-48bdecb59e3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976112474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.976112474
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2850368722
Short name T10
Test name
Test status
Simulation time 405655397 ps
CPU time 2.88 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:42 PM PDT 24
Peak memory 198048 kb
Host smart-7478ea69-ce44-422f-b510-0582d332e316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850368722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2850368722
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2923365047
Short name T279
Test name
Test status
Simulation time 146913975 ps
CPU time 1.04 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:41 PM PDT 24
Peak memory 195564 kb
Host smart-e42f83ff-246c-46eb-9208-348fadaf4c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923365047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2923365047
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2432411552
Short name T126
Test name
Test status
Simulation time 36975660 ps
CPU time 0.84 seconds
Started Jun 05 05:14:38 PM PDT 24
Finished Jun 05 05:14:39 PM PDT 24
Peak memory 196108 kb
Host smart-b24cbfbb-774d-4649-835b-fa236223585e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432411552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2432411552
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1827412439
Short name T382
Test name
Test status
Simulation time 72558208544 ps
CPU time 197.16 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:18:00 PM PDT 24
Peak memory 198204 kb
Host smart-6dc0978d-a758-45d0-9fe9-361b83359cd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827412439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1827412439
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3650766290
Short name T84
Test name
Test status
Simulation time 15280358 ps
CPU time 0.57 seconds
Started Jun 05 05:14:44 PM PDT 24
Finished Jun 05 05:14:46 PM PDT 24
Peak memory 193952 kb
Host smart-2bb24082-1d4b-47bd-8418-7ba98efb7fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650766290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3650766290
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.572410952
Short name T337
Test name
Test status
Simulation time 139075480 ps
CPU time 0.84 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:41 PM PDT 24
Peak memory 195516 kb
Host smart-4186b1e2-aec2-42ec-b50b-2cb9bb092a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572410952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.572410952
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.764183032
Short name T179
Test name
Test status
Simulation time 3317654449 ps
CPU time 24.72 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:15:06 PM PDT 24
Peak memory 196852 kb
Host smart-8d2eaff7-2a70-4ce2-a327-1c8ef9619487
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764183032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.764183032
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1485021155
Short name T20
Test name
Test status
Simulation time 40733696 ps
CPU time 0.76 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:14:44 PM PDT 24
Peak memory 196604 kb
Host smart-28460989-6f86-4ac9-aec8-9faded17f21b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485021155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1485021155
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1098688356
Short name T303
Test name
Test status
Simulation time 208177510 ps
CPU time 1.05 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:14:43 PM PDT 24
Peak memory 196728 kb
Host smart-ae379491-129f-4838-ba01-f37e1194bced
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098688356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1098688356
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.141283678
Short name T307
Test name
Test status
Simulation time 91925574 ps
CPU time 3.58 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:14:47 PM PDT 24
Peak memory 198104 kb
Host smart-e6658bd7-a2ac-426f-a5b7-76f0976fb47b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141283678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.141283678
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3476691078
Short name T181
Test name
Test status
Simulation time 153410287 ps
CPU time 2.98 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:14:44 PM PDT 24
Peak memory 196988 kb
Host smart-8b197ab4-e79f-4da8-a21e-7625af888db2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476691078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3476691078
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3480644313
Short name T250
Test name
Test status
Simulation time 25654637 ps
CPU time 0.65 seconds
Started Jun 05 05:14:43 PM PDT 24
Finished Jun 05 05:14:44 PM PDT 24
Peak memory 195072 kb
Host smart-0d996220-e772-4979-95b2-4fb6e5eddadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480644313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3480644313
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.727052167
Short name T475
Test name
Test status
Simulation time 226465660 ps
CPU time 1.15 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:41 PM PDT 24
Peak memory 196712 kb
Host smart-97e26e23-9f69-4cd1-83e2-c845ea727e02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727052167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.727052167
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.835265492
Short name T686
Test name
Test status
Simulation time 196866795 ps
CPU time 2.84 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:14:45 PM PDT 24
Peak memory 198032 kb
Host smart-40d7cbc3-0322-4706-b5c2-44c86c039866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835265492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.835265492
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.4193402699
Short name T82
Test name
Test status
Simulation time 396103459 ps
CPU time 1.34 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:42 PM PDT 24
Peak memory 198080 kb
Host smart-0ab9c619-2ea1-4886-a2ab-866d15641c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193402699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.4193402699
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2513484024
Short name T116
Test name
Test status
Simulation time 30612944 ps
CPU time 0.99 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:14:41 PM PDT 24
Peak memory 195696 kb
Host smart-c6f4b06e-a890-402d-95b9-04e65a70bc7f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513484024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2513484024
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2089504494
Short name T3
Test name
Test status
Simulation time 15175062115 ps
CPU time 46.25 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:15:28 PM PDT 24
Peak memory 198256 kb
Host smart-f2e5f964-b536-478d-8921-a7afeea6bb7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089504494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2089504494
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.618914398
Short name T63
Test name
Test status
Simulation time 145289413860 ps
CPU time 793.67 seconds
Started Jun 05 05:14:38 PM PDT 24
Finished Jun 05 05:27:53 PM PDT 24
Peak memory 198304 kb
Host smart-a7723d4f-ff33-4bbe-b31b-c29ddd904c93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=618914398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.618914398
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.4206112630
Short name T329
Test name
Test status
Simulation time 29529419 ps
CPU time 0.59 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:14:43 PM PDT 24
Peak memory 194836 kb
Host smart-ea2fe3e3-68ae-488d-b2df-fdb98ca6d00d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206112630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.4206112630
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2730893666
Short name T653
Test name
Test status
Simulation time 43394844 ps
CPU time 0.69 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:14:43 PM PDT 24
Peak memory 194320 kb
Host smart-4898305e-8457-45de-b5ed-d0ba769d0d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730893666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2730893666
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3415461933
Short name T412
Test name
Test status
Simulation time 5411925911 ps
CPU time 27.6 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:15:08 PM PDT 24
Peak memory 197552 kb
Host smart-18455508-c6a1-4113-bd28-025f18333b46
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415461933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3415461933
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3821842011
Short name T224
Test name
Test status
Simulation time 91978555 ps
CPU time 1 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:14:44 PM PDT 24
Peak memory 196604 kb
Host smart-0da11fc6-72d8-4c59-a9a4-201434535355
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821842011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3821842011
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.365990784
Short name T21
Test name
Test status
Simulation time 31258934 ps
CPU time 0.74 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:14:44 PM PDT 24
Peak memory 194648 kb
Host smart-37a6e8a9-5390-4f95-96d8-109849b9a8db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365990784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.365990784
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.162113792
Short name T185
Test name
Test status
Simulation time 361425430 ps
CPU time 3.85 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:14:45 PM PDT 24
Peak memory 198004 kb
Host smart-cae0252e-adff-42d7-8f37-3e23e2a6d990
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162113792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.162113792
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3022605785
Short name T611
Test name
Test status
Simulation time 440694662 ps
CPU time 3.75 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:14:45 PM PDT 24
Peak memory 198108 kb
Host smart-962d3e0f-0a07-4164-9b08-e2b8cd107030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022605785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3022605785
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3054198737
Short name T196
Test name
Test status
Simulation time 184071911 ps
CPU time 1.23 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:40 PM PDT 24
Peak memory 196184 kb
Host smart-2d3f71fa-549b-4f5c-b1e6-b9e306d45a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054198737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3054198737
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2769635654
Short name T482
Test name
Test status
Simulation time 61753873 ps
CPU time 1.22 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:14:44 PM PDT 24
Peak memory 198116 kb
Host smart-2fd0e911-d131-4ca7-92c8-c7a17b4eb8e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769635654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2769635654
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.807924286
Short name T694
Test name
Test status
Simulation time 1441931322 ps
CPU time 5.97 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:14:48 PM PDT 24
Peak memory 198088 kb
Host smart-95b5318a-226c-4f36-9244-10e96bd7a500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807924286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.807924286
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2851046362
Short name T683
Test name
Test status
Simulation time 266175219 ps
CPU time 1.37 seconds
Started Jun 05 05:14:39 PM PDT 24
Finished Jun 05 05:14:41 PM PDT 24
Peak memory 195592 kb
Host smart-4120e9aa-fce8-4877-b8cb-98c1ff25cb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851046362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2851046362
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.37195094
Short name T122
Test name
Test status
Simulation time 483497543 ps
CPU time 1.01 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:14:42 PM PDT 24
Peak memory 195640 kb
Host smart-fc3dbd69-5a77-475f-9a2c-cc9bf4621f09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37195094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.37195094
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3231362175
Short name T302
Test name
Test status
Simulation time 18994699854 ps
CPU time 175.55 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:17:38 PM PDT 24
Peak memory 198276 kb
Host smart-1bc53b72-64b3-4309-b331-b5c20fe1c869
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231362175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3231362175
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.436918890
Short name T68
Test name
Test status
Simulation time 36362047768 ps
CPU time 984.95 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:31:07 PM PDT 24
Peak memory 198252 kb
Host smart-fe40f1c9-1a22-40f4-8eb3-f4ac5b2ff2b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=436918890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.436918890
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3055468214
Short name T145
Test name
Test status
Simulation time 60823863 ps
CPU time 0.59 seconds
Started Jun 05 05:14:51 PM PDT 24
Finished Jun 05 05:14:52 PM PDT 24
Peak memory 194908 kb
Host smart-0dc38dd5-3582-4f07-aaf4-6b8097b967fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055468214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3055468214
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1022931626
Short name T456
Test name
Test status
Simulation time 71734172 ps
CPU time 0.71 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:14:43 PM PDT 24
Peak memory 195108 kb
Host smart-70d49f6a-1ec2-4ff3-98d6-62c871c0e94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022931626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1022931626
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3913443183
Short name T592
Test name
Test status
Simulation time 1914800541 ps
CPU time 12.67 seconds
Started Jun 05 05:14:44 PM PDT 24
Finished Jun 05 05:14:57 PM PDT 24
Peak memory 196584 kb
Host smart-acd68083-3710-4871-8565-e09984a18eb6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913443183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3913443183
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3235382952
Short name T594
Test name
Test status
Simulation time 175125432 ps
CPU time 0.71 seconds
Started Jun 05 05:14:48 PM PDT 24
Finished Jun 05 05:14:50 PM PDT 24
Peak memory 194800 kb
Host smart-a99d45fa-3356-4dd1-aa68-de675e97bf30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235382952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3235382952
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2164308935
Short name T560
Test name
Test status
Simulation time 380766164 ps
CPU time 1.58 seconds
Started Jun 05 05:14:43 PM PDT 24
Finished Jun 05 05:14:45 PM PDT 24
Peak memory 196908 kb
Host smart-17dce02b-7138-45f0-8f27-0d7456d6d4be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164308935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2164308935
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.143007217
Short name T289
Test name
Test status
Simulation time 207497248 ps
CPU time 3.28 seconds
Started Jun 05 05:14:44 PM PDT 24
Finished Jun 05 05:14:48 PM PDT 24
Peak memory 198064 kb
Host smart-ddb36cd1-e48c-4148-9ddc-136b8fce3bbb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143007217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.143007217
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2754339604
Short name T441
Test name
Test status
Simulation time 55707366 ps
CPU time 0.96 seconds
Started Jun 05 05:14:44 PM PDT 24
Finished Jun 05 05:14:45 PM PDT 24
Peak memory 195436 kb
Host smart-7c7c17a8-dc53-43c4-9e50-58ac6e75cb2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754339604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2754339604
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.299915457
Short name T267
Test name
Test status
Simulation time 39370698 ps
CPU time 0.89 seconds
Started Jun 05 05:14:43 PM PDT 24
Finished Jun 05 05:14:45 PM PDT 24
Peak memory 196024 kb
Host smart-32476e3b-99a2-44c5-984c-6fb18b31f6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299915457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.299915457
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1354370640
Short name T249
Test name
Test status
Simulation time 99095595 ps
CPU time 1.28 seconds
Started Jun 05 05:14:43 PM PDT 24
Finished Jun 05 05:14:45 PM PDT 24
Peak memory 196568 kb
Host smart-67d16e71-5401-4b96-952c-7cae4acc2908
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354370640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1354370640
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3825986547
Short name T13
Test name
Test status
Simulation time 61511821 ps
CPU time 2.94 seconds
Started Jun 05 05:14:40 PM PDT 24
Finished Jun 05 05:14:43 PM PDT 24
Peak memory 198072 kb
Host smart-1cd7b07d-5988-498b-b084-d0df2cc5956c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825986547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3825986547
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1936497846
Short name T419
Test name
Test status
Simulation time 54409558 ps
CPU time 0.92 seconds
Started Jun 05 05:14:42 PM PDT 24
Finished Jun 05 05:14:44 PM PDT 24
Peak memory 195460 kb
Host smart-c185853d-a6b2-4f19-a30a-06146a618cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936497846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1936497846
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2025981249
Short name T56
Test name
Test status
Simulation time 42891052 ps
CPU time 1.24 seconds
Started Jun 05 05:14:41 PM PDT 24
Finished Jun 05 05:14:43 PM PDT 24
Peak memory 195492 kb
Host smart-0b5b4bf1-60e1-44ef-ba49-4fbb8a3c5b99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025981249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2025981249
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2981003887
Short name T275
Test name
Test status
Simulation time 21945681100 ps
CPU time 98.65 seconds
Started Jun 05 05:14:50 PM PDT 24
Finished Jun 05 05:16:29 PM PDT 24
Peak memory 198164 kb
Host smart-99e46cc3-38f9-44bb-af67-3517d9d4fba0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981003887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2981003887
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1015182324
Short name T169
Test name
Test status
Simulation time 12375727 ps
CPU time 0.62 seconds
Started Jun 05 05:14:48 PM PDT 24
Finished Jun 05 05:14:49 PM PDT 24
Peak memory 194144 kb
Host smart-d4f396a2-39c4-4626-b428-a3b04531ef8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015182324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1015182324
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2818516998
Short name T219
Test name
Test status
Simulation time 272713016 ps
CPU time 0.89 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:51 PM PDT 24
Peak memory 196588 kb
Host smart-340a1875-7d6c-44ab-9e6e-fd0e279a780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818516998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2818516998
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.87491564
Short name T375
Test name
Test status
Simulation time 805549484 ps
CPU time 9.11 seconds
Started Jun 05 05:14:47 PM PDT 24
Finished Jun 05 05:14:57 PM PDT 24
Peak memory 198012 kb
Host smart-e6743d7a-b17a-47a0-b026-788bac40d3cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87491564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stress
.87491564
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2021236666
Short name T282
Test name
Test status
Simulation time 126992346 ps
CPU time 1 seconds
Started Jun 05 05:14:48 PM PDT 24
Finished Jun 05 05:14:50 PM PDT 24
Peak memory 197096 kb
Host smart-86e21102-8a51-47f0-82e9-f59419cb2bbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021236666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2021236666
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2035333120
Short name T161
Test name
Test status
Simulation time 52842160 ps
CPU time 0.98 seconds
Started Jun 05 05:14:47 PM PDT 24
Finished Jun 05 05:14:48 PM PDT 24
Peak memory 196124 kb
Host smart-350cfa45-2515-4f36-af78-fd9e203bbf89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035333120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2035333120
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1407037578
Short name T134
Test name
Test status
Simulation time 233417214 ps
CPU time 2.11 seconds
Started Jun 05 05:14:52 PM PDT 24
Finished Jun 05 05:14:54 PM PDT 24
Peak memory 198104 kb
Host smart-4f714bd8-5e39-4a80-9a9a-39b1555fe02b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407037578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1407037578
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.421967008
Short name T159
Test name
Test status
Simulation time 48729906 ps
CPU time 1.44 seconds
Started Jun 05 05:14:47 PM PDT 24
Finished Jun 05 05:14:49 PM PDT 24
Peak memory 197628 kb
Host smart-ce25913b-32f3-4e75-b3a1-dbcf3a6d6ed6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421967008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
421967008
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3902112866
Short name T331
Test name
Test status
Simulation time 112715497 ps
CPU time 0.95 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:51 PM PDT 24
Peak memory 196072 kb
Host smart-035673e2-cbcf-4ed0-b653-e58cc9194abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902112866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3902112866
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2790382130
Short name T210
Test name
Test status
Simulation time 104618403 ps
CPU time 0.62 seconds
Started Jun 05 05:14:48 PM PDT 24
Finished Jun 05 05:14:49 PM PDT 24
Peak memory 194244 kb
Host smart-52cff418-3716-4e14-8e0b-305b82440ef5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790382130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2790382130
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.4073131630
Short name T388
Test name
Test status
Simulation time 377637531 ps
CPU time 4.3 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:54 PM PDT 24
Peak memory 197876 kb
Host smart-7c9460ac-d140-4750-9bc5-7ba1a4c054ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073131630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.4073131630
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1002846383
Short name T206
Test name
Test status
Simulation time 115024277 ps
CPU time 0.94 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:51 PM PDT 24
Peak memory 195836 kb
Host smart-6fccb25f-90b9-4464-9cdb-c36432011169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002846383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1002846383
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.796047497
Short name T197
Test name
Test status
Simulation time 1548589553 ps
CPU time 1.31 seconds
Started Jun 05 05:14:50 PM PDT 24
Finished Jun 05 05:14:52 PM PDT 24
Peak memory 196928 kb
Host smart-60251698-10b1-4934-b561-d38b55b6a52a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796047497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.796047497
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3976824761
Short name T491
Test name
Test status
Simulation time 28634023997 ps
CPU time 195.76 seconds
Started Jun 05 05:14:47 PM PDT 24
Finished Jun 05 05:18:04 PM PDT 24
Peak memory 198228 kb
Host smart-18352edd-8969-44ea-814f-38a66a78f13c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976824761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3976824761
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1421550238
Short name T706
Test name
Test status
Simulation time 26154938 ps
CPU time 0.65 seconds
Started Jun 05 05:14:48 PM PDT 24
Finished Jun 05 05:14:49 PM PDT 24
Peak memory 194148 kb
Host smart-f71e29d9-ff0a-4562-b8a9-b89f30598025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421550238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1421550238
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3742434857
Short name T247
Test name
Test status
Simulation time 51374942 ps
CPU time 0.77 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:51 PM PDT 24
Peak memory 195380 kb
Host smart-f2345f18-389c-4ea6-bd95-eef937c3429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742434857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3742434857
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2819459633
Short name T673
Test name
Test status
Simulation time 1456820581 ps
CPU time 24.44 seconds
Started Jun 05 05:14:50 PM PDT 24
Finished Jun 05 05:15:15 PM PDT 24
Peak memory 198016 kb
Host smart-6bdd1d15-7977-4fac-a0ee-0c540316aa9e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819459633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2819459633
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.296496226
Short name T354
Test name
Test status
Simulation time 982883760 ps
CPU time 0.87 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:51 PM PDT 24
Peak memory 196064 kb
Host smart-cc3fa857-dc83-4667-8f69-57a06350708d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296496226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.296496226
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3656209684
Short name T595
Test name
Test status
Simulation time 64456339 ps
CPU time 0.85 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:50 PM PDT 24
Peak memory 196256 kb
Host smart-29842611-0b8a-4cc1-851a-76ffc0fd1346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656209684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3656209684
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2576722154
Short name T657
Test name
Test status
Simulation time 301039819 ps
CPU time 3.04 seconds
Started Jun 05 05:14:47 PM PDT 24
Finished Jun 05 05:14:51 PM PDT 24
Peak memory 198020 kb
Host smart-972eea38-ba55-40e7-940c-9d24e96e3a39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576722154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2576722154
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1608646462
Short name T236
Test name
Test status
Simulation time 400796549 ps
CPU time 1.78 seconds
Started Jun 05 05:14:47 PM PDT 24
Finished Jun 05 05:14:50 PM PDT 24
Peak memory 196912 kb
Host smart-d9d71c8a-ea74-4187-8928-b879459cf097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608646462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1608646462
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2438127975
Short name T563
Test name
Test status
Simulation time 119856329 ps
CPU time 1.23 seconds
Started Jun 05 05:14:51 PM PDT 24
Finished Jun 05 05:14:53 PM PDT 24
Peak memory 195888 kb
Host smart-9d864401-302b-42b4-be25-8c2cba85e73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438127975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2438127975
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3716575234
Short name T489
Test name
Test status
Simulation time 63509056 ps
CPU time 1.14 seconds
Started Jun 05 05:14:50 PM PDT 24
Finished Jun 05 05:14:52 PM PDT 24
Peak memory 196168 kb
Host smart-eed79a01-f972-4bd7-aa3b-269b4458141b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716575234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3716575234
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1175924741
Short name T445
Test name
Test status
Simulation time 201813577 ps
CPU time 2.53 seconds
Started Jun 05 05:14:50 PM PDT 24
Finished Jun 05 05:14:53 PM PDT 24
Peak memory 198020 kb
Host smart-b8cc9742-0ae5-4b08-a997-e7a42e13f42f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175924741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1175924741
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.4178696897
Short name T350
Test name
Test status
Simulation time 138256156 ps
CPU time 1.09 seconds
Started Jun 05 05:14:48 PM PDT 24
Finished Jun 05 05:14:50 PM PDT 24
Peak memory 196452 kb
Host smart-babf0577-477b-4890-a5de-9044d0e37545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178696897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.4178696897
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1561877803
Short name T643
Test name
Test status
Simulation time 74578471 ps
CPU time 1.34 seconds
Started Jun 05 05:14:48 PM PDT 24
Finished Jun 05 05:14:50 PM PDT 24
Peak memory 196924 kb
Host smart-17b49d58-794b-415f-b027-5ddc7418194f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561877803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1561877803
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.241074141
Short name T227
Test name
Test status
Simulation time 3707059158 ps
CPU time 53.4 seconds
Started Jun 05 05:14:52 PM PDT 24
Finished Jun 05 05:15:46 PM PDT 24
Peak memory 198240 kb
Host smart-d898baa0-0089-48f0-9898-5619f58b5626
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241074141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.241074141
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.250417211
Short name T232
Test name
Test status
Simulation time 10805597 ps
CPU time 0.58 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:56 PM PDT 24
Peak memory 193972 kb
Host smart-0d66ab29-316a-43a6-bffb-41130037e0f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250417211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.250417211
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4026590248
Short name T635
Test name
Test status
Simulation time 204511010 ps
CPU time 0.67 seconds
Started Jun 05 05:14:48 PM PDT 24
Finished Jun 05 05:14:49 PM PDT 24
Peak memory 194300 kb
Host smart-37a2a8ab-697d-4e49-a4bf-3491bd58e22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026590248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4026590248
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.603735783
Short name T154
Test name
Test status
Simulation time 497913709 ps
CPU time 24.8 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:15:14 PM PDT 24
Peak memory 196820 kb
Host smart-63f0259e-1323-42d9-b12a-5fd842ce8b87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603735783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.603735783
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3961195487
Short name T261
Test name
Test status
Simulation time 210692782 ps
CPU time 1.09 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:52 PM PDT 24
Peak memory 196496 kb
Host smart-00db2ee8-241d-46f8-9cb8-d1c5148bdfd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961195487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3961195487
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1969335415
Short name T505
Test name
Test status
Simulation time 64538747 ps
CPU time 1.21 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:51 PM PDT 24
Peak memory 195824 kb
Host smart-e2deeeee-2e02-481e-ac93-e4c8a3178733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969335415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1969335415
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3238377169
Short name T198
Test name
Test status
Simulation time 219099658 ps
CPU time 1.72 seconds
Started Jun 05 05:14:50 PM PDT 24
Finished Jun 05 05:14:52 PM PDT 24
Peak memory 198268 kb
Host smart-efd80422-5fe7-4cf4-a25e-6a4573238be7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238377169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3238377169
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2642928277
Short name T351
Test name
Test status
Simulation time 307994459 ps
CPU time 2.41 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:53 PM PDT 24
Peak memory 198096 kb
Host smart-4bfbaa42-07b1-40ac-a534-ec9227f9d250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642928277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2642928277
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3744869673
Short name T672
Test name
Test status
Simulation time 24740621 ps
CPU time 0.75 seconds
Started Jun 05 05:14:50 PM PDT 24
Finished Jun 05 05:14:52 PM PDT 24
Peak memory 196132 kb
Host smart-90eeaf27-307a-45d6-8b7f-2f532cd05bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744869673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3744869673
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3154715818
Short name T454
Test name
Test status
Simulation time 124523911 ps
CPU time 1.34 seconds
Started Jun 05 05:14:48 PM PDT 24
Finished Jun 05 05:14:50 PM PDT 24
Peak memory 197080 kb
Host smart-c7449861-aa2c-4038-89d2-d19dc5a425bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154715818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3154715818
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2336856259
Short name T642
Test name
Test status
Simulation time 134550932 ps
CPU time 1.98 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:51 PM PDT 24
Peak memory 198076 kb
Host smart-2054103e-ae71-4f39-a381-ad5e9dd688c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336856259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2336856259
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.242169402
Short name T659
Test name
Test status
Simulation time 46099505 ps
CPU time 0.91 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:14:51 PM PDT 24
Peak memory 196188 kb
Host smart-dd0b6439-7122-487d-b774-4bd2cec4e36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242169402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.242169402
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2347607382
Short name T308
Test name
Test status
Simulation time 51422674 ps
CPU time 0.83 seconds
Started Jun 05 05:14:52 PM PDT 24
Finished Jun 05 05:14:53 PM PDT 24
Peak memory 195388 kb
Host smart-2a0edc40-9557-408d-a159-2eb0c8d896e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347607382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2347607382
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1294611057
Short name T127
Test name
Test status
Simulation time 32986138683 ps
CPU time 244.69 seconds
Started Jun 05 05:14:49 PM PDT 24
Finished Jun 05 05:18:54 PM PDT 24
Peak memory 198288 kb
Host smart-2658f825-361b-4c2c-901f-57ad6df2935a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294611057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1294611057
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3066707777
Short name T162
Test name
Test status
Simulation time 12885136 ps
CPU time 0.61 seconds
Started Jun 05 05:14:08 PM PDT 24
Finished Jun 05 05:14:10 PM PDT 24
Peak memory 193960 kb
Host smart-3987be88-59b4-4726-bdc9-708b30c8cf88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066707777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3066707777
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4099963245
Short name T450
Test name
Test status
Simulation time 48837552 ps
CPU time 0.93 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:06 PM PDT 24
Peak memory 196360 kb
Host smart-849cc1e3-8624-4844-b780-4b245755a0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099963245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.4099963245
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.4071932078
Short name T605
Test name
Test status
Simulation time 411144476 ps
CPU time 11.3 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:17 PM PDT 24
Peak memory 197012 kb
Host smart-f86ecb25-1d48-498a-8f80-a575e3d8215c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071932078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.4071932078
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2678305776
Short name T708
Test name
Test status
Simulation time 611426686 ps
CPU time 1.1 seconds
Started Jun 05 05:14:01 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 196396 kb
Host smart-d44eea9a-c721-42ac-8660-67c88e1397df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678305776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2678305776
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2739210676
Short name T372
Test name
Test status
Simulation time 23610582 ps
CPU time 0.79 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:05 PM PDT 24
Peak memory 195504 kb
Host smart-85d08a30-4cb3-47c6-892c-81344993236d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739210676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2739210676
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1146287143
Short name T675
Test name
Test status
Simulation time 58407751 ps
CPU time 2.25 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:07 PM PDT 24
Peak memory 196468 kb
Host smart-8e513ba4-3710-4b59-925a-d3d59a784916
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146287143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1146287143
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2851413900
Short name T667
Test name
Test status
Simulation time 323481301 ps
CPU time 2.16 seconds
Started Jun 05 05:14:02 PM PDT 24
Finished Jun 05 05:14:05 PM PDT 24
Peak memory 198120 kb
Host smart-df792ba1-0aec-4e59-b13c-99bc634b9a24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851413900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2851413900
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3114232357
Short name T485
Test name
Test status
Simulation time 157265394 ps
CPU time 0.92 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:07 PM PDT 24
Peak memory 195924 kb
Host smart-5206110d-f3fd-423d-98f0-30f050095679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114232357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3114232357
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1891652315
Short name T473
Test name
Test status
Simulation time 61058748 ps
CPU time 0.86 seconds
Started Jun 05 05:14:02 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 195624 kb
Host smart-4ce15512-9324-464a-8e93-fcb618aef1d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891652315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1891652315
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3821869078
Short name T139
Test name
Test status
Simulation time 1040607051 ps
CPU time 5.11 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:10 PM PDT 24
Peak memory 198064 kb
Host smart-669b8f17-633e-402a-89e4-1df0a0c09780
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821869078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3821869078
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.933316897
Short name T216
Test name
Test status
Simulation time 236740167 ps
CPU time 1.35 seconds
Started Jun 05 05:14:06 PM PDT 24
Finished Jun 05 05:14:08 PM PDT 24
Peak memory 196908 kb
Host smart-0de224db-d66b-43c4-97c8-4d8709e63d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933316897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.933316897
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3333589800
Short name T519
Test name
Test status
Simulation time 39043765 ps
CPU time 0.77 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:05 PM PDT 24
Peak memory 196016 kb
Host smart-2e5e6e34-821e-4d8a-ac63-6b989990320e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333589800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3333589800
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3975660450
Short name T442
Test name
Test status
Simulation time 112685967018 ps
CPU time 146.13 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:16:32 PM PDT 24
Peak memory 198164 kb
Host smart-c0b7fe10-91d7-4855-a369-027fe696c414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975660450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3975660450
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.222416053
Short name T580
Test name
Test status
Simulation time 103479283690 ps
CPU time 1443.48 seconds
Started Jun 05 05:14:01 PM PDT 24
Finished Jun 05 05:38:05 PM PDT 24
Peak memory 198264 kb
Host smart-7424c98d-d4d6-4b35-a53c-c946e78325bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=222416053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.222416053
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1204189004
Short name T387
Test name
Test status
Simulation time 14685520 ps
CPU time 0.58 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:56 PM PDT 24
Peak memory 194600 kb
Host smart-7a342db7-1d0f-4169-b2b1-501b873eeaf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204189004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1204189004
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2140613470
Short name T167
Test name
Test status
Simulation time 83628787 ps
CPU time 0.88 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:57 PM PDT 24
Peak memory 197332 kb
Host smart-8d1178bc-f78c-4124-b9d1-8654b2eced6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140613470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2140613470
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2614182593
Short name T117
Test name
Test status
Simulation time 4170829316 ps
CPU time 24.99 seconds
Started Jun 05 05:14:57 PM PDT 24
Finished Jun 05 05:15:23 PM PDT 24
Peak memory 198076 kb
Host smart-6843b88b-c54f-4ac1-a485-200c45976f11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614182593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2614182593
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1715119764
Short name T517
Test name
Test status
Simulation time 136579421 ps
CPU time 0.87 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:57 PM PDT 24
Peak memory 195780 kb
Host smart-19e8d41c-e16d-4c91-aaa7-f169401eb878
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715119764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1715119764
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.867864654
Short name T712
Test name
Test status
Simulation time 893401480 ps
CPU time 3.39 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:59 PM PDT 24
Peak memory 198112 kb
Host smart-5bc5990a-145b-45e0-ac3c-f09e130fe391
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867864654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.867864654
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2341824927
Short name T233
Test name
Test status
Simulation time 130748090 ps
CPU time 2.67 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:58 PM PDT 24
Peak memory 197276 kb
Host smart-8f04b2d9-3896-45cc-87f3-3ce54d83567d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341824927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2341824927
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3524186230
Short name T266
Test name
Test status
Simulation time 47823827 ps
CPU time 1.12 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:57 PM PDT 24
Peak memory 196708 kb
Host smart-9e063e80-6b91-47ab-8db1-40ed09b07445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524186230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3524186230
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3001887448
Short name T410
Test name
Test status
Simulation time 59770447 ps
CPU time 0.92 seconds
Started Jun 05 05:14:58 PM PDT 24
Finished Jun 05 05:14:59 PM PDT 24
Peak memory 196004 kb
Host smart-c0d27b00-a29d-4937-9a9b-dcf104373d4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001887448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3001887448
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3086932768
Short name T451
Test name
Test status
Simulation time 139136257 ps
CPU time 1.51 seconds
Started Jun 05 05:14:54 PM PDT 24
Finished Jun 05 05:14:57 PM PDT 24
Peak memory 198044 kb
Host smart-f63ede06-3cda-4c6f-8460-719fa7b98f39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086932768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3086932768
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.117457321
Short name T507
Test name
Test status
Simulation time 32614312 ps
CPU time 0.85 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:56 PM PDT 24
Peak memory 196140 kb
Host smart-cd554553-837c-4f1c-9c50-f540b2b39286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117457321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.117457321
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.4237565357
Short name T251
Test name
Test status
Simulation time 101139344 ps
CPU time 1.15 seconds
Started Jun 05 05:14:56 PM PDT 24
Finished Jun 05 05:14:58 PM PDT 24
Peak memory 195820 kb
Host smart-f76950b3-dc24-4c3e-8847-7cdf58fe1c62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237565357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.4237565357
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2033481883
Short name T292
Test name
Test status
Simulation time 43789971675 ps
CPU time 131.22 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:17:07 PM PDT 24
Peak memory 198236 kb
Host smart-d3a3fcd2-771f-440f-992b-352444578f48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033481883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2033481883
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3057490588
Short name T369
Test name
Test status
Simulation time 13947665 ps
CPU time 0.6 seconds
Started Jun 05 05:14:56 PM PDT 24
Finished Jun 05 05:14:57 PM PDT 24
Peak memory 194140 kb
Host smart-52324b77-010e-42c8-b359-1e731d3f341f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057490588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3057490588
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2218903043
Short name T461
Test name
Test status
Simulation time 65477402 ps
CPU time 0.67 seconds
Started Jun 05 05:14:56 PM PDT 24
Finished Jun 05 05:14:58 PM PDT 24
Peak memory 194124 kb
Host smart-73e3f65e-2b50-4f6c-93a5-c21b833e0b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218903043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2218903043
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3777748815
Short name T12
Test name
Test status
Simulation time 338928296 ps
CPU time 10.5 seconds
Started Jun 05 05:14:58 PM PDT 24
Finished Jun 05 05:15:09 PM PDT 24
Peak memory 195036 kb
Host smart-c972fd42-1b15-4804-a714-adcb97bc978e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777748815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3777748815
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3753376777
Short name T203
Test name
Test status
Simulation time 31175295 ps
CPU time 0.74 seconds
Started Jun 05 05:14:54 PM PDT 24
Finished Jun 05 05:14:55 PM PDT 24
Peak memory 195820 kb
Host smart-66da823a-a716-4217-a8c3-3a1106144537
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753376777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3753376777
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.834764006
Short name T403
Test name
Test status
Simulation time 137826526 ps
CPU time 0.88 seconds
Started Jun 05 05:14:56 PM PDT 24
Finished Jun 05 05:14:58 PM PDT 24
Peak memory 195796 kb
Host smart-438aee2a-33eb-490f-9e10-e4680b01bb65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834764006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.834764006
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.742123694
Short name T542
Test name
Test status
Simulation time 63821953 ps
CPU time 1.46 seconds
Started Jun 05 05:14:59 PM PDT 24
Finished Jun 05 05:15:01 PM PDT 24
Peak memory 196464 kb
Host smart-fe518ed6-2eaf-4d2a-b529-b1e81e6cc2e9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742123694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.742123694
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.856760404
Short name T213
Test name
Test status
Simulation time 672714679 ps
CPU time 2.23 seconds
Started Jun 05 05:14:58 PM PDT 24
Finished Jun 05 05:15:00 PM PDT 24
Peak memory 196612 kb
Host smart-b18106e4-8e76-49b4-aff2-b0007251a902
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856760404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
856760404
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2221891613
Short name T547
Test name
Test status
Simulation time 76562545 ps
CPU time 0.96 seconds
Started Jun 05 05:14:59 PM PDT 24
Finished Jun 05 05:15:00 PM PDT 24
Peak memory 195932 kb
Host smart-fd82bb93-f531-4241-beab-4351e2a78ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221891613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2221891613
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.55602940
Short name T323
Test name
Test status
Simulation time 94118815 ps
CPU time 1.04 seconds
Started Jun 05 05:15:04 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 196668 kb
Host smart-bda624eb-04dd-4f88-89d3-1bb79036d55b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55602940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup_
pulldown.55602940
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3945710446
Short name T356
Test name
Test status
Simulation time 427311108 ps
CPU time 5.08 seconds
Started Jun 05 05:14:57 PM PDT 24
Finished Jun 05 05:15:03 PM PDT 24
Peak memory 198024 kb
Host smart-3ec46ff2-5466-4ba5-bfb7-2be541b1a1e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945710446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3945710446
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2356454691
Short name T392
Test name
Test status
Simulation time 43466034 ps
CPU time 1.14 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:57 PM PDT 24
Peak memory 196388 kb
Host smart-82ec4793-20c8-412a-8b35-fbb5b7e41f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356454691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2356454691
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1231698224
Short name T231
Test name
Test status
Simulation time 69508940 ps
CPU time 1.17 seconds
Started Jun 05 05:15:02 PM PDT 24
Finished Jun 05 05:15:04 PM PDT 24
Peak memory 196468 kb
Host smart-6153fd90-102c-4d5f-a3b2-e64569ce3e8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231698224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1231698224
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.524431201
Short name T660
Test name
Test status
Simulation time 5543247774 ps
CPU time 74.63 seconds
Started Jun 05 05:14:58 PM PDT 24
Finished Jun 05 05:16:13 PM PDT 24
Peak memory 198240 kb
Host smart-9be88190-7d6d-44e3-9df6-0dd1268c3b8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524431201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.524431201
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1484261686
Short name T470
Test name
Test status
Simulation time 32705248538 ps
CPU time 893.54 seconds
Started Jun 05 05:14:57 PM PDT 24
Finished Jun 05 05:29:51 PM PDT 24
Peak memory 198348 kb
Host smart-632aa744-0c12-45e9-a9eb-bf8996e2dc29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1484261686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1484261686
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2323338422
Short name T269
Test name
Test status
Simulation time 69741760 ps
CPU time 0.61 seconds
Started Jun 05 05:15:02 PM PDT 24
Finished Jun 05 05:15:03 PM PDT 24
Peak memory 194852 kb
Host smart-28db3598-43c2-4e1c-9207-a7b2368855eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323338422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2323338422
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2201341345
Short name T182
Test name
Test status
Simulation time 84777267 ps
CPU time 0.92 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 196492 kb
Host smart-fc2279f9-0203-4298-9592-2000a60a73ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201341345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2201341345
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3586949479
Short name T152
Test name
Test status
Simulation time 145591423 ps
CPU time 4.22 seconds
Started Jun 05 05:14:56 PM PDT 24
Finished Jun 05 05:15:01 PM PDT 24
Peak memory 195896 kb
Host smart-6b59b1fc-d5c1-4395-9ca1-282e8ea74b11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586949479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3586949479
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3899950256
Short name T630
Test name
Test status
Simulation time 83065179 ps
CPU time 0.96 seconds
Started Jun 05 05:14:56 PM PDT 24
Finished Jun 05 05:14:58 PM PDT 24
Peak memory 197104 kb
Host smart-b7bb8b5b-8dc9-4f3d-8e71-34f761a9d73f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899950256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3899950256
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1698243499
Short name T16
Test name
Test status
Simulation time 48856955 ps
CPU time 0.95 seconds
Started Jun 05 05:14:54 PM PDT 24
Finished Jun 05 05:14:56 PM PDT 24
Peak memory 197340 kb
Host smart-04526141-ce88-4229-b1f0-c8cbff079b42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698243499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1698243499
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.924076763
Short name T85
Test name
Test status
Simulation time 243147787 ps
CPU time 2.65 seconds
Started Jun 05 05:14:54 PM PDT 24
Finished Jun 05 05:14:57 PM PDT 24
Peak memory 198048 kb
Host smart-4f8ff129-df0d-437b-9521-27d9b788132a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924076763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.924076763
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.849511227
Short name T550
Test name
Test status
Simulation time 55722282 ps
CPU time 1.57 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:58 PM PDT 24
Peak memory 196092 kb
Host smart-6c0a30cd-0e99-43b8-b493-af3d0e3bf343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849511227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
849511227
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3409607412
Short name T377
Test name
Test status
Simulation time 21816648 ps
CPU time 0.97 seconds
Started Jun 05 05:14:57 PM PDT 24
Finished Jun 05 05:14:59 PM PDT 24
Peak memory 196040 kb
Host smart-1441f717-baf5-4735-ba54-d0e03301b012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409607412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3409607412
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2771114580
Short name T436
Test name
Test status
Simulation time 284969212 ps
CPU time 0.9 seconds
Started Jun 05 05:14:56 PM PDT 24
Finished Jun 05 05:14:58 PM PDT 24
Peak memory 196104 kb
Host smart-4140ebf2-b035-4b55-a655-7ec9e029511f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771114580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2771114580
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2397782131
Short name T554
Test name
Test status
Simulation time 2470322899 ps
CPU time 6.06 seconds
Started Jun 05 05:15:02 PM PDT 24
Finished Jun 05 05:15:09 PM PDT 24
Peak memory 198140 kb
Host smart-7b2cd66a-d284-48fd-a329-8678fbf5dd2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397782131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2397782131
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3478329546
Short name T172
Test name
Test status
Simulation time 370161671 ps
CPU time 1.32 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 198020 kb
Host smart-10df13ec-7a86-45be-adbc-56749d293123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478329546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3478329546
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2903651434
Short name T518
Test name
Test status
Simulation time 159978939 ps
CPU time 1.36 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:14:57 PM PDT 24
Peak memory 195848 kb
Host smart-571b274a-719b-4213-bfc4-b0ec9ec72e66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903651434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2903651434
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.981020725
Short name T618
Test name
Test status
Simulation time 18722488115 ps
CPU time 126.64 seconds
Started Jun 05 05:14:55 PM PDT 24
Finished Jun 05 05:17:03 PM PDT 24
Peak memory 198236 kb
Host smart-fb45a6ec-df00-4914-a966-6b71fe0803bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981020725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.981020725
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.4069931539
Short name T160
Test name
Test status
Simulation time 37632438 ps
CPU time 0.61 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 193968 kb
Host smart-49759337-3f9e-49be-9285-49357f8282ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069931539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.4069931539
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2144700624
Short name T431
Test name
Test status
Simulation time 18616567 ps
CPU time 0.73 seconds
Started Jun 05 05:15:02 PM PDT 24
Finished Jun 05 05:15:03 PM PDT 24
Peak memory 194332 kb
Host smart-d207e94d-7a52-4bab-87fd-5fc8c7d41393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144700624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2144700624
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2730552481
Short name T639
Test name
Test status
Simulation time 654616466 ps
CPU time 6.08 seconds
Started Jun 05 05:15:06 PM PDT 24
Finished Jun 05 05:15:13 PM PDT 24
Peak memory 195488 kb
Host smart-6aba65d1-1db4-47a6-bc7d-1a10be399e06
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730552481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2730552481
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3422068148
Short name T584
Test name
Test status
Simulation time 84135427 ps
CPU time 1 seconds
Started Jun 05 05:15:04 PM PDT 24
Finished Jun 05 05:15:06 PM PDT 24
Peak memory 196668 kb
Host smart-76cd66ff-b561-437f-b469-2d268c8dcd1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422068148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3422068148
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4255797452
Short name T411
Test name
Test status
Simulation time 352686421 ps
CPU time 1.45 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 196948 kb
Host smart-36fbb5f8-a057-4a00-9cac-c8bf11530c35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255797452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4255797452
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.574210473
Short name T274
Test name
Test status
Simulation time 238078439 ps
CPU time 1.81 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:06 PM PDT 24
Peak memory 196784 kb
Host smart-77213668-d65c-471f-a069-a5ce4c78e135
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574210473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.574210473
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.4291084642
Short name T400
Test name
Test status
Simulation time 404407490 ps
CPU time 2.29 seconds
Started Jun 05 05:15:01 PM PDT 24
Finished Jun 05 05:15:04 PM PDT 24
Peak memory 197436 kb
Host smart-a683a97e-b6f7-4b04-9958-cd05cd158f45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291084642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.4291084642
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.569164832
Short name T696
Test name
Test status
Simulation time 40021949 ps
CPU time 0.66 seconds
Started Jun 05 05:15:12 PM PDT 24
Finished Jun 05 05:15:14 PM PDT 24
Peak memory 195340 kb
Host smart-e60c879c-fb38-4d53-a15c-7185218951bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569164832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.569164832
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3621152103
Short name T546
Test name
Test status
Simulation time 83073918 ps
CPU time 0.78 seconds
Started Jun 05 05:15:01 PM PDT 24
Finished Jun 05 05:15:03 PM PDT 24
Peak memory 196128 kb
Host smart-de41918a-49cb-40d3-8590-bb0c2d320a39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621152103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3621152103
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3193484670
Short name T18
Test name
Test status
Simulation time 291287851 ps
CPU time 3.28 seconds
Started Jun 05 05:15:01 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 197748 kb
Host smart-23ab0534-de76-46f7-9933-087ba5d8827f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193484670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3193484670
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2477948743
Short name T551
Test name
Test status
Simulation time 33366802 ps
CPU time 1.09 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 195584 kb
Host smart-f1dd0cb7-e8bb-448f-a551-9c810eaa79f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477948743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2477948743
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.9105559
Short name T523
Test name
Test status
Simulation time 49712110 ps
CPU time 1.26 seconds
Started Jun 05 05:15:12 PM PDT 24
Finished Jun 05 05:15:14 PM PDT 24
Peak memory 196208 kb
Host smart-837ce436-322d-4c38-bd7f-98da9d48d68f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9105559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.9105559
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2763253889
Short name T538
Test name
Test status
Simulation time 13583268039 ps
CPU time 171.69 seconds
Started Jun 05 05:15:04 PM PDT 24
Finished Jun 05 05:17:56 PM PDT 24
Peak memory 198296 kb
Host smart-30455983-ecde-4f38-a1fe-9c4f858e4e3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763253889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2763253889
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2698638683
Short name T304
Test name
Test status
Simulation time 21664361 ps
CPU time 0.56 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 193924 kb
Host smart-750e5d97-39f5-4f28-b0b9-bfe112908af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698638683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2698638683
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.446839529
Short name T241
Test name
Test status
Simulation time 131792050 ps
CPU time 0.9 seconds
Started Jun 05 05:15:02 PM PDT 24
Finished Jun 05 05:15:03 PM PDT 24
Peak memory 195612 kb
Host smart-4d33e4a0-ba39-4bbd-a4ac-d4ae65f4d2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446839529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.446839529
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3462189579
Short name T360
Test name
Test status
Simulation time 1861986962 ps
CPU time 7.89 seconds
Started Jun 05 05:15:02 PM PDT 24
Finished Jun 05 05:15:10 PM PDT 24
Peak memory 196884 kb
Host smart-080b67dd-9bd8-498d-a458-e098c7cb1577
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462189579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3462189579
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.676946248
Short name T355
Test name
Test status
Simulation time 67337441 ps
CPU time 1.03 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 196648 kb
Host smart-28ce3c38-c1fa-46c7-beaf-70774a820efa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676946248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.676946248
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1954331946
Short name T439
Test name
Test status
Simulation time 62650029 ps
CPU time 0.71 seconds
Started Jun 05 05:15:06 PM PDT 24
Finished Jun 05 05:15:08 PM PDT 24
Peak memory 194460 kb
Host smart-12e448fd-bf32-4218-94e8-ba0df32f048c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954331946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1954331946
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1780827662
Short name T631
Test name
Test status
Simulation time 140009953 ps
CPU time 1.47 seconds
Started Jun 05 05:15:11 PM PDT 24
Finished Jun 05 05:15:13 PM PDT 24
Peak memory 196632 kb
Host smart-46421df7-19e5-44cb-b36f-920f69bdf9e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780827662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1780827662
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.990564959
Short name T416
Test name
Test status
Simulation time 486149764 ps
CPU time 3.12 seconds
Started Jun 05 05:15:05 PM PDT 24
Finished Jun 05 05:15:09 PM PDT 24
Peak memory 196980 kb
Host smart-2eef02bc-d844-4819-aaf7-9e1c005f05ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990564959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
990564959
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.323406990
Short name T583
Test name
Test status
Simulation time 305018322 ps
CPU time 0.83 seconds
Started Jun 05 05:15:01 PM PDT 24
Finished Jun 05 05:15:02 PM PDT 24
Peak memory 195552 kb
Host smart-6d1c0224-e473-4368-b14a-ca1e43c8bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323406990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.323406990
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1198968420
Short name T398
Test name
Test status
Simulation time 56285167 ps
CPU time 1.36 seconds
Started Jun 05 05:15:01 PM PDT 24
Finished Jun 05 05:15:03 PM PDT 24
Peak memory 197044 kb
Host smart-75326140-30ff-4ae2-a96d-1c6f0dbdb54b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198968420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1198968420
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2380059413
Short name T344
Test name
Test status
Simulation time 150014664 ps
CPU time 2.05 seconds
Started Jun 05 05:15:13 PM PDT 24
Finished Jun 05 05:15:15 PM PDT 24
Peak memory 197968 kb
Host smart-c283d8a5-c18b-42cd-b3c5-aa8e7041e4ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380059413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2380059413
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1691235124
Short name T130
Test name
Test status
Simulation time 137065099 ps
CPU time 0.95 seconds
Started Jun 05 05:15:04 PM PDT 24
Finished Jun 05 05:15:06 PM PDT 24
Peak memory 196480 kb
Host smart-509c7ded-5224-455e-972d-243c22a92a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691235124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1691235124
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2471711183
Short name T405
Test name
Test status
Simulation time 187632908 ps
CPU time 1.32 seconds
Started Jun 05 05:15:02 PM PDT 24
Finished Jun 05 05:15:04 PM PDT 24
Peak memory 195588 kb
Host smart-4672eaec-554f-43b2-922f-2a0c0ede50bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471711183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2471711183
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4195387069
Short name T297
Test name
Test status
Simulation time 14853657569 ps
CPU time 105.85 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:16:49 PM PDT 24
Peak memory 198184 kb
Host smart-66ce3465-8d24-4680-b91f-391b6eeb0765
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195387069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4195387069
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2079500668
Short name T78
Test name
Test status
Simulation time 610928127263 ps
CPU time 1471.08 seconds
Started Jun 05 05:15:13 PM PDT 24
Finished Jun 05 05:39:45 PM PDT 24
Peak memory 198212 kb
Host smart-109474c1-5cb0-4efc-876c-a0942556cfde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2079500668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2079500668
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2748822681
Short name T582
Test name
Test status
Simulation time 35138481 ps
CPU time 0.59 seconds
Started Jun 05 05:15:01 PM PDT 24
Finished Jun 05 05:15:02 PM PDT 24
Peak memory 193956 kb
Host smart-9d2f4883-25e6-42ff-9001-2f44f45e70a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748822681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2748822681
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3299257433
Short name T488
Test name
Test status
Simulation time 26784820 ps
CPU time 0.86 seconds
Started Jun 05 05:15:05 PM PDT 24
Finished Jun 05 05:15:07 PM PDT 24
Peak memory 195368 kb
Host smart-bb406f57-a62e-482b-9c0c-7ba507bd3d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299257433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3299257433
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2518898477
Short name T218
Test name
Test status
Simulation time 8293984254 ps
CPU time 26.48 seconds
Started Jun 05 05:15:11 PM PDT 24
Finished Jun 05 05:15:38 PM PDT 24
Peak memory 198096 kb
Host smart-fb39afdb-17ac-4890-9a13-dbf09d1a40bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518898477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2518898477
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2894479665
Short name T446
Test name
Test status
Simulation time 40071715 ps
CPU time 0.88 seconds
Started Jun 05 05:15:05 PM PDT 24
Finished Jun 05 05:15:07 PM PDT 24
Peak memory 196792 kb
Host smart-ddba94cb-5093-4f42-9086-68801d25c95a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894479665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2894479665
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3160553206
Short name T637
Test name
Test status
Simulation time 249060687 ps
CPU time 1.3 seconds
Started Jun 05 05:15:04 PM PDT 24
Finished Jun 05 05:15:07 PM PDT 24
Peak memory 197220 kb
Host smart-d0af2e9e-9fb1-4f15-96c0-00a33639fce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160553206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3160553206
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1925350489
Short name T209
Test name
Test status
Simulation time 31298856 ps
CPU time 1.37 seconds
Started Jun 05 05:15:06 PM PDT 24
Finished Jun 05 05:15:08 PM PDT 24
Peak memory 196656 kb
Host smart-859fce4e-84b3-436e-b6a6-fc2d1e2e1cff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925350489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1925350489
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1898755188
Short name T143
Test name
Test status
Simulation time 420034961 ps
CPU time 2.47 seconds
Started Jun 05 05:15:01 PM PDT 24
Finished Jun 05 05:15:04 PM PDT 24
Peak memory 196268 kb
Host smart-c37f6aa5-a149-4c70-a5c3-d3892e3c5bab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898755188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1898755188
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.4262954265
Short name T658
Test name
Test status
Simulation time 443436656 ps
CPU time 1.28 seconds
Started Jun 05 05:15:01 PM PDT 24
Finished Jun 05 05:15:03 PM PDT 24
Peak memory 196600 kb
Host smart-48c17ba0-2883-41a6-ade6-4f7696e6ef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262954265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.4262954265
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3069372254
Short name T650
Test name
Test status
Simulation time 43694050 ps
CPU time 1.06 seconds
Started Jun 05 05:15:04 PM PDT 24
Finished Jun 05 05:15:06 PM PDT 24
Peak memory 196016 kb
Host smart-766fb6a7-d92a-48dd-a174-9c637bc80178
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069372254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3069372254
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.4020816583
Short name T295
Test name
Test status
Simulation time 80628587 ps
CPU time 4.12 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:08 PM PDT 24
Peak memory 198024 kb
Host smart-6b5a4953-9a00-4403-b87d-852a739e66b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020816583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.4020816583
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3245935626
Short name T648
Test name
Test status
Simulation time 128834475 ps
CPU time 1.16 seconds
Started Jun 05 05:15:02 PM PDT 24
Finished Jun 05 05:15:04 PM PDT 24
Peak memory 196288 kb
Host smart-b1396a71-b471-4847-b363-50409a81ae2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245935626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3245935626
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1438479486
Short name T272
Test name
Test status
Simulation time 70583676 ps
CPU time 0.96 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 196528 kb
Host smart-f4404a2a-c035-4fa7-ae4b-6029a12baf44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438479486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1438479486
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3403993330
Short name T440
Test name
Test status
Simulation time 7707578744 ps
CPU time 192.83 seconds
Started Jun 05 05:15:10 PM PDT 24
Finished Jun 05 05:18:23 PM PDT 24
Peak memory 198148 kb
Host smart-573587fb-8b7e-4359-952e-cf8ea67b74f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403993330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3403993330
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.4249325252
Short name T157
Test name
Test status
Simulation time 11325653 ps
CPU time 0.56 seconds
Started Jun 05 05:15:12 PM PDT 24
Finished Jun 05 05:15:13 PM PDT 24
Peak memory 194668 kb
Host smart-b09ad730-230c-4e01-b736-5e846ba7ebdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249325252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.4249325252
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2548400199
Short name T237
Test name
Test status
Simulation time 23789596 ps
CPU time 0.83 seconds
Started Jun 05 05:15:16 PM PDT 24
Finished Jun 05 05:15:17 PM PDT 24
Peak memory 195340 kb
Host smart-1179085f-8163-4d30-ab1b-fb461a7ba950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548400199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2548400199
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1553077786
Short name T208
Test name
Test status
Simulation time 522894423 ps
CPU time 18.97 seconds
Started Jun 05 05:15:12 PM PDT 24
Finished Jun 05 05:15:32 PM PDT 24
Peak memory 196996 kb
Host smart-defd7fd6-3610-42de-86c9-56446d3c4fcd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553077786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1553077786
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2294726140
Short name T364
Test name
Test status
Simulation time 410364670 ps
CPU time 1.04 seconds
Started Jun 05 05:15:12 PM PDT 24
Finished Jun 05 05:15:14 PM PDT 24
Peak memory 196188 kb
Host smart-0b1d48fd-42a6-4ec1-9a02-82c80c245061
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294726140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2294726140
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.4109009630
Short name T300
Test name
Test status
Simulation time 182907181 ps
CPU time 1.16 seconds
Started Jun 05 05:15:10 PM PDT 24
Finished Jun 05 05:15:12 PM PDT 24
Peak memory 196052 kb
Host smart-d25a7273-00f0-47d0-b5e4-035ff504f50c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109009630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.4109009630
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2463500707
Short name T427
Test name
Test status
Simulation time 367106728 ps
CPU time 3.56 seconds
Started Jun 05 05:15:13 PM PDT 24
Finished Jun 05 05:15:17 PM PDT 24
Peak memory 196692 kb
Host smart-3a5e3230-f5a0-455b-a3ba-92430dc00f19
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463500707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2463500707
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.596183246
Short name T663
Test name
Test status
Simulation time 168197712 ps
CPU time 3.22 seconds
Started Jun 05 05:15:11 PM PDT 24
Finished Jun 05 05:15:14 PM PDT 24
Peak memory 196816 kb
Host smart-accfde4d-d44d-46fa-a5e6-84712363fbec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596183246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
596183246
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1573822486
Short name T682
Test name
Test status
Simulation time 68541572 ps
CPU time 1.4 seconds
Started Jun 05 05:15:05 PM PDT 24
Finished Jun 05 05:15:07 PM PDT 24
Peak memory 198136 kb
Host smart-2048c847-1f6c-43a5-9b44-690f3cb2ad33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573822486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1573822486
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2246154480
Short name T358
Test name
Test status
Simulation time 110630489 ps
CPU time 1.26 seconds
Started Jun 05 05:15:03 PM PDT 24
Finished Jun 05 05:15:05 PM PDT 24
Peak memory 197060 kb
Host smart-4fa0da86-b8c1-448e-bc18-91a5f48ef50c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246154480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2246154480
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1818215054
Short name T301
Test name
Test status
Simulation time 491318751 ps
CPU time 1.46 seconds
Started Jun 05 05:15:13 PM PDT 24
Finished Jun 05 05:15:16 PM PDT 24
Peak memory 197952 kb
Host smart-bcd3b1f1-7078-4e65-bbe6-e63c21311eed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818215054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1818215054
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1883718900
Short name T422
Test name
Test status
Simulation time 41051479 ps
CPU time 1.27 seconds
Started Jun 05 05:15:06 PM PDT 24
Finished Jun 05 05:15:08 PM PDT 24
Peak memory 195556 kb
Host smart-3bd2c9c2-d557-4327-89a5-ae1d13025136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883718900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1883718900
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3923851409
Short name T268
Test name
Test status
Simulation time 280145561 ps
CPU time 1 seconds
Started Jun 05 05:15:02 PM PDT 24
Finished Jun 05 05:15:03 PM PDT 24
Peak memory 196716 kb
Host smart-d714643c-5458-4267-9be8-d8f9c3a57a10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923851409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3923851409
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1655049994
Short name T4
Test name
Test status
Simulation time 86708514927 ps
CPU time 136.21 seconds
Started Jun 05 05:15:11 PM PDT 24
Finished Jun 05 05:17:28 PM PDT 24
Peak memory 198296 kb
Host smart-8e145642-4dd3-446f-a8d3-1b7030d29656
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655049994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1655049994
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.893103969
Short name T459
Test name
Test status
Simulation time 46924280962 ps
CPU time 365.38 seconds
Started Jun 05 05:15:13 PM PDT 24
Finished Jun 05 05:21:19 PM PDT 24
Peak memory 198292 kb
Host smart-21fdf7b2-b03b-497f-a0fc-0d45a1834edb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=893103969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.893103969
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.4014251734
Short name T315
Test name
Test status
Simulation time 21797023 ps
CPU time 0.6 seconds
Started Jun 05 05:15:20 PM PDT 24
Finished Jun 05 05:15:21 PM PDT 24
Peak memory 194860 kb
Host smart-d6437104-e08c-4481-a71e-3df53cc6833d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014251734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.4014251734
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.491382462
Short name T638
Test name
Test status
Simulation time 55573884 ps
CPU time 0.81 seconds
Started Jun 05 05:15:15 PM PDT 24
Finished Jun 05 05:15:16 PM PDT 24
Peak memory 196148 kb
Host smart-3719220f-3d3a-4ebe-b3fb-12f95a85ff72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491382462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.491382462
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3502812253
Short name T616
Test name
Test status
Simulation time 356007766 ps
CPU time 10.23 seconds
Started Jun 05 05:15:12 PM PDT 24
Finished Jun 05 05:15:23 PM PDT 24
Peak memory 196572 kb
Host smart-607a6b14-99f5-414a-9e58-53bd9e60ef35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502812253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3502812253
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2510088776
Short name T277
Test name
Test status
Simulation time 734099705 ps
CPU time 1.05 seconds
Started Jun 05 05:15:14 PM PDT 24
Finished Jun 05 05:15:16 PM PDT 24
Peak memory 197968 kb
Host smart-c422b09e-822c-4c96-9cae-14d826f4a1ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510088776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2510088776
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.467835663
Short name T625
Test name
Test status
Simulation time 1242757957 ps
CPU time 1.45 seconds
Started Jun 05 05:15:10 PM PDT 24
Finished Jun 05 05:15:12 PM PDT 24
Peak memory 195860 kb
Host smart-9d877233-e57f-4bda-a4aa-4d269c302702
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467835663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.467835663
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4243955106
Short name T532
Test name
Test status
Simulation time 280227272 ps
CPU time 2.96 seconds
Started Jun 05 05:15:14 PM PDT 24
Finished Jun 05 05:15:17 PM PDT 24
Peak memory 198104 kb
Host smart-f2579af4-a7b0-4044-bf3b-5824abd13b87
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243955106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4243955106
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2556694417
Short name T299
Test name
Test status
Simulation time 63664873 ps
CPU time 1.85 seconds
Started Jun 05 05:15:12 PM PDT 24
Finished Jun 05 05:15:15 PM PDT 24
Peak memory 196960 kb
Host smart-f8bd64b1-05ab-42c3-a099-cd898b54c2f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556694417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2556694417
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1146792208
Short name T568
Test name
Test status
Simulation time 28526714 ps
CPU time 0.86 seconds
Started Jun 05 05:15:11 PM PDT 24
Finished Jun 05 05:15:12 PM PDT 24
Peak memory 195592 kb
Host smart-ad6b1485-4960-4ad4-b48c-369f9e4e5706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146792208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1146792208
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3424344135
Short name T133
Test name
Test status
Simulation time 19263406 ps
CPU time 0.68 seconds
Started Jun 05 05:15:15 PM PDT 24
Finished Jun 05 05:15:16 PM PDT 24
Peak memory 194356 kb
Host smart-610eec42-03a9-401a-8122-bb9c8687c54f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424344135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3424344135
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.263917253
Short name T467
Test name
Test status
Simulation time 427567967 ps
CPU time 2.06 seconds
Started Jun 05 05:15:14 PM PDT 24
Finished Jun 05 05:15:17 PM PDT 24
Peak memory 198076 kb
Host smart-6d7079e4-1e3a-4c2e-b530-c7f097e1e010
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263917253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.263917253
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3019620860
Short name T691
Test name
Test status
Simulation time 175214612 ps
CPU time 1.18 seconds
Started Jun 05 05:15:11 PM PDT 24
Finished Jun 05 05:15:13 PM PDT 24
Peak memory 196232 kb
Host smart-81b0525a-b476-4e16-8291-16ec72d7cbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019620860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3019620860
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1393030011
Short name T115
Test name
Test status
Simulation time 205668887 ps
CPU time 0.92 seconds
Started Jun 05 05:15:12 PM PDT 24
Finished Jun 05 05:15:13 PM PDT 24
Peak memory 195516 kb
Host smart-0768da4c-6284-4596-9434-9d6f9a9bf12e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393030011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1393030011
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.4174456291
Short name T681
Test name
Test status
Simulation time 5434840151 ps
CPU time 152.4 seconds
Started Jun 05 05:15:13 PM PDT 24
Finished Jun 05 05:17:46 PM PDT 24
Peak memory 198296 kb
Host smart-f4e4e4bf-271d-4c2b-8c41-b368405f6036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174456291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.4174456291
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1917371536
Short name T458
Test name
Test status
Simulation time 34768031517 ps
CPU time 839.9 seconds
Started Jun 05 05:15:12 PM PDT 24
Finished Jun 05 05:29:13 PM PDT 24
Peak memory 198292 kb
Host smart-a68396bd-7b15-45ec-a6c0-f8e1d8a09e88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1917371536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1917371536
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.968815009
Short name T597
Test name
Test status
Simulation time 42680091 ps
CPU time 0.6 seconds
Started Jun 05 05:15:26 PM PDT 24
Finished Jun 05 05:15:28 PM PDT 24
Peak memory 193980 kb
Host smart-03cfa65a-a833-42d7-b9cd-c24882223018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968815009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.968815009
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1254897669
Short name T264
Test name
Test status
Simulation time 125211649 ps
CPU time 0.85 seconds
Started Jun 05 05:15:20 PM PDT 24
Finished Jun 05 05:15:22 PM PDT 24
Peak memory 195472 kb
Host smart-28824677-0346-4d95-8ef1-021c17433122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254897669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1254897669
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2583077881
Short name T288
Test name
Test status
Simulation time 191378739 ps
CPU time 9.68 seconds
Started Jun 05 05:15:22 PM PDT 24
Finished Jun 05 05:15:32 PM PDT 24
Peak memory 197972 kb
Host smart-1bb2dbf6-02f0-4f25-bc4c-b959f3d9576d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583077881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2583077881
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2572528909
Short name T381
Test name
Test status
Simulation time 29715684 ps
CPU time 0.79 seconds
Started Jun 05 05:15:27 PM PDT 24
Finished Jun 05 05:15:28 PM PDT 24
Peak memory 195948 kb
Host smart-50380ee6-fc99-4df9-b9fb-ba35f4d88800
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572528909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2572528909
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3174218212
Short name T190
Test name
Test status
Simulation time 110278611 ps
CPU time 1.33 seconds
Started Jun 05 05:15:20 PM PDT 24
Finished Jun 05 05:15:22 PM PDT 24
Peak memory 198088 kb
Host smart-ac432ccc-fd52-4a27-9bbe-c83e387f9600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174218212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3174218212
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3368215823
Short name T486
Test name
Test status
Simulation time 94826500 ps
CPU time 3.74 seconds
Started Jun 05 05:15:21 PM PDT 24
Finished Jun 05 05:15:25 PM PDT 24
Peak memory 197308 kb
Host smart-b080816d-2de5-46ef-bc67-bc20583c09e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368215823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3368215823
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1555747455
Short name T14
Test name
Test status
Simulation time 106166961 ps
CPU time 1.06 seconds
Started Jun 05 05:15:22 PM PDT 24
Finished Jun 05 05:15:23 PM PDT 24
Peak memory 195728 kb
Host smart-fd356881-11bf-4f2b-bba1-bcb3e5699429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555747455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1555747455
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3759219282
Short name T471
Test name
Test status
Simulation time 71973278 ps
CPU time 0.74 seconds
Started Jun 05 05:15:20 PM PDT 24
Finished Jun 05 05:15:21 PM PDT 24
Peak memory 195164 kb
Host smart-fb22976e-41af-47c9-931e-0f6f7551dd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759219282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3759219282
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.100832493
Short name T478
Test name
Test status
Simulation time 39589691 ps
CPU time 0.95 seconds
Started Jun 05 05:15:22 PM PDT 24
Finished Jun 05 05:15:24 PM PDT 24
Peak memory 196052 kb
Host smart-89550520-f677-4dcc-bd01-30eb1915c8f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100832493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.100832493
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2931098375
Short name T697
Test name
Test status
Simulation time 34812466 ps
CPU time 1.63 seconds
Started Jun 05 05:15:20 PM PDT 24
Finished Jun 05 05:15:23 PM PDT 24
Peak memory 198016 kb
Host smart-3d16375a-dd07-42ff-9c00-48e4d3b774ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931098375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2931098375
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2801117690
Short name T284
Test name
Test status
Simulation time 30070598 ps
CPU time 0.99 seconds
Started Jun 05 05:15:21 PM PDT 24
Finished Jun 05 05:15:22 PM PDT 24
Peak memory 195820 kb
Host smart-edcdf132-67dd-4865-bd95-e432fd8fa1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801117690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2801117690
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1760827660
Short name T69
Test name
Test status
Simulation time 28939374 ps
CPU time 0.91 seconds
Started Jun 05 05:15:20 PM PDT 24
Finished Jun 05 05:15:21 PM PDT 24
Peak memory 197104 kb
Host smart-e8265248-2cf8-4fd7-8d8e-57c6120d9b6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760827660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1760827660
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2383741115
Short name T321
Test name
Test status
Simulation time 20606316184 ps
CPU time 118.4 seconds
Started Jun 05 05:15:27 PM PDT 24
Finished Jun 05 05:17:26 PM PDT 24
Peak memory 198280 kb
Host smart-76043a3c-8593-4884-9992-4a0f4de40e09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383741115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2383741115
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2809089592
Short name T374
Test name
Test status
Simulation time 15790675 ps
CPU time 0.64 seconds
Started Jun 05 05:15:29 PM PDT 24
Finished Jun 05 05:15:31 PM PDT 24
Peak memory 194596 kb
Host smart-a7326a99-dbb2-4950-acc0-4e9ae7525d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809089592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2809089592
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.498292339
Short name T235
Test name
Test status
Simulation time 62997187 ps
CPU time 0.73 seconds
Started Jun 05 05:15:27 PM PDT 24
Finished Jun 05 05:15:29 PM PDT 24
Peak memory 195384 kb
Host smart-74670127-4669-4a97-85e8-38887b872d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498292339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.498292339
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.808233577
Short name T383
Test name
Test status
Simulation time 636217586 ps
CPU time 18.06 seconds
Started Jun 05 05:15:29 PM PDT 24
Finished Jun 05 05:15:47 PM PDT 24
Peak memory 195576 kb
Host smart-a62ac54a-ec0f-42f1-89c1-90284b2fe3c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808233577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.808233577
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2251330892
Short name T276
Test name
Test status
Simulation time 40734023 ps
CPU time 0.65 seconds
Started Jun 05 05:15:26 PM PDT 24
Finished Jun 05 05:15:27 PM PDT 24
Peak memory 194636 kb
Host smart-aea5c26a-1221-43b0-a3aa-f98d4536a39f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251330892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2251330892
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3189568856
Short name T503
Test name
Test status
Simulation time 82252391 ps
CPU time 1.22 seconds
Started Jun 05 05:15:28 PM PDT 24
Finished Jun 05 05:15:30 PM PDT 24
Peak memory 196884 kb
Host smart-258c4173-585d-4e47-a541-1fe8132722de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189568856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3189568856
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3064553225
Short name T402
Test name
Test status
Simulation time 23122780 ps
CPU time 0.98 seconds
Started Jun 05 05:15:26 PM PDT 24
Finished Jun 05 05:15:27 PM PDT 24
Peak memory 196388 kb
Host smart-01318db4-8678-4174-9116-9c64dad4a5e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064553225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3064553225
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1710386116
Short name T541
Test name
Test status
Simulation time 339853573 ps
CPU time 1.24 seconds
Started Jun 05 05:15:31 PM PDT 24
Finished Jun 05 05:15:33 PM PDT 24
Peak memory 197332 kb
Host smart-2b7cec8a-d1d6-4b47-8abd-4e419c412fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710386116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1710386116
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4216787964
Short name T680
Test name
Test status
Simulation time 37879554 ps
CPU time 0.67 seconds
Started Jun 05 05:15:30 PM PDT 24
Finished Jun 05 05:15:31 PM PDT 24
Peak memory 194420 kb
Host smart-02156ce9-424f-4f8e-a0d3-c359a873d658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216787964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4216787964
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.839085870
Short name T200
Test name
Test status
Simulation time 277666410 ps
CPU time 1.28 seconds
Started Jun 05 05:15:27 PM PDT 24
Finished Jun 05 05:15:29 PM PDT 24
Peak memory 197076 kb
Host smart-73184178-2726-49fc-8cd8-d22ff5b50257
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839085870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.839085870
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2877264320
Short name T484
Test name
Test status
Simulation time 51944656 ps
CPU time 2.19 seconds
Started Jun 05 05:15:26 PM PDT 24
Finished Jun 05 05:15:29 PM PDT 24
Peak memory 198064 kb
Host smart-8bcbb7d6-0377-4fc9-bb6e-c384184d0844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877264320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2877264320
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.113604898
Short name T366
Test name
Test status
Simulation time 349626733 ps
CPU time 1.47 seconds
Started Jun 05 05:15:27 PM PDT 24
Finished Jun 05 05:15:29 PM PDT 24
Peak memory 196928 kb
Host smart-b543f2ba-336b-4de9-bd2d-1d48f0aba25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113604898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.113604898
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.4117785207
Short name T343
Test name
Test status
Simulation time 126820276 ps
CPU time 0.8 seconds
Started Jun 05 05:15:27 PM PDT 24
Finished Jun 05 05:15:29 PM PDT 24
Peak memory 195272 kb
Host smart-3574c571-747f-4267-97ab-bc506c90e644
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117785207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.4117785207
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1197222527
Short name T141
Test name
Test status
Simulation time 37332544346 ps
CPU time 144.5 seconds
Started Jun 05 05:15:27 PM PDT 24
Finished Jun 05 05:17:52 PM PDT 24
Peak memory 198164 kb
Host smart-91c9df35-e5ae-436f-b712-c1aeb6f95548
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197222527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1197222527
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1353428240
Short name T64
Test name
Test status
Simulation time 64642952114 ps
CPU time 750.65 seconds
Started Jun 05 05:15:30 PM PDT 24
Finished Jun 05 05:28:01 PM PDT 24
Peak memory 198132 kb
Host smart-5445c5c3-7ece-4658-a6e0-7b93582d4c2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1353428240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1353428240
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3929466286
Short name T217
Test name
Test status
Simulation time 49135033 ps
CPU time 0.62 seconds
Started Jun 05 05:14:12 PM PDT 24
Finished Jun 05 05:14:13 PM PDT 24
Peak memory 194868 kb
Host smart-ff89dfbf-6a72-4ed6-9633-0035dcba6928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929466286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3929466286
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1877388401
Short name T552
Test name
Test status
Simulation time 172713153 ps
CPU time 0.62 seconds
Started Jun 05 05:14:08 PM PDT 24
Finished Jun 05 05:14:10 PM PDT 24
Peak memory 194076 kb
Host smart-6e5cac16-23ad-4367-82c0-4a88ce3f0392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877388401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1877388401
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1205516520
Short name T586
Test name
Test status
Simulation time 1127294623 ps
CPU time 18.83 seconds
Started Jun 05 05:14:04 PM PDT 24
Finished Jun 05 05:14:23 PM PDT 24
Peak memory 197012 kb
Host smart-80476d4f-fbb2-4f59-b2d8-1998ec83e080
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205516520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1205516520
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.309257638
Short name T604
Test name
Test status
Simulation time 104048586 ps
CPU time 0.86 seconds
Started Jun 05 05:14:13 PM PDT 24
Finished Jun 05 05:14:15 PM PDT 24
Peak memory 195920 kb
Host smart-ff9a01e5-9d8b-4b99-a052-b76e3f99dcf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309257638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.309257638
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3725195118
Short name T645
Test name
Test status
Simulation time 76010133 ps
CPU time 0.9 seconds
Started Jun 05 05:14:08 PM PDT 24
Finished Jun 05 05:14:10 PM PDT 24
Peak memory 196600 kb
Host smart-7c31061a-bdb6-4dc1-a1f6-82b80b0aeecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725195118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3725195118
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2939141533
Short name T423
Test name
Test status
Simulation time 60784400 ps
CPU time 2.18 seconds
Started Jun 05 05:14:07 PM PDT 24
Finished Jun 05 05:14:10 PM PDT 24
Peak memory 198112 kb
Host smart-8b80ddb0-7ac1-4587-b1e4-4c2a50a498f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939141533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2939141533
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.297901931
Short name T72
Test name
Test status
Simulation time 77762495 ps
CPU time 1.12 seconds
Started Jun 05 05:14:07 PM PDT 24
Finished Jun 05 05:14:09 PM PDT 24
Peak memory 196408 kb
Host smart-9b08290a-34d3-464d-80a0-7814e1b58825
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297901931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.297901931
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3372737477
Short name T226
Test name
Test status
Simulation time 160767426 ps
CPU time 0.82 seconds
Started Jun 05 05:14:03 PM PDT 24
Finished Jun 05 05:14:05 PM PDT 24
Peak memory 195600 kb
Host smart-31765c01-b28e-414a-8db8-baa4c3c1a669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372737477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3372737477
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1894951530
Short name T535
Test name
Test status
Simulation time 31612801 ps
CPU time 0.86 seconds
Started Jun 05 05:14:07 PM PDT 24
Finished Jun 05 05:14:08 PM PDT 24
Peak memory 196672 kb
Host smart-a8abff9c-0137-466f-9419-acb57b2b4f8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894951530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1894951530
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3785576699
Short name T258
Test name
Test status
Simulation time 391225259 ps
CPU time 4.54 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:14:16 PM PDT 24
Peak memory 197880 kb
Host smart-6e3a5904-24f9-4875-a61c-4abcf069e4b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785576699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3785576699
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1864683106
Short name T53
Test name
Test status
Simulation time 217896773 ps
CPU time 0.92 seconds
Started Jun 05 05:14:09 PM PDT 24
Finished Jun 05 05:14:11 PM PDT 24
Peak memory 213852 kb
Host smart-7bdc10b1-19f1-432b-afbc-1a415a9267a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864683106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1864683106
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.168484511
Short name T327
Test name
Test status
Simulation time 74667078 ps
CPU time 1.11 seconds
Started Jun 05 05:14:05 PM PDT 24
Finished Jun 05 05:14:07 PM PDT 24
Peak memory 195572 kb
Host smart-94982f34-14ac-4dec-9e64-198a7d0802a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168484511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.168484511
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.741385535
Short name T175
Test name
Test status
Simulation time 49521989 ps
CPU time 0.99 seconds
Started Jun 05 05:14:02 PM PDT 24
Finished Jun 05 05:14:03 PM PDT 24
Peak memory 197100 kb
Host smart-e1886637-3fcd-49b8-ba9d-2f582f04e61d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741385535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.741385535
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1851566020
Short name T525
Test name
Test status
Simulation time 5447970452 ps
CPU time 135.45 seconds
Started Jun 05 05:14:09 PM PDT 24
Finished Jun 05 05:16:25 PM PDT 24
Peak memory 198248 kb
Host smart-e816828b-090b-45cc-ae40-85b06d30d933
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851566020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1851566020
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1907068577
Short name T281
Test name
Test status
Simulation time 47641286 ps
CPU time 0.63 seconds
Started Jun 05 05:15:38 PM PDT 24
Finished Jun 05 05:15:39 PM PDT 24
Peak memory 194164 kb
Host smart-43834b1e-b7f9-4c22-b4a8-d1d9b2414e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907068577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1907068577
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.438714285
Short name T322
Test name
Test status
Simulation time 56799975 ps
CPU time 0.9 seconds
Started Jun 05 05:15:26 PM PDT 24
Finished Jun 05 05:15:28 PM PDT 24
Peak memory 196040 kb
Host smart-12256928-0590-4d62-9e28-251f217bcf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438714285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.438714285
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2776811608
Short name T376
Test name
Test status
Simulation time 2488471433 ps
CPU time 21.17 seconds
Started Jun 05 05:15:40 PM PDT 24
Finished Jun 05 05:16:02 PM PDT 24
Peak memory 195848 kb
Host smart-b980c820-832f-4c71-913f-e1109f32de0c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776811608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2776811608
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.434524076
Short name T397
Test name
Test status
Simulation time 232863776 ps
CPU time 1.05 seconds
Started Jun 05 05:15:34 PM PDT 24
Finished Jun 05 05:15:36 PM PDT 24
Peak memory 196848 kb
Host smart-d78cbc16-5f73-46fb-8d5d-cb26b8f4cfbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434524076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.434524076
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2153690093
Short name T187
Test name
Test status
Simulation time 85512014 ps
CPU time 1.17 seconds
Started Jun 05 05:15:30 PM PDT 24
Finished Jun 05 05:15:32 PM PDT 24
Peak memory 196132 kb
Host smart-e50573c6-10cb-4b0f-982e-b78f5fdc41a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153690093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2153690093
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1524139137
Short name T404
Test name
Test status
Simulation time 91629279 ps
CPU time 1.2 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:15:38 PM PDT 24
Peak memory 197728 kb
Host smart-0f5f8903-a6d9-4736-8eb7-87e77f74a91f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524139137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1524139137
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3451273934
Short name T291
Test name
Test status
Simulation time 72585537 ps
CPU time 1.7 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:15:39 PM PDT 24
Peak memory 196084 kb
Host smart-5123abf5-6111-43e8-8b08-229d7583fd7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451273934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3451273934
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.411035535
Short name T566
Test name
Test status
Simulation time 229391569 ps
CPU time 1.32 seconds
Started Jun 05 05:15:29 PM PDT 24
Finished Jun 05 05:15:31 PM PDT 24
Peak memory 198064 kb
Host smart-2761c430-ef37-43e6-a4ec-34ca45a55493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411035535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.411035535
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3722623980
Short name T244
Test name
Test status
Simulation time 25979969 ps
CPU time 0.81 seconds
Started Jun 05 05:15:28 PM PDT 24
Finished Jun 05 05:15:30 PM PDT 24
Peak memory 195464 kb
Host smart-2b50ade9-1c38-499a-b767-5e5b836d2a3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722623980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3722623980
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2063231909
Short name T19
Test name
Test status
Simulation time 166226561 ps
CPU time 2.11 seconds
Started Jun 05 05:15:38 PM PDT 24
Finished Jun 05 05:15:41 PM PDT 24
Peak memory 198020 kb
Host smart-cfe9e12a-73f3-4cb9-a48e-23a71e9ce075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063231909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2063231909
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2070019956
Short name T242
Test name
Test status
Simulation time 158298752 ps
CPU time 1.14 seconds
Started Jun 05 05:15:27 PM PDT 24
Finished Jun 05 05:15:29 PM PDT 24
Peak memory 195648 kb
Host smart-c1034526-8130-45a4-a88f-57c8ba1461a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070019956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2070019956
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1864359229
Short name T132
Test name
Test status
Simulation time 108325238 ps
CPU time 0.87 seconds
Started Jun 05 05:15:29 PM PDT 24
Finished Jun 05 05:15:31 PM PDT 24
Peak memory 195512 kb
Host smart-6ab56903-ee12-436a-9bf9-9c6ae10d2b80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864359229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1864359229
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1293391183
Short name T437
Test name
Test status
Simulation time 11983205 ps
CPU time 0.62 seconds
Started Jun 05 05:15:44 PM PDT 24
Finished Jun 05 05:15:46 PM PDT 24
Peak memory 194160 kb
Host smart-2fea85ea-910c-4c4d-9f99-67410777719e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293391183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1293391183
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.4214621086
Short name T338
Test name
Test status
Simulation time 22281957 ps
CPU time 0.78 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:15:38 PM PDT 24
Peak memory 195312 kb
Host smart-ac70b0de-e489-4d33-9475-f67436a5e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214621086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.4214621086
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2255921794
Short name T688
Test name
Test status
Simulation time 609180201 ps
CPU time 22.21 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:15:59 PM PDT 24
Peak memory 196984 kb
Host smart-0f6f65e4-6277-49a2-a31c-75c1f0147ac6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255921794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2255921794
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1317357504
Short name T602
Test name
Test status
Simulation time 22881825 ps
CPU time 0.62 seconds
Started Jun 05 05:15:37 PM PDT 24
Finished Jun 05 05:15:38 PM PDT 24
Peak memory 194500 kb
Host smart-6ce2e580-b92e-4e30-9138-8e681ad28c8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317357504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1317357504
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4053530655
Short name T170
Test name
Test status
Simulation time 119309609 ps
CPU time 0.69 seconds
Started Jun 05 05:15:44 PM PDT 24
Finished Jun 05 05:15:46 PM PDT 24
Peak memory 194404 kb
Host smart-02d291e5-3494-4cc1-b66e-8d484dff5695
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053530655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4053530655
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1106431029
Short name T298
Test name
Test status
Simulation time 270710452 ps
CPU time 2.8 seconds
Started Jun 05 05:15:37 PM PDT 24
Finished Jun 05 05:15:41 PM PDT 24
Peak memory 198156 kb
Host smart-7239f643-a24c-404e-aade-4109ca88f9b6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106431029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1106431029
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1911879923
Short name T271
Test name
Test status
Simulation time 134951040 ps
CPU time 2.19 seconds
Started Jun 05 05:15:37 PM PDT 24
Finished Jun 05 05:15:40 PM PDT 24
Peak memory 197100 kb
Host smart-bf62c8d2-c093-4557-bdd4-8384948fb1f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911879923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1911879923
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2002137168
Short name T27
Test name
Test status
Simulation time 97749866 ps
CPU time 1.16 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:15:38 PM PDT 24
Peak memory 196804 kb
Host smart-de5b6555-303a-43d0-831d-525078594a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002137168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2002137168
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1557235841
Short name T312
Test name
Test status
Simulation time 48390305 ps
CPU time 1.02 seconds
Started Jun 05 05:15:37 PM PDT 24
Finished Jun 05 05:15:39 PM PDT 24
Peak memory 196628 kb
Host smart-9c696c33-6f02-4e65-924a-4d5e979d9a31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557235841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1557235841
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3884632785
Short name T571
Test name
Test status
Simulation time 449032936 ps
CPU time 5.29 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:15:42 PM PDT 24
Peak memory 198072 kb
Host smart-437feb04-f53c-4f60-8894-d1357ccf0cb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884632785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3884632785
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3649486429
Short name T263
Test name
Test status
Simulation time 117106818 ps
CPU time 1.21 seconds
Started Jun 05 05:15:35 PM PDT 24
Finished Jun 05 05:15:37 PM PDT 24
Peak memory 196356 kb
Host smart-626d2213-9bd7-44ad-ba87-04d3e1b70da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649486429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3649486429
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2995045377
Short name T353
Test name
Test status
Simulation time 240256174 ps
CPU time 1.13 seconds
Started Jun 05 05:15:35 PM PDT 24
Finished Jun 05 05:15:37 PM PDT 24
Peak memory 195580 kb
Host smart-7f4481f0-87a4-43a4-b120-28b0ab53ca94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995045377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2995045377
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.577726497
Short name T576
Test name
Test status
Simulation time 3691282862 ps
CPU time 48.51 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:16:26 PM PDT 24
Peak memory 198296 kb
Host smart-e9a43c22-c1e3-4dfb-b042-30dd3a688e58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577726497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.577726497
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1876668735
Short name T345
Test name
Test status
Simulation time 36542483 ps
CPU time 0.58 seconds
Started Jun 05 05:15:45 PM PDT 24
Finished Jun 05 05:15:46 PM PDT 24
Peak memory 194860 kb
Host smart-ce487b0f-f9c6-4a32-9f63-26e46c1dfbdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876668735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1876668735
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1072374962
Short name T455
Test name
Test status
Simulation time 102390173 ps
CPU time 0.83 seconds
Started Jun 05 05:15:44 PM PDT 24
Finished Jun 05 05:15:46 PM PDT 24
Peak memory 195428 kb
Host smart-3ada6d88-c390-4d19-80dd-502a5d3a6c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072374962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1072374962
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1057160333
Short name T120
Test name
Test status
Simulation time 3938318380 ps
CPU time 27.17 seconds
Started Jun 05 05:15:42 PM PDT 24
Finished Jun 05 05:16:11 PM PDT 24
Peak memory 196684 kb
Host smart-f7543fcc-d902-437b-a4cc-d17639972d22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057160333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1057160333
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3781426427
Short name T389
Test name
Test status
Simulation time 170740204 ps
CPU time 0.94 seconds
Started Jun 05 05:15:44 PM PDT 24
Finished Jun 05 05:15:46 PM PDT 24
Peak memory 197992 kb
Host smart-2d5f5625-ee21-4c6a-affb-1600d35079eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781426427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3781426427
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.756161273
Short name T195
Test name
Test status
Simulation time 51407814 ps
CPU time 1.39 seconds
Started Jun 05 05:15:41 PM PDT 24
Finished Jun 05 05:15:43 PM PDT 24
Peak memory 197204 kb
Host smart-c797cd5f-2b28-4f57-92be-bc811b53a0c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756161273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.756161273
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2703773495
Short name T447
Test name
Test status
Simulation time 169986313 ps
CPU time 3.76 seconds
Started Jun 05 05:15:49 PM PDT 24
Finished Jun 05 05:15:54 PM PDT 24
Peak memory 198088 kb
Host smart-86e34411-deff-49bd-be66-c51919632652
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703773495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2703773495
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.418658094
Short name T499
Test name
Test status
Simulation time 156697454 ps
CPU time 3.49 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:15:48 PM PDT 24
Peak memory 198048 kb
Host smart-2764945f-eeb5-4406-a3b7-34a86979d58d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418658094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
418658094
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2250413448
Short name T693
Test name
Test status
Simulation time 99978080 ps
CPU time 0.68 seconds
Started Jun 05 05:15:41 PM PDT 24
Finished Jun 05 05:15:43 PM PDT 24
Peak memory 194368 kb
Host smart-c652c2d9-9c87-4144-afbf-68d05c8a5f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250413448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2250413448
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.802786752
Short name T391
Test name
Test status
Simulation time 583326887 ps
CPU time 1.07 seconds
Started Jun 05 05:15:42 PM PDT 24
Finished Jun 05 05:15:45 PM PDT 24
Peak memory 195900 kb
Host smart-67fbf67a-ad81-44d2-a433-9115e82c9e6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802786752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.802786752
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.177530247
Short name T428
Test name
Test status
Simulation time 2134313881 ps
CPU time 6.15 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:15:50 PM PDT 24
Peak memory 197976 kb
Host smart-ee10275c-cc7a-4320-8f01-b192926c5906
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177530247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.177530247
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.4134055738
Short name T60
Test name
Test status
Simulation time 40968376 ps
CPU time 0.79 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:15:45 PM PDT 24
Peak memory 195328 kb
Host smart-52c2bf1f-0b32-4367-9416-57e09ec13eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134055738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.4134055738
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3259700039
Short name T588
Test name
Test status
Simulation time 601058924 ps
CPU time 1.56 seconds
Started Jun 05 05:15:45 PM PDT 24
Finished Jun 05 05:15:47 PM PDT 24
Peak memory 198028 kb
Host smart-b3304bc9-3b5c-4793-abc4-6c634dab71dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259700039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3259700039
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1874354758
Short name T214
Test name
Test status
Simulation time 25079108336 ps
CPU time 141.61 seconds
Started Jun 05 05:15:49 PM PDT 24
Finished Jun 05 05:18:12 PM PDT 24
Peak memory 197940 kb
Host smart-1af3ac63-f399-466e-821a-808c191c92b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874354758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1874354758
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1659441383
Short name T348
Test name
Test status
Simulation time 30535437 ps
CPU time 0.56 seconds
Started Jun 05 05:15:51 PM PDT 24
Finished Jun 05 05:15:52 PM PDT 24
Peak memory 193960 kb
Host smart-485f69f2-890b-4626-8d5d-13b6fd349f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659441383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1659441383
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3565424348
Short name T119
Test name
Test status
Simulation time 160967435 ps
CPU time 0.88 seconds
Started Jun 05 05:16:13 PM PDT 24
Finished Jun 05 05:16:15 PM PDT 24
Peak memory 195988 kb
Host smart-23804db7-ccef-4610-a23e-aefb0fe86161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565424348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3565424348
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2985456575
Short name T621
Test name
Test status
Simulation time 300955272 ps
CPU time 3.95 seconds
Started Jun 05 05:16:01 PM PDT 24
Finished Jun 05 05:16:05 PM PDT 24
Peak memory 195780 kb
Host smart-58d8c14e-cf4b-4321-906f-9053df626323
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985456575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2985456575
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2123357289
Short name T702
Test name
Test status
Simulation time 198725598 ps
CPU time 1.01 seconds
Started Jun 05 05:15:49 PM PDT 24
Finished Jun 05 05:15:51 PM PDT 24
Peak memory 196440 kb
Host smart-b5f8eeca-49d8-47cd-bbd8-a696a02c9381
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123357289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2123357289
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.515864672
Short name T373
Test name
Test status
Simulation time 63529332 ps
CPU time 1.08 seconds
Started Jun 05 05:15:44 PM PDT 24
Finished Jun 05 05:15:46 PM PDT 24
Peak memory 196024 kb
Host smart-6299ab25-afc2-4409-8fde-cd57d854e5f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515864672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.515864672
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.564190867
Short name T390
Test name
Test status
Simulation time 316465728 ps
CPU time 3.58 seconds
Started Jun 05 05:15:51 PM PDT 24
Finished Jun 05 05:15:55 PM PDT 24
Peak memory 198096 kb
Host smart-3f26ee50-31bc-45a6-85a1-82bfceee039d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564190867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.564190867
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2846671681
Short name T123
Test name
Test status
Simulation time 265453637 ps
CPU time 2.18 seconds
Started Jun 05 05:15:49 PM PDT 24
Finished Jun 05 05:15:52 PM PDT 24
Peak memory 197128 kb
Host smart-359b901e-c0b2-477b-9d10-e9589ef43ee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846671681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2846671681
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1214786023
Short name T359
Test name
Test status
Simulation time 647092063 ps
CPU time 1.25 seconds
Started Jun 05 05:15:42 PM PDT 24
Finished Jun 05 05:15:43 PM PDT 24
Peak memory 197064 kb
Host smart-308ac035-c545-4dd0-b848-73b251fdd6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214786023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1214786023
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2466841303
Short name T709
Test name
Test status
Simulation time 52322956 ps
CPU time 0.72 seconds
Started Jun 05 05:15:49 PM PDT 24
Finished Jun 05 05:15:51 PM PDT 24
Peak memory 194048 kb
Host smart-cbbce707-902e-4106-b465-f09a677bb942
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466841303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2466841303
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.713521994
Short name T633
Test name
Test status
Simulation time 411660616 ps
CPU time 3.63 seconds
Started Jun 05 05:15:53 PM PDT 24
Finished Jun 05 05:15:57 PM PDT 24
Peak memory 198036 kb
Host smart-d293cac9-d83a-4a64-a44c-7a213328126a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713521994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.713521994
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3004446619
Short name T514
Test name
Test status
Simulation time 475487450 ps
CPU time 1.02 seconds
Started Jun 05 05:15:45 PM PDT 24
Finished Jun 05 05:15:47 PM PDT 24
Peak memory 195900 kb
Host smart-f7c82dad-bf8a-4a10-9ae1-cd5459e5f743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004446619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3004446619
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.528460445
Short name T619
Test name
Test status
Simulation time 393105470 ps
CPU time 1.17 seconds
Started Jun 05 05:15:42 PM PDT 24
Finished Jun 05 05:15:43 PM PDT 24
Peak memory 196288 kb
Host smart-8e69e86b-a280-449b-b42a-8ca6b53574a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528460445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.528460445
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2975097628
Short name T515
Test name
Test status
Simulation time 1458630902 ps
CPU time 21.26 seconds
Started Jun 05 05:15:51 PM PDT 24
Finished Jun 05 05:16:13 PM PDT 24
Peak memory 198116 kb
Host smart-d0beb8e1-11d6-4317-8006-532cf5219b5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975097628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2975097628
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1237859513
Short name T591
Test name
Test status
Simulation time 33273117 ps
CPU time 0.57 seconds
Started Jun 05 05:15:59 PM PDT 24
Finished Jun 05 05:16:00 PM PDT 24
Peak memory 194600 kb
Host smart-e219b786-8bf5-4a49-b2cb-801690ede3ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237859513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1237859513
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2635032700
Short name T654
Test name
Test status
Simulation time 106224836 ps
CPU time 0.76 seconds
Started Jun 05 05:15:50 PM PDT 24
Finished Jun 05 05:15:51 PM PDT 24
Peak memory 196140 kb
Host smart-028e0834-3174-4820-8fac-4262b46581bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635032700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2635032700
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3029261626
Short name T118
Test name
Test status
Simulation time 520552620 ps
CPU time 7.13 seconds
Started Jun 05 05:15:50 PM PDT 24
Finished Jun 05 05:15:58 PM PDT 24
Peak memory 195568 kb
Host smart-2044788d-0c44-4e4e-a1c4-e48a5dc86f79
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029261626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3029261626
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1002551894
Short name T73
Test name
Test status
Simulation time 51003120 ps
CPU time 0.89 seconds
Started Jun 05 05:15:52 PM PDT 24
Finished Jun 05 05:15:54 PM PDT 24
Peak memory 196832 kb
Host smart-57734b82-0a11-4390-9a61-bda823bddd5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002551894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1002551894
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2103287771
Short name T671
Test name
Test status
Simulation time 84683650 ps
CPU time 0.81 seconds
Started Jun 05 05:15:50 PM PDT 24
Finished Jun 05 05:15:51 PM PDT 24
Peak memory 195588 kb
Host smart-932e7f83-b7c4-4590-9865-698e0adff156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103287771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2103287771
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.580290644
Short name T609
Test name
Test status
Simulation time 94548565 ps
CPU time 3.57 seconds
Started Jun 05 05:15:48 PM PDT 24
Finished Jun 05 05:15:52 PM PDT 24
Peak memory 198104 kb
Host smart-8e1f160d-c79d-42fa-825a-ded82b971c79
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580290644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.580290644
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.646797210
Short name T452
Test name
Test status
Simulation time 299484620 ps
CPU time 1.7 seconds
Started Jun 05 05:15:52 PM PDT 24
Finished Jun 05 05:15:55 PM PDT 24
Peak memory 196176 kb
Host smart-9f47d25b-c895-407b-a6ac-d1bfab84dfe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646797210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
646797210
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3963867182
Short name T305
Test name
Test status
Simulation time 133880447 ps
CPU time 0.98 seconds
Started Jun 05 05:16:01 PM PDT 24
Finished Jun 05 05:16:02 PM PDT 24
Peak memory 196808 kb
Host smart-77a35656-a924-4a90-b86b-8d3a2633dd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963867182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3963867182
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.333055719
Short name T521
Test name
Test status
Simulation time 68501838 ps
CPU time 0.84 seconds
Started Jun 05 05:15:49 PM PDT 24
Finished Jun 05 05:15:50 PM PDT 24
Peak memory 196676 kb
Host smart-c92d9644-0b96-43da-a612-fb02f03f01c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333055719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.333055719
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.502596485
Short name T240
Test name
Test status
Simulation time 2132430771 ps
CPU time 2.19 seconds
Started Jun 05 05:15:48 PM PDT 24
Finished Jun 05 05:15:51 PM PDT 24
Peak memory 198020 kb
Host smart-6f23bfc0-45b3-4278-a7a5-e6b9b24f8791
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502596485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.502596485
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2110945186
Short name T479
Test name
Test status
Simulation time 55956353 ps
CPU time 1.48 seconds
Started Jun 05 05:15:50 PM PDT 24
Finished Jun 05 05:15:52 PM PDT 24
Peak memory 196352 kb
Host smart-2e721f33-976d-47e1-8216-837781355f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110945186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2110945186
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1877031488
Short name T357
Test name
Test status
Simulation time 208012528 ps
CPU time 1.67 seconds
Started Jun 05 05:15:51 PM PDT 24
Finished Jun 05 05:15:53 PM PDT 24
Peak memory 195644 kb
Host smart-73af832d-41ba-43c8-b593-5f6ff72f99f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877031488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1877031488
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2982640625
Short name T2
Test name
Test status
Simulation time 13668530033 ps
CPU time 40.8 seconds
Started Jun 05 05:15:59 PM PDT 24
Finished Jun 05 05:16:41 PM PDT 24
Peak memory 198240 kb
Host smart-4e4d410d-0da5-4b00-8582-3a6e661508ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982640625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2982640625
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.829091261
Short name T57
Test name
Test status
Simulation time 12105830 ps
CPU time 0.61 seconds
Started Jun 05 05:16:08 PM PDT 24
Finished Jun 05 05:16:10 PM PDT 24
Peak memory 194836 kb
Host smart-ec1b6fcc-0e0a-41c4-8102-4c806918a01b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829091261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.829091261
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2604763006
Short name T396
Test name
Test status
Simulation time 158524765 ps
CPU time 1.02 seconds
Started Jun 05 05:15:57 PM PDT 24
Finished Jun 05 05:15:59 PM PDT 24
Peak memory 196608 kb
Host smart-b86efbaa-1aa9-4989-b325-bc15478a4355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604763006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2604763006
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.798947731
Short name T22
Test name
Test status
Simulation time 480551675 ps
CPU time 8.87 seconds
Started Jun 05 05:15:59 PM PDT 24
Finished Jun 05 05:16:08 PM PDT 24
Peak memory 197032 kb
Host smart-a01010b2-0c1b-4b14-a687-c3c4ee553169
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798947731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.798947731
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2925937907
Short name T464
Test name
Test status
Simulation time 26858206 ps
CPU time 0.63 seconds
Started Jun 05 05:15:57 PM PDT 24
Finished Jun 05 05:15:58 PM PDT 24
Peak memory 194732 kb
Host smart-6874a3b4-7f5e-4b6e-bea0-2915c035fbc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925937907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2925937907
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2378431043
Short name T311
Test name
Test status
Simulation time 1231183208 ps
CPU time 1.2 seconds
Started Jun 05 05:16:02 PM PDT 24
Finished Jun 05 05:16:04 PM PDT 24
Peak memory 196192 kb
Host smart-a5b8d672-de43-4691-8db1-d745f9317215
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378431043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2378431043
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1930881191
Short name T71
Test name
Test status
Simulation time 213293653 ps
CPU time 2.47 seconds
Started Jun 05 05:15:58 PM PDT 24
Finished Jun 05 05:16:02 PM PDT 24
Peak memory 198096 kb
Host smart-9e5ac1fe-2af8-4ca0-aea3-3d9bb99e9964
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930881191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1930881191
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.734953497
Short name T230
Test name
Test status
Simulation time 67959026 ps
CPU time 1.54 seconds
Started Jun 05 05:15:59 PM PDT 24
Finished Jun 05 05:16:02 PM PDT 24
Peak memory 196560 kb
Host smart-fa223db4-6e29-418e-82d3-8451abd6cc31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734953497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
734953497
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1849136809
Short name T316
Test name
Test status
Simulation time 31412618 ps
CPU time 0.68 seconds
Started Jun 05 05:15:58 PM PDT 24
Finished Jun 05 05:16:00 PM PDT 24
Peak memory 194456 kb
Host smart-0f5f6d51-d6ff-40c1-8ebc-bda774377be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849136809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1849136809
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1551759170
Short name T573
Test name
Test status
Simulation time 279206693 ps
CPU time 1.35 seconds
Started Jun 05 05:16:03 PM PDT 24
Finished Jun 05 05:16:05 PM PDT 24
Peak memory 197048 kb
Host smart-bfac40e4-1cda-4a8f-9d31-359eaba528df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551759170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1551759170
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.404396921
Short name T457
Test name
Test status
Simulation time 459922563 ps
CPU time 5.88 seconds
Started Jun 05 05:16:02 PM PDT 24
Finished Jun 05 05:16:09 PM PDT 24
Peak memory 197956 kb
Host smart-0f743642-8fac-431a-959b-31ee99cd114a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404396921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.404396921
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.181637396
Short name T325
Test name
Test status
Simulation time 269652605 ps
CPU time 1.02 seconds
Started Jun 05 05:16:02 PM PDT 24
Finished Jun 05 05:16:03 PM PDT 24
Peak memory 197232 kb
Host smart-22348015-eba9-46fe-8d42-a901a1971b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181637396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.181637396
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2769138583
Short name T462
Test name
Test status
Simulation time 102192049 ps
CPU time 1.05 seconds
Started Jun 05 05:15:59 PM PDT 24
Finished Jun 05 05:16:00 PM PDT 24
Peak memory 195948 kb
Host smart-8b13d3db-0fe5-4cab-a152-eb341652ef0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769138583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2769138583
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3749410389
Short name T5
Test name
Test status
Simulation time 143750836861 ps
CPU time 196.26 seconds
Started Jun 05 05:15:57 PM PDT 24
Finished Jun 05 05:19:14 PM PDT 24
Peak memory 198240 kb
Host smart-65a17c9c-4814-4706-b7fe-2e386e2536d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749410389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3749410389
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1452163601
Short name T62
Test name
Test status
Simulation time 17980859863 ps
CPU time 425.95 seconds
Started Jun 05 05:16:06 PM PDT 24
Finished Jun 05 05:23:12 PM PDT 24
Peak memory 198288 kb
Host smart-80b43bfc-2528-4364-97c5-4d18e08bf1c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1452163601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1452163601
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.629545566
Short name T598
Test name
Test status
Simulation time 22304440 ps
CPU time 0.59 seconds
Started Jun 05 05:16:16 PM PDT 24
Finished Jun 05 05:16:17 PM PDT 24
Peak memory 194668 kb
Host smart-90bbbe57-2ad9-4acb-adda-5d57e4d95f56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629545566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.629545566
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.45568245
Short name T228
Test name
Test status
Simulation time 139236108 ps
CPU time 0.72 seconds
Started Jun 05 05:16:08 PM PDT 24
Finished Jun 05 05:16:09 PM PDT 24
Peak memory 195316 kb
Host smart-cc76d84f-1902-4614-a0bb-75e67906c20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45568245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.45568245
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3881434417
Short name T527
Test name
Test status
Simulation time 3027387204 ps
CPU time 20.75 seconds
Started Jun 05 05:16:17 PM PDT 24
Finished Jun 05 05:16:38 PM PDT 24
Peak memory 196700 kb
Host smart-3aecd131-788e-46c1-822b-89772a0c17be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881434417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3881434417
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2197986848
Short name T221
Test name
Test status
Simulation time 142732304 ps
CPU time 0.73 seconds
Started Jun 05 05:16:14 PM PDT 24
Finished Jun 05 05:16:16 PM PDT 24
Peak memory 195544 kb
Host smart-8be83808-1295-4908-bc81-c59370354f71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197986848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2197986848
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.473188392
Short name T386
Test name
Test status
Simulation time 258852681 ps
CPU time 1.14 seconds
Started Jun 05 05:16:13 PM PDT 24
Finished Jun 05 05:16:15 PM PDT 24
Peak memory 196788 kb
Host smart-3ea4ae33-f119-4caa-93d2-17ee7e9dfd1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473188392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.473188392
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1796335477
Short name T529
Test name
Test status
Simulation time 44962255 ps
CPU time 1.08 seconds
Started Jun 05 05:16:15 PM PDT 24
Finished Jun 05 05:16:17 PM PDT 24
Peak memory 197656 kb
Host smart-16c7570d-a671-43d3-a929-301901b5d6f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796335477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1796335477
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1336238826
Short name T607
Test name
Test status
Simulation time 155023570 ps
CPU time 3.54 seconds
Started Jun 05 05:16:14 PM PDT 24
Finished Jun 05 05:16:18 PM PDT 24
Peak memory 198108 kb
Host smart-5a9bc84a-2794-4845-b769-e3c297398e7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336238826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1336238826
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1326966422
Short name T243
Test name
Test status
Simulation time 112097008 ps
CPU time 1.11 seconds
Started Jun 05 05:16:07 PM PDT 24
Finished Jun 05 05:16:09 PM PDT 24
Peak memory 195828 kb
Host smart-1349575e-f567-41a7-b900-664697e772b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326966422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1326966422
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1558491349
Short name T590
Test name
Test status
Simulation time 413951972 ps
CPU time 1.36 seconds
Started Jun 05 05:16:07 PM PDT 24
Finished Jun 05 05:16:09 PM PDT 24
Peak memory 198060 kb
Host smart-a3189b19-55b2-4927-a5c3-045a8102eb17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558491349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1558491349
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.857017553
Short name T626
Test name
Test status
Simulation time 472096665 ps
CPU time 4.49 seconds
Started Jun 05 05:16:15 PM PDT 24
Finished Jun 05 05:16:20 PM PDT 24
Peak memory 198032 kb
Host smart-8c5ace4b-b1e1-45ba-9656-1ae707f9a14f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857017553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.857017553
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3260650497
Short name T278
Test name
Test status
Simulation time 265085018 ps
CPU time 1.16 seconds
Started Jun 05 05:16:06 PM PDT 24
Finished Jun 05 05:16:08 PM PDT 24
Peak memory 196836 kb
Host smart-2707aeb1-a32e-4f18-ad24-15cee300bac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260650497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3260650497
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1998768792
Short name T549
Test name
Test status
Simulation time 67202712 ps
CPU time 1.1 seconds
Started Jun 05 05:16:07 PM PDT 24
Finished Jun 05 05:16:08 PM PDT 24
Peak memory 195592 kb
Host smart-5aad5392-0257-4587-a359-bab2c0b9b4ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998768792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1998768792
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2595245657
Short name T640
Test name
Test status
Simulation time 48742254400 ps
CPU time 204.92 seconds
Started Jun 05 05:16:13 PM PDT 24
Finished Jun 05 05:19:39 PM PDT 24
Peak memory 198296 kb
Host smart-4f944678-480e-44e9-b7bd-deb29edcc8d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595245657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2595245657
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.3902507663
Short name T66
Test name
Test status
Simulation time 82738597201 ps
CPU time 646.57 seconds
Started Jun 05 05:16:14 PM PDT 24
Finished Jun 05 05:27:01 PM PDT 24
Peak memory 198276 kb
Host smart-b690e515-406f-451c-bc7a-9fce8b205d88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3902507663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.3902507663
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2119233310
Short name T666
Test name
Test status
Simulation time 31739542 ps
CPU time 0.59 seconds
Started Jun 05 05:16:24 PM PDT 24
Finished Jun 05 05:16:25 PM PDT 24
Peak memory 193888 kb
Host smart-e385e1e4-ac45-45f6-9683-716994144294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119233310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2119233310
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.149064354
Short name T394
Test name
Test status
Simulation time 69703902 ps
CPU time 0.8 seconds
Started Jun 05 05:16:13 PM PDT 24
Finished Jun 05 05:16:15 PM PDT 24
Peak memory 196128 kb
Host smart-f39084c2-e2c5-46a8-8e42-4e9d524ff030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149064354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.149064354
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1283774105
Short name T270
Test name
Test status
Simulation time 418998223 ps
CPU time 15.13 seconds
Started Jun 05 05:16:24 PM PDT 24
Finished Jun 05 05:16:40 PM PDT 24
Peak memory 196836 kb
Host smart-4c76a229-61d9-4fc6-8a59-81574f16f0ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283774105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1283774105
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3757979100
Short name T310
Test name
Test status
Simulation time 28019510 ps
CPU time 0.69 seconds
Started Jun 05 05:16:21 PM PDT 24
Finished Jun 05 05:16:23 PM PDT 24
Peak memory 194776 kb
Host smart-5536eb7b-325c-4c82-99db-7eb31443c10d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757979100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3757979100
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2403483981
Short name T393
Test name
Test status
Simulation time 187331883 ps
CPU time 0.91 seconds
Started Jun 05 05:16:13 PM PDT 24
Finished Jun 05 05:16:15 PM PDT 24
Peak memory 196868 kb
Host smart-1665c3d5-445c-4ff7-b130-ee9889ce40ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403483981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2403483981
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2903229542
Short name T533
Test name
Test status
Simulation time 134161137 ps
CPU time 1.65 seconds
Started Jun 05 05:16:23 PM PDT 24
Finished Jun 05 05:16:25 PM PDT 24
Peak memory 196544 kb
Host smart-e5b87c31-daf5-49de-998f-e1eddccdc76e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903229542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2903229542
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.53148161
Short name T585
Test name
Test status
Simulation time 42374767 ps
CPU time 0.93 seconds
Started Jun 05 05:16:22 PM PDT 24
Finished Jun 05 05:16:24 PM PDT 24
Peak memory 195516 kb
Host smart-a4df8a2a-0a9e-4e6e-8d7d-a953e5c76ac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53148161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.53148161
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.867033259
Short name T171
Test name
Test status
Simulation time 257901754 ps
CPU time 1.2 seconds
Started Jun 05 05:16:15 PM PDT 24
Finished Jun 05 05:16:17 PM PDT 24
Peak memory 196876 kb
Host smart-c33f5de4-6d0d-4a12-97a2-2ef9d9b22c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867033259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.867033259
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3810298797
Short name T293
Test name
Test status
Simulation time 237308454 ps
CPU time 1.2 seconds
Started Jun 05 05:16:15 PM PDT 24
Finished Jun 05 05:16:17 PM PDT 24
Peak memory 196580 kb
Host smart-5046c532-a107-49f1-8b35-9faf0acb6882
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810298797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3810298797
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1522100126
Short name T371
Test name
Test status
Simulation time 336008387 ps
CPU time 5.5 seconds
Started Jun 05 05:16:22 PM PDT 24
Finished Jun 05 05:16:29 PM PDT 24
Peak memory 198048 kb
Host smart-21000adb-d493-4100-83b0-d75652ab54ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522100126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1522100126
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2329032168
Short name T174
Test name
Test status
Simulation time 38245213 ps
CPU time 1.24 seconds
Started Jun 05 05:16:14 PM PDT 24
Finished Jun 05 05:16:15 PM PDT 24
Peak memory 196820 kb
Host smart-6174ad91-09ef-4706-ad3e-d17e3a8ccc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329032168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2329032168
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3658105088
Short name T508
Test name
Test status
Simulation time 132677017 ps
CPU time 1.12 seconds
Started Jun 05 05:16:15 PM PDT 24
Finished Jun 05 05:16:16 PM PDT 24
Peak memory 195688 kb
Host smart-431dac84-c957-46ee-b2f5-1c05a5cd81ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658105088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3658105088
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3475853455
Short name T158
Test name
Test status
Simulation time 5617497984 ps
CPU time 32.1 seconds
Started Jun 05 05:16:21 PM PDT 24
Finished Jun 05 05:16:54 PM PDT 24
Peak memory 198268 kb
Host smart-fbe30b14-e227-4a9e-b59c-0d35666921bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475853455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3475853455
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.4130852052
Short name T716
Test name
Test status
Simulation time 50788758167 ps
CPU time 1066.28 seconds
Started Jun 05 05:16:23 PM PDT 24
Finished Jun 05 05:34:10 PM PDT 24
Peak memory 198276 kb
Host smart-688a86eb-84e5-4148-a933-42cb62318888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4130852052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.4130852052
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3603331453
Short name T509
Test name
Test status
Simulation time 54005061 ps
CPU time 0.6 seconds
Started Jun 05 05:16:34 PM PDT 24
Finished Jun 05 05:16:35 PM PDT 24
Peak memory 193976 kb
Host smart-9bbbf1b0-4a3d-4d65-a91d-66e7b39ec412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603331453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3603331453
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2491364148
Short name T306
Test name
Test status
Simulation time 19861446 ps
CPU time 0.74 seconds
Started Jun 05 05:16:36 PM PDT 24
Finished Jun 05 05:16:37 PM PDT 24
Peak memory 194956 kb
Host smart-f9b9664d-41d3-44c3-8e6c-d37fc6bd126a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491364148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2491364148
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1517284903
Short name T262
Test name
Test status
Simulation time 339697741 ps
CPU time 16.88 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:16:50 PM PDT 24
Peak memory 196976 kb
Host smart-c54b4771-bd20-4004-bf3d-2dba9f7f1ca7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517284903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1517284903
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.680597947
Short name T420
Test name
Test status
Simulation time 86045425 ps
CPU time 0.64 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:16:34 PM PDT 24
Peak memory 194588 kb
Host smart-87748902-4094-4660-a85f-9eb35800f071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680597947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.680597947
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2607069056
Short name T421
Test name
Test status
Simulation time 200843647 ps
CPU time 1.2 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:16:35 PM PDT 24
Peak memory 196196 kb
Host smart-d8f2c5c4-9dcf-4189-b8d8-2febda100f2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607069056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2607069056
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1803050120
Short name T711
Test name
Test status
Simulation time 1135101807 ps
CPU time 3.38 seconds
Started Jun 05 05:16:41 PM PDT 24
Finished Jun 05 05:16:45 PM PDT 24
Peak memory 198100 kb
Host smart-3a24a595-abcb-4ca5-bbb3-350f1b1a7734
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803050120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1803050120
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1124056743
Short name T148
Test name
Test status
Simulation time 274936646 ps
CPU time 2.41 seconds
Started Jun 05 05:16:34 PM PDT 24
Finished Jun 05 05:16:37 PM PDT 24
Peak memory 195900 kb
Host smart-ca760d52-e8c7-49bd-b40b-c66e292a3485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124056743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1124056743
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.225772693
Short name T212
Test name
Test status
Simulation time 38527073 ps
CPU time 1.21 seconds
Started Jun 05 05:16:35 PM PDT 24
Finished Jun 05 05:16:37 PM PDT 24
Peak memory 196964 kb
Host smart-22669e23-9fe6-47c8-9e5a-49825023a85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225772693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.225772693
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1411443405
Short name T260
Test name
Test status
Simulation time 66022764 ps
CPU time 0.68 seconds
Started Jun 05 05:16:34 PM PDT 24
Finished Jun 05 05:16:35 PM PDT 24
Peak memory 195068 kb
Host smart-3042d742-d04c-486a-9d50-f875c8f5723e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411443405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1411443405
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1531407845
Short name T225
Test name
Test status
Simulation time 466904899 ps
CPU time 3.04 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:16:37 PM PDT 24
Peak memory 198040 kb
Host smart-182fa576-4ca7-4263-896d-7619bc02741f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531407845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1531407845
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3933149016
Short name T448
Test name
Test status
Simulation time 57454830 ps
CPU time 1.07 seconds
Started Jun 05 05:16:23 PM PDT 24
Finished Jun 05 05:16:25 PM PDT 24
Peak memory 195656 kb
Host smart-2b3cd1e8-7af6-4baf-b7f8-cc0430e6f5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933149016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3933149016
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1414738630
Short name T676
Test name
Test status
Simulation time 71687731 ps
CPU time 0.88 seconds
Started Jun 05 05:16:32 PM PDT 24
Finished Jun 05 05:16:33 PM PDT 24
Peak memory 195504 kb
Host smart-e7d47054-cdb9-4b24-aa80-ec61e669f677
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414738630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1414738630
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3135691085
Short name T669
Test name
Test status
Simulation time 19263814059 ps
CPU time 75.78 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:17:49 PM PDT 24
Peak memory 198164 kb
Host smart-28b0ff71-f62d-4699-9bd5-9ff13628fe8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135691085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3135691085
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2245906654
Short name T601
Test name
Test status
Simulation time 94408813 ps
CPU time 0.62 seconds
Started Jun 05 05:16:38 PM PDT 24
Finished Jun 05 05:16:39 PM PDT 24
Peak memory 193952 kb
Host smart-a4b31811-4f25-40c9-81fc-f0d010266e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245906654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2245906654
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2198331803
Short name T23
Test name
Test status
Simulation time 38922813 ps
CPU time 0.94 seconds
Started Jun 05 05:16:37 PM PDT 24
Finished Jun 05 05:16:38 PM PDT 24
Peak memory 195780 kb
Host smart-0049bf21-bf98-45ad-8f4e-005d9a983792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198331803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2198331803
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1265508541
Short name T25
Test name
Test status
Simulation time 276669088 ps
CPU time 7.63 seconds
Started Jun 05 05:16:35 PM PDT 24
Finished Jun 05 05:16:43 PM PDT 24
Peak memory 198004 kb
Host smart-4297dd47-2d7a-44b9-bd2f-9e7ea9778719
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265508541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1265508541
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.867046119
Short name T628
Test name
Test status
Simulation time 47379930 ps
CPU time 0.9 seconds
Started Jun 05 05:16:41 PM PDT 24
Finished Jun 05 05:16:42 PM PDT 24
Peak memory 196864 kb
Host smart-431e69f0-af0a-4298-a06f-23ca77bbdd8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867046119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.867046119
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.218524279
Short name T290
Test name
Test status
Simulation time 150648869 ps
CPU time 1.36 seconds
Started Jun 05 05:16:39 PM PDT 24
Finished Jun 05 05:16:41 PM PDT 24
Peak memory 198104 kb
Host smart-1a1646d1-7409-4a81-94d7-a38496a04b4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218524279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.218524279
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1818742656
Short name T254
Test name
Test status
Simulation time 77146129 ps
CPU time 2.95 seconds
Started Jun 05 05:16:36 PM PDT 24
Finished Jun 05 05:16:39 PM PDT 24
Peak memory 196604 kb
Host smart-8189e404-8d01-4aa4-8ed0-44985c43d115
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818742656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1818742656
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3331685526
Short name T424
Test name
Test status
Simulation time 132191894 ps
CPU time 3.06 seconds
Started Jun 05 05:16:36 PM PDT 24
Finished Jun 05 05:16:40 PM PDT 24
Peak memory 197244 kb
Host smart-c65ce074-179b-4a38-843b-91385718b20e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331685526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3331685526
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1172958078
Short name T520
Test name
Test status
Simulation time 48457115 ps
CPU time 1.04 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:16:35 PM PDT 24
Peak memory 195948 kb
Host smart-cc0ab932-8dab-43ae-acab-275387f1021b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172958078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1172958078
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3160523245
Short name T634
Test name
Test status
Simulation time 23095140 ps
CPU time 0.74 seconds
Started Jun 05 05:16:35 PM PDT 24
Finished Jun 05 05:16:36 PM PDT 24
Peak memory 195400 kb
Host smart-d72e61fd-5b72-44b6-8478-d5e1d99493e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160523245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3160523245
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3740332955
Short name T253
Test name
Test status
Simulation time 271137905 ps
CPU time 3.62 seconds
Started Jun 05 05:16:40 PM PDT 24
Finished Jun 05 05:16:44 PM PDT 24
Peak memory 197768 kb
Host smart-faeed287-2e82-49d1-8a3c-bcbb43db1865
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740332955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3740332955
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.4187130263
Short name T474
Test name
Test status
Simulation time 793797095 ps
CPU time 1.2 seconds
Started Jun 05 05:16:31 PM PDT 24
Finished Jun 05 05:16:33 PM PDT 24
Peak memory 195880 kb
Host smart-1e42c066-9f0e-4ee1-85bd-80bbc233f583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187130263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.4187130263
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1401353046
Short name T600
Test name
Test status
Simulation time 181549351 ps
CPU time 0.92 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:16:34 PM PDT 24
Peak memory 195468 kb
Host smart-0f00f3bb-9661-4005-b4ec-afba5575e1b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401353046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1401353046
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.613974148
Short name T526
Test name
Test status
Simulation time 5920492160 ps
CPU time 31.19 seconds
Started Jun 05 05:16:38 PM PDT 24
Finished Jun 05 05:17:10 PM PDT 24
Peak memory 198292 kb
Host smart-36328426-df05-4997-b0b3-223dd5559fed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613974148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.613974148
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2331619525
Short name T67
Test name
Test status
Simulation time 80787439404 ps
CPU time 1351.36 seconds
Started Jun 05 05:16:36 PM PDT 24
Finished Jun 05 05:39:08 PM PDT 24
Peak memory 198316 kb
Host smart-a1dcf1db-bd03-4e27-ac98-72113fa228a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2331619525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2331619525
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.673505399
Short name T555
Test name
Test status
Simulation time 57374549 ps
CPU time 0.55 seconds
Started Jun 05 05:14:14 PM PDT 24
Finished Jun 05 05:14:15 PM PDT 24
Peak memory 193532 kb
Host smart-a31e004c-9d18-4ee3-9cc3-51b59d1e4e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673505399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.673505399
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3021879298
Short name T287
Test name
Test status
Simulation time 55461979 ps
CPU time 0.78 seconds
Started Jun 05 05:14:12 PM PDT 24
Finished Jun 05 05:14:14 PM PDT 24
Peak memory 195300 kb
Host smart-3e499441-acb1-43f5-ab3c-35d08da7523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021879298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3021879298
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.756958573
Short name T477
Test name
Test status
Simulation time 1118547229 ps
CPU time 4.5 seconds
Started Jun 05 05:14:15 PM PDT 24
Finished Jun 05 05:14:20 PM PDT 24
Peak memory 195932 kb
Host smart-9ad6c48a-070d-46ea-bc27-d835f3f96e86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756958573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.756958573
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.233397473
Short name T687
Test name
Test status
Simulation time 51829615 ps
CPU time 0.9 seconds
Started Jun 05 05:14:16 PM PDT 24
Finished Jun 05 05:14:18 PM PDT 24
Peak memory 196112 kb
Host smart-b84a6b35-5dec-4bc5-8ed5-f82fec631def
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233397473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.233397473
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.4251323400
Short name T429
Test name
Test status
Simulation time 17784661 ps
CPU time 0.68 seconds
Started Jun 05 05:14:14 PM PDT 24
Finished Jun 05 05:14:15 PM PDT 24
Peak memory 194420 kb
Host smart-0ec34d6d-1843-4dcf-a722-a7a3508b040e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251323400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.4251323400
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.500763096
Short name T163
Test name
Test status
Simulation time 137071151 ps
CPU time 1.56 seconds
Started Jun 05 05:14:14 PM PDT 24
Finished Jun 05 05:14:16 PM PDT 24
Peak memory 196840 kb
Host smart-7f28d082-9076-4089-afe1-8e66af84185f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500763096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.500763096
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3568106785
Short name T539
Test name
Test status
Simulation time 91757427 ps
CPU time 2.87 seconds
Started Jun 05 05:14:15 PM PDT 24
Finished Jun 05 05:14:18 PM PDT 24
Peak memory 197380 kb
Host smart-13d310f3-a26b-442b-9364-5011fc6b6856
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568106785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3568106785
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.630274623
Short name T83
Test name
Test status
Simulation time 367750253 ps
CPU time 1.01 seconds
Started Jun 05 05:14:09 PM PDT 24
Finished Jun 05 05:14:10 PM PDT 24
Peak memory 196116 kb
Host smart-227ca0a9-16c1-4f83-8a94-929f1559878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630274623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.630274623
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2927145932
Short name T530
Test name
Test status
Simulation time 66484643 ps
CPU time 1.4 seconds
Started Jun 05 05:14:14 PM PDT 24
Finished Jun 05 05:14:17 PM PDT 24
Peak memory 197004 kb
Host smart-4723f37b-7929-4d28-91fb-96d389a96d6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927145932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2927145932
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1867108184
Short name T413
Test name
Test status
Simulation time 7924822776 ps
CPU time 5.32 seconds
Started Jun 05 05:14:12 PM PDT 24
Finished Jun 05 05:14:18 PM PDT 24
Peak memory 198188 kb
Host smart-a32cc743-e729-45e0-aaca-51a51a1dc060
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867108184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1867108184
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3119121943
Short name T39
Test name
Test status
Simulation time 329130637 ps
CPU time 0.97 seconds
Started Jun 05 05:14:12 PM PDT 24
Finished Jun 05 05:14:14 PM PDT 24
Peak memory 215036 kb
Host smart-7c6efc92-7b81-4eaa-ba27-961c2c17c3b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119121943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3119121943
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.99090490
Short name T192
Test name
Test status
Simulation time 670709132 ps
CPU time 1.07 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:14:12 PM PDT 24
Peak memory 196560 kb
Host smart-90f2c02a-9c4b-412f-b68c-1685ea8fa2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99090490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.99090490
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2197886328
Short name T432
Test name
Test status
Simulation time 76050448 ps
CPU time 1.4 seconds
Started Jun 05 05:14:11 PM PDT 24
Finished Jun 05 05:14:13 PM PDT 24
Peak memory 198096 kb
Host smart-516a2753-7cc9-4809-a043-ae9ef6c1f320
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197886328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2197886328
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1733720847
Short name T168
Test name
Test status
Simulation time 7723576497 ps
CPU time 103.28 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:15:54 PM PDT 24
Peak memory 198224 kb
Host smart-bd45425e-0cad-492a-857a-6a5068619903
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733720847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1733720847
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2656003228
Short name T562
Test name
Test status
Simulation time 13245504 ps
CPU time 0.58 seconds
Started Jun 05 05:16:43 PM PDT 24
Finished Jun 05 05:16:44 PM PDT 24
Peak memory 193912 kb
Host smart-835d1b2f-c668-415f-8f0f-5f5746484eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656003228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2656003228
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3204980604
Short name T239
Test name
Test status
Simulation time 87091937 ps
CPU time 0.85 seconds
Started Jun 05 05:16:53 PM PDT 24
Finished Jun 05 05:16:55 PM PDT 24
Peak memory 195464 kb
Host smart-7229f520-68f4-4bdf-8038-31a1277491da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204980604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3204980604
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1254717067
Short name T469
Test name
Test status
Simulation time 331834144 ps
CPU time 17 seconds
Started Jun 05 05:16:53 PM PDT 24
Finished Jun 05 05:17:11 PM PDT 24
Peak memory 197376 kb
Host smart-6cb4526c-e41d-4640-aac4-fa3317cb1898
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254717067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1254717067
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3033838126
Short name T75
Test name
Test status
Simulation time 67323434 ps
CPU time 0.98 seconds
Started Jun 05 05:16:46 PM PDT 24
Finished Jun 05 05:16:48 PM PDT 24
Peak memory 196716 kb
Host smart-81d8bea9-5b66-44bb-9124-2c29a087aaae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033838126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3033838126
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2994733296
Short name T593
Test name
Test status
Simulation time 193256456 ps
CPU time 1.44 seconds
Started Jun 05 05:16:53 PM PDT 24
Finished Jun 05 05:16:56 PM PDT 24
Peak memory 196324 kb
Host smart-7744de29-2c0a-42f5-892f-70a1ebc56d3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994733296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2994733296
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1786181958
Short name T561
Test name
Test status
Simulation time 168463749 ps
CPU time 3.42 seconds
Started Jun 05 05:16:44 PM PDT 24
Finished Jun 05 05:16:47 PM PDT 24
Peak memory 197340 kb
Host smart-6d132084-72ad-4845-bd8e-cc27f9057a70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786181958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1786181958
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2934597079
Short name T587
Test name
Test status
Simulation time 21107914 ps
CPU time 0.83 seconds
Started Jun 05 05:16:46 PM PDT 24
Finished Jun 05 05:16:47 PM PDT 24
Peak memory 196720 kb
Host smart-a6f5ad81-b438-4abc-ab52-53f3bb7ccf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934597079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2934597079
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.839904707
Short name T632
Test name
Test status
Simulation time 42234096 ps
CPU time 1.03 seconds
Started Jun 05 05:16:44 PM PDT 24
Finished Jun 05 05:16:46 PM PDT 24
Peak memory 196052 kb
Host smart-cb4dd08f-0a63-4b19-b9b1-c4220583f398
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839904707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.839904707
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.118160844
Short name T641
Test name
Test status
Simulation time 2746815582 ps
CPU time 2.86 seconds
Started Jun 05 05:16:44 PM PDT 24
Finished Jun 05 05:16:47 PM PDT 24
Peak memory 198172 kb
Host smart-1593caef-0ac5-45f7-b0bf-ed08cb0445b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118160844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.118160844
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3642049949
Short name T465
Test name
Test status
Simulation time 33970491 ps
CPU time 1.06 seconds
Started Jun 05 05:16:38 PM PDT 24
Finished Jun 05 05:16:39 PM PDT 24
Peak memory 195888 kb
Host smart-6dd39758-f4f2-4f3b-93c2-7ea89be65054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642049949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3642049949
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.388200905
Short name T340
Test name
Test status
Simulation time 58249430 ps
CPU time 0.8 seconds
Started Jun 05 05:16:41 PM PDT 24
Finished Jun 05 05:16:42 PM PDT 24
Peak memory 195988 kb
Host smart-1b9af43b-4a76-485e-9b5c-24b474b3c2b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388200905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.388200905
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.353477431
Short name T9
Test name
Test status
Simulation time 45077696164 ps
CPU time 97.34 seconds
Started Jun 05 05:16:45 PM PDT 24
Finished Jun 05 05:18:23 PM PDT 24
Peak memory 198136 kb
Host smart-ee3d23bd-9945-4e5f-9558-2ead97155e0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353477431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.353477431
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.982303283
Short name T466
Test name
Test status
Simulation time 38580796 ps
CPU time 0.57 seconds
Started Jun 05 05:17:00 PM PDT 24
Finished Jun 05 05:17:02 PM PDT 24
Peak memory 193944 kb
Host smart-3885fc88-caf5-480e-bc54-0051b102fe82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982303283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.982303283
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3742492215
Short name T70
Test name
Test status
Simulation time 148699733 ps
CPU time 0.84 seconds
Started Jun 05 05:16:51 PM PDT 24
Finished Jun 05 05:16:52 PM PDT 24
Peak memory 195444 kb
Host smart-1f7efa50-244f-489f-8701-55a8809d35e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742492215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3742492215
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.7897374
Short name T613
Test name
Test status
Simulation time 923572996 ps
CPU time 26 seconds
Started Jun 05 05:16:52 PM PDT 24
Finished Jun 05 05:17:18 PM PDT 24
Peak memory 197172 kb
Host smart-6a0badbf-1f09-4423-a5f1-16d2a5477a90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7897374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stress.7897374
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.709306402
Short name T705
Test name
Test status
Simulation time 89973611 ps
CPU time 0.82 seconds
Started Jun 05 05:16:52 PM PDT 24
Finished Jun 05 05:16:54 PM PDT 24
Peak memory 196524 kb
Host smart-95653f05-1150-4eec-abd4-ed097bde7a89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709306402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.709306402
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2379725980
Short name T80
Test name
Test status
Simulation time 136092541 ps
CPU time 1.13 seconds
Started Jun 05 05:16:51 PM PDT 24
Finished Jun 05 05:16:53 PM PDT 24
Peak memory 196768 kb
Host smart-57bdd374-9b2c-4155-aad8-d35f8fed637f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379725980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2379725980
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3830661548
Short name T296
Test name
Test status
Simulation time 430526575 ps
CPU time 2.81 seconds
Started Jun 05 05:16:50 PM PDT 24
Finished Jun 05 05:16:54 PM PDT 24
Peak memory 198104 kb
Host smart-e925cb6d-8c57-4b06-879e-728dbe5e912b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830661548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3830661548
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2708403078
Short name T480
Test name
Test status
Simulation time 295146304 ps
CPU time 2.2 seconds
Started Jun 05 05:16:50 PM PDT 24
Finished Jun 05 05:16:53 PM PDT 24
Peak memory 195848 kb
Host smart-7f851197-b15d-457e-97ea-c4748f6c6d8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708403078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2708403078
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1136891265
Short name T623
Test name
Test status
Simulation time 60102269 ps
CPU time 1.3 seconds
Started Jun 05 05:16:53 PM PDT 24
Finished Jun 05 05:16:55 PM PDT 24
Peak memory 197068 kb
Host smart-92767c2d-5a7d-499e-81e9-19621eb15f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136891265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1136891265
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3223158015
Short name T512
Test name
Test status
Simulation time 58544954 ps
CPU time 1.12 seconds
Started Jun 05 05:16:51 PM PDT 24
Finished Jun 05 05:16:53 PM PDT 24
Peak memory 196080 kb
Host smart-7d0a97cd-9236-4773-ae93-5ed02dcc2ce6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223158015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3223158015
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2836585190
Short name T335
Test name
Test status
Simulation time 340825054 ps
CPU time 5.24 seconds
Started Jun 05 05:16:52 PM PDT 24
Finished Jun 05 05:16:58 PM PDT 24
Peak memory 196460 kb
Host smart-f8c7cd03-b622-4f66-8d93-9519b741bd33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836585190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2836585190
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1848379638
Short name T710
Test name
Test status
Simulation time 540745386 ps
CPU time 0.83 seconds
Started Jun 05 05:16:54 PM PDT 24
Finished Jun 05 05:16:56 PM PDT 24
Peak memory 195348 kb
Host smart-7247bc57-7778-4e19-9bd4-910cb728d938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848379638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1848379638
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2023575179
Short name T194
Test name
Test status
Simulation time 92120322 ps
CPU time 1.35 seconds
Started Jun 05 05:16:53 PM PDT 24
Finished Jun 05 05:16:55 PM PDT 24
Peak memory 196288 kb
Host smart-5c7795fa-584b-437f-9029-3bb70e4c60db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023575179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2023575179
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3199472214
Short name T544
Test name
Test status
Simulation time 6866626611 ps
CPU time 41.97 seconds
Started Jun 05 05:17:00 PM PDT 24
Finished Jun 05 05:17:42 PM PDT 24
Peak memory 198240 kb
Host smart-866918f1-8cb4-4dbc-8d7b-4c37a6113450
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199472214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3199472214
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2555947316
Short name T678
Test name
Test status
Simulation time 100626350 ps
CPU time 0.58 seconds
Started Jun 05 05:17:06 PM PDT 24
Finished Jun 05 05:17:07 PM PDT 24
Peak memory 194860 kb
Host smart-b80a167b-4e70-49d8-ac24-e434453e181e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555947316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2555947316
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.4158756490
Short name T647
Test name
Test status
Simulation time 28953691 ps
CPU time 0.66 seconds
Started Jun 05 05:16:58 PM PDT 24
Finished Jun 05 05:16:59 PM PDT 24
Peak memory 194348 kb
Host smart-cc9665e5-6fc4-4b97-8838-9ad62506b9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158756490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.4158756490
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.84710127
Short name T502
Test name
Test status
Simulation time 703679360 ps
CPU time 20.2 seconds
Started Jun 05 05:17:00 PM PDT 24
Finished Jun 05 05:17:21 PM PDT 24
Peak memory 197044 kb
Host smart-e1530965-3c39-4bf5-a0d2-61ac43f84ff7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84710127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stress
.84710127
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1205982124
Short name T449
Test name
Test status
Simulation time 32323016 ps
CPU time 0.64 seconds
Started Jun 05 05:16:59 PM PDT 24
Finished Jun 05 05:17:00 PM PDT 24
Peak memory 194624 kb
Host smart-623c3966-f852-4ba5-ab63-db558d0823d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205982124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1205982124
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1879361021
Short name T147
Test name
Test status
Simulation time 35648764 ps
CPU time 1.03 seconds
Started Jun 05 05:17:04 PM PDT 24
Finished Jun 05 05:17:06 PM PDT 24
Peak memory 196744 kb
Host smart-ecc8d7f8-c0ac-4455-a3ba-a2721f3d6abf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879361021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1879361021
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1360748262
Short name T700
Test name
Test status
Simulation time 96898074 ps
CPU time 3.94 seconds
Started Jun 05 05:16:59 PM PDT 24
Finished Jun 05 05:17:04 PM PDT 24
Peak memory 198100 kb
Host smart-37cc32ad-3540-4494-a033-59f5328084cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360748262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1360748262
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2480786118
Short name T596
Test name
Test status
Simulation time 240135124 ps
CPU time 3.37 seconds
Started Jun 05 05:16:58 PM PDT 24
Finished Jun 05 05:17:02 PM PDT 24
Peak memory 195868 kb
Host smart-3f4cc64f-4a74-4db5-a799-4846ec7cdd16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480786118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2480786118
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.899370093
Short name T425
Test name
Test status
Simulation time 512091962 ps
CPU time 1.15 seconds
Started Jun 05 05:16:59 PM PDT 24
Finished Jun 05 05:17:00 PM PDT 24
Peak memory 197132 kb
Host smart-8d00a44d-c5f3-47fd-8176-f2c8fed3436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899370093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.899370093
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1382591353
Short name T570
Test name
Test status
Simulation time 22627280 ps
CPU time 0.74 seconds
Started Jun 05 05:16:57 PM PDT 24
Finished Jun 05 05:16:58 PM PDT 24
Peak memory 196116 kb
Host smart-fd6c33bf-6ae2-4753-8c83-625e33e8bd35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382591353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1382591353
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1239886249
Short name T255
Test name
Test status
Simulation time 217883248 ps
CPU time 5.08 seconds
Started Jun 05 05:17:00 PM PDT 24
Finished Jun 05 05:17:05 PM PDT 24
Peak memory 198072 kb
Host smart-d7e680c3-9fa5-4874-b29c-ae61c7c04787
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239886249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1239886249
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.507673696
Short name T319
Test name
Test status
Simulation time 90106053 ps
CPU time 1 seconds
Started Jun 05 05:16:58 PM PDT 24
Finished Jun 05 05:17:00 PM PDT 24
Peak memory 195568 kb
Host smart-1141084d-c86a-4c62-84ae-5fb2f416dc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507673696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.507673696
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2857157054
Short name T453
Test name
Test status
Simulation time 60718739 ps
CPU time 0.76 seconds
Started Jun 05 05:17:00 PM PDT 24
Finished Jun 05 05:17:01 PM PDT 24
Peak memory 195240 kb
Host smart-0bc1a30b-9135-464f-8e41-07cf444acd8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857157054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2857157054
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3199663740
Short name T603
Test name
Test status
Simulation time 1919915743 ps
CPU time 27.2 seconds
Started Jun 05 05:17:06 PM PDT 24
Finished Jun 05 05:17:34 PM PDT 24
Peak memory 198112 kb
Host smart-ef0c24c5-fa0f-491d-ad00-beb2826f0ab6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199663740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3199663740
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2125702772
Short name T42
Test name
Test status
Simulation time 14637675 ps
CPU time 0.6 seconds
Started Jun 05 05:17:17 PM PDT 24
Finished Jun 05 05:17:18 PM PDT 24
Peak memory 193980 kb
Host smart-78ffdcbf-5c7d-4fe9-aa67-83793085d706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125702772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2125702772
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2266154102
Short name T380
Test name
Test status
Simulation time 189593405 ps
CPU time 0.8 seconds
Started Jun 05 05:17:07 PM PDT 24
Finished Jun 05 05:17:08 PM PDT 24
Peak memory 196204 kb
Host smart-5a1ec9bc-f3bc-43ba-8fe7-9834d2790675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266154102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2266154102
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1512840173
Short name T384
Test name
Test status
Simulation time 2567146825 ps
CPU time 5.82 seconds
Started Jun 05 05:17:16 PM PDT 24
Finished Jun 05 05:17:22 PM PDT 24
Peak memory 197088 kb
Host smart-717381cd-aa9e-47be-80cb-ec7ee537bfc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512840173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1512840173
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2910043522
Short name T481
Test name
Test status
Simulation time 291730847 ps
CPU time 0.95 seconds
Started Jun 05 05:17:15 PM PDT 24
Finished Jun 05 05:17:16 PM PDT 24
Peak memory 198024 kb
Host smart-f1c69da6-dfd7-4d37-b663-8173b710a1eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910043522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2910043522
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.601793924
Short name T617
Test name
Test status
Simulation time 289469658 ps
CPU time 1.16 seconds
Started Jun 05 05:17:06 PM PDT 24
Finished Jun 05 05:17:07 PM PDT 24
Peak memory 196128 kb
Host smart-6ac69630-1026-44be-b465-794c4d14ce34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601793924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.601793924
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.546813411
Short name T476
Test name
Test status
Simulation time 63039895 ps
CPU time 2.4 seconds
Started Jun 05 05:17:16 PM PDT 24
Finished Jun 05 05:17:19 PM PDT 24
Peak memory 198148 kb
Host smart-8f98503f-c1a1-4a1f-8883-e7a29aab78a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546813411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.546813411
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.236803302
Short name T664
Test name
Test status
Simulation time 326529482 ps
CPU time 2.44 seconds
Started Jun 05 05:17:05 PM PDT 24
Finished Jun 05 05:17:08 PM PDT 24
Peak memory 196556 kb
Host smart-ee6a99e6-53f4-43a8-b37a-94dfdb3f4303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236803302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
236803302
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1877329276
Short name T142
Test name
Test status
Simulation time 43251890 ps
CPU time 1.02 seconds
Started Jun 05 05:17:07 PM PDT 24
Finished Jun 05 05:17:09 PM PDT 24
Peak memory 196068 kb
Host smart-da20e147-0cd8-4c1b-98b5-8748e69152f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877329276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1877329276
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1500597259
Short name T537
Test name
Test status
Simulation time 28003181 ps
CPU time 0.74 seconds
Started Jun 05 05:17:06 PM PDT 24
Finished Jun 05 05:17:07 PM PDT 24
Peak memory 195392 kb
Host smart-e496f2ee-c7d5-4569-b28d-1c948d18f109
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500597259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1500597259
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1233584804
Short name T153
Test name
Test status
Simulation time 98523806 ps
CPU time 4.39 seconds
Started Jun 05 05:17:17 PM PDT 24
Finished Jun 05 05:17:22 PM PDT 24
Peak memory 198008 kb
Host smart-cf11d35c-4d78-49d7-99e4-50d65201b0ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233584804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1233584804
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2302018112
Short name T11
Test name
Test status
Simulation time 123513253 ps
CPU time 1.2 seconds
Started Jun 05 05:17:07 PM PDT 24
Finished Jun 05 05:17:08 PM PDT 24
Peak memory 195904 kb
Host smart-e76f58b5-f5f3-4e6d-a5ec-b2f59018312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302018112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2302018112
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2509176251
Short name T223
Test name
Test status
Simulation time 201830671 ps
CPU time 1.11 seconds
Started Jun 05 05:17:06 PM PDT 24
Finished Jun 05 05:17:07 PM PDT 24
Peak memory 195872 kb
Host smart-335b6ebf-7dd8-4564-bde2-c8f2685c568c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509176251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2509176251
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1900453741
Short name T363
Test name
Test status
Simulation time 3364089244 ps
CPU time 69.44 seconds
Started Jun 05 05:17:15 PM PDT 24
Finished Jun 05 05:18:24 PM PDT 24
Peak memory 198164 kb
Host smart-00904ef0-ea5c-4597-bd9b-c5c1afe33bc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900453741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1900453741
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3738441835
Short name T180
Test name
Test status
Simulation time 15003010 ps
CPU time 0.6 seconds
Started Jun 05 05:17:23 PM PDT 24
Finished Jun 05 05:17:24 PM PDT 24
Peak memory 193948 kb
Host smart-f7f4bb70-2010-4915-bdda-1d049bc172ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738441835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3738441835
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1499024365
Short name T612
Test name
Test status
Simulation time 275398894 ps
CPU time 0.84 seconds
Started Jun 05 05:17:16 PM PDT 24
Finished Jun 05 05:17:17 PM PDT 24
Peak memory 196120 kb
Host smart-899470ce-6bce-4722-94a9-feb8cdc23a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499024365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1499024365
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2991117920
Short name T677
Test name
Test status
Simulation time 350507853 ps
CPU time 12.13 seconds
Started Jun 05 05:17:22 PM PDT 24
Finished Jun 05 05:17:35 PM PDT 24
Peak memory 196824 kb
Host smart-7edf28f5-4f8c-4b2c-99bb-93a48dc3246f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991117920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2991117920
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.972610338
Short name T558
Test name
Test status
Simulation time 33970175 ps
CPU time 0.72 seconds
Started Jun 05 05:17:21 PM PDT 24
Finished Jun 05 05:17:22 PM PDT 24
Peak memory 194860 kb
Host smart-eaaa2a3a-53fd-4206-ac64-9568deaca0e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972610338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.972610338
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2247932884
Short name T567
Test name
Test status
Simulation time 526213928 ps
CPU time 1.08 seconds
Started Jun 05 05:17:15 PM PDT 24
Finished Jun 05 05:17:17 PM PDT 24
Peak memory 196104 kb
Host smart-7066c485-38b4-401e-809e-210fb73efd69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247932884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2247932884
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3099583510
Short name T557
Test name
Test status
Simulation time 64775862 ps
CPU time 2.48 seconds
Started Jun 05 05:17:22 PM PDT 24
Finished Jun 05 05:17:25 PM PDT 24
Peak memory 198080 kb
Host smart-79bf8a1f-e2a3-4a00-ba07-91bf4e28d500
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099583510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3099583510
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3628922099
Short name T493
Test name
Test status
Simulation time 51853177 ps
CPU time 0.97 seconds
Started Jun 05 05:17:21 PM PDT 24
Finished Jun 05 05:17:23 PM PDT 24
Peak memory 195740 kb
Host smart-61afc60c-625f-4f1e-8d79-bc302e929471
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628922099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3628922099
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3524132418
Short name T713
Test name
Test status
Simulation time 190537018 ps
CPU time 1.23 seconds
Started Jun 05 05:17:16 PM PDT 24
Finished Jun 05 05:17:18 PM PDT 24
Peak memory 196820 kb
Host smart-11821c72-1c0d-485b-b7d1-1e75fb244938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524132418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3524132418
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.450986089
Short name T460
Test name
Test status
Simulation time 108065777 ps
CPU time 1.11 seconds
Started Jun 05 05:17:15 PM PDT 24
Finished Jun 05 05:17:17 PM PDT 24
Peak memory 196136 kb
Host smart-0ba8a97f-ff75-436a-88b7-5d51ce45b664
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450986089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.450986089
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.695830883
Short name T674
Test name
Test status
Simulation time 1463942122 ps
CPU time 5.55 seconds
Started Jun 05 05:17:22 PM PDT 24
Finished Jun 05 05:17:28 PM PDT 24
Peak memory 197988 kb
Host smart-4124d42a-9047-4ef8-bf82-ccdb6240ecf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695830883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.695830883
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.524260851
Short name T128
Test name
Test status
Simulation time 238653368 ps
CPU time 1.26 seconds
Started Jun 05 05:17:16 PM PDT 24
Finished Jun 05 05:17:18 PM PDT 24
Peak memory 196512 kb
Host smart-c41f24cd-5dac-4ada-8a79-b938e772d42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524260851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.524260851
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3601916417
Short name T472
Test name
Test status
Simulation time 58538001 ps
CPU time 1.22 seconds
Started Jun 05 05:17:17 PM PDT 24
Finished Jun 05 05:17:19 PM PDT 24
Peak memory 195740 kb
Host smart-a46cd483-62f8-41d9-bfb5-3d473619d6d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601916417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3601916417
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1654761011
Short name T286
Test name
Test status
Simulation time 22780005545 ps
CPU time 158.83 seconds
Started Jun 05 05:17:23 PM PDT 24
Finished Jun 05 05:20:02 PM PDT 24
Peak memory 198240 kb
Host smart-f3204a7c-f143-4567-a740-7e71b195ba3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654761011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1654761011
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.497624543
Short name T516
Test name
Test status
Simulation time 77383334565 ps
CPU time 1401.99 seconds
Started Jun 05 05:17:23 PM PDT 24
Finished Jun 05 05:40:45 PM PDT 24
Peak memory 198224 kb
Host smart-a9bcc796-ce17-4d52-887d-33a479ab4efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=497624543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.497624543
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2256035045
Short name T15
Test name
Test status
Simulation time 49274253 ps
CPU time 0.58 seconds
Started Jun 05 05:17:29 PM PDT 24
Finished Jun 05 05:17:30 PM PDT 24
Peak memory 193976 kb
Host smart-b6f65998-b6c5-4d73-8702-52dccc13b11d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256035045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2256035045
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2903106857
Short name T252
Test name
Test status
Simulation time 63670863 ps
CPU time 0.79 seconds
Started Jun 05 05:17:22 PM PDT 24
Finished Jun 05 05:17:23 PM PDT 24
Peak memory 196304 kb
Host smart-c1275bda-c30a-4a43-ada0-4e81f624f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903106857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2903106857
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.736490730
Short name T178
Test name
Test status
Simulation time 5194751694 ps
CPU time 25.82 seconds
Started Jun 05 05:17:29 PM PDT 24
Finished Jun 05 05:17:56 PM PDT 24
Peak memory 197580 kb
Host smart-64fe5672-bb52-4411-be9b-e3322108474d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736490730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.736490730
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.574629884
Short name T606
Test name
Test status
Simulation time 472867546 ps
CPU time 1.04 seconds
Started Jun 05 05:17:28 PM PDT 24
Finished Jun 05 05:17:29 PM PDT 24
Peak memory 196776 kb
Host smart-f153dbf3-3e38-4add-9910-ec8ef4ad4f50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574629884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.574629884
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1702256986
Short name T714
Test name
Test status
Simulation time 28931784 ps
CPU time 0.94 seconds
Started Jun 05 05:17:21 PM PDT 24
Finished Jun 05 05:17:23 PM PDT 24
Peak memory 197768 kb
Host smart-d32942eb-6e00-4cb8-a4e9-fdc0d5aac39f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702256986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1702256986
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1455130473
Short name T426
Test name
Test status
Simulation time 66925125 ps
CPU time 2.59 seconds
Started Jun 05 05:17:32 PM PDT 24
Finished Jun 05 05:17:35 PM PDT 24
Peak memory 198000 kb
Host smart-7fa729b4-ef8e-4056-a941-01d3b28f4043
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455130473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1455130473
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2309595123
Short name T370
Test name
Test status
Simulation time 318517448 ps
CPU time 3.2 seconds
Started Jun 05 05:17:24 PM PDT 24
Finished Jun 05 05:17:28 PM PDT 24
Peak memory 198124 kb
Host smart-152344af-0815-48fa-bd3f-5a1458fbc96b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309595123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2309595123
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4284551346
Short name T577
Test name
Test status
Simulation time 37465933 ps
CPU time 0.9 seconds
Started Jun 05 05:17:22 PM PDT 24
Finished Jun 05 05:17:23 PM PDT 24
Peak memory 196084 kb
Host smart-eb57e1f5-e6cb-4357-8da7-cc1c77572d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284551346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4284551346
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3733743869
Short name T487
Test name
Test status
Simulation time 175468217 ps
CPU time 1.01 seconds
Started Jun 05 05:17:22 PM PDT 24
Finished Jun 05 05:17:24 PM PDT 24
Peak memory 196776 kb
Host smart-cc7a2deb-e7de-419c-9db0-1992899fe8a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733743869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3733743869
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.4196100732
Short name T468
Test name
Test status
Simulation time 108524164 ps
CPU time 4.84 seconds
Started Jun 05 05:17:31 PM PDT 24
Finished Jun 05 05:17:36 PM PDT 24
Peak memory 198108 kb
Host smart-c50952ac-9db2-4b7a-8841-ab820d22e085
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196100732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.4196100732
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.4095511437
Short name T164
Test name
Test status
Simulation time 73803642 ps
CPU time 1.3 seconds
Started Jun 05 05:17:22 PM PDT 24
Finished Jun 05 05:17:24 PM PDT 24
Peak memory 198040 kb
Host smart-fee077b4-4e93-4f79-88e4-45d0560b9518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095511437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.4095511437
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2266863675
Short name T313
Test name
Test status
Simulation time 63117807 ps
CPU time 1.21 seconds
Started Jun 05 05:17:18 PM PDT 24
Finished Jun 05 05:17:20 PM PDT 24
Peak memory 197208 kb
Host smart-aaaa8517-d9f1-4042-9263-d7434f90645d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266863675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2266863675
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1260346601
Short name T483
Test name
Test status
Simulation time 18944835911 ps
CPU time 105.61 seconds
Started Jun 05 05:17:33 PM PDT 24
Finished Jun 05 05:19:19 PM PDT 24
Peak memory 198240 kb
Host smart-84a0762f-8d65-4d74-89fa-9c82547def89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260346601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1260346601
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2181610304
Short name T65
Test name
Test status
Simulation time 231807853163 ps
CPU time 1540.69 seconds
Started Jun 05 05:17:31 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 198248 kb
Host smart-144018b4-3328-4ba9-9d16-7d0d79da09ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2181610304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2181610304
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2397539862
Short name T177
Test name
Test status
Simulation time 16775558 ps
CPU time 0.61 seconds
Started Jun 05 05:17:38 PM PDT 24
Finished Jun 05 05:17:40 PM PDT 24
Peak memory 194984 kb
Host smart-ee1db7e9-0755-4281-aa3b-c1685c08b9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397539862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2397539862
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1811924146
Short name T135
Test name
Test status
Simulation time 200523546 ps
CPU time 0.86 seconds
Started Jun 05 05:17:32 PM PDT 24
Finished Jun 05 05:17:33 PM PDT 24
Peak memory 195264 kb
Host smart-2bb4392c-1641-442b-99d2-124bd3db94ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811924146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1811924146
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3578571056
Short name T184
Test name
Test status
Simulation time 708394283 ps
CPU time 19.86 seconds
Started Jun 05 05:17:30 PM PDT 24
Finished Jun 05 05:17:51 PM PDT 24
Peak memory 196768 kb
Host smart-3e785424-9f1b-46d7-a711-fabd57b46760
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578571056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3578571056
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3289305748
Short name T6
Test name
Test status
Simulation time 115937948 ps
CPU time 1.12 seconds
Started Jun 05 05:17:37 PM PDT 24
Finished Jun 05 05:17:38 PM PDT 24
Peak memory 196664 kb
Host smart-5d394497-db01-4a5e-8824-e4907d0c2ef8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289305748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3289305748
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2125551292
Short name T256
Test name
Test status
Simulation time 54871439 ps
CPU time 1 seconds
Started Jun 05 05:17:29 PM PDT 24
Finished Jun 05 05:17:30 PM PDT 24
Peak memory 196560 kb
Host smart-83b972d0-5c2a-48bb-bd61-79d255a311dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125551292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2125551292
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3165678241
Short name T283
Test name
Test status
Simulation time 54380743 ps
CPU time 2.27 seconds
Started Jun 05 05:17:30 PM PDT 24
Finished Jun 05 05:17:33 PM PDT 24
Peak memory 198104 kb
Host smart-18e9c8d0-5212-4a20-a9ce-41e419bbff28
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165678241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3165678241
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3307754829
Short name T336
Test name
Test status
Simulation time 119623768 ps
CPU time 0.86 seconds
Started Jun 05 05:17:33 PM PDT 24
Finished Jun 05 05:17:35 PM PDT 24
Peak memory 195624 kb
Host smart-8138a13d-9a3f-45d5-a4fd-687f5880432c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307754829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3307754829
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.4084991454
Short name T273
Test name
Test status
Simulation time 99692830 ps
CPU time 1.04 seconds
Started Jun 05 05:17:31 PM PDT 24
Finished Jun 05 05:17:32 PM PDT 24
Peak memory 195824 kb
Host smart-9e65fe1f-0f59-43ea-b490-a1c032dd9aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084991454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.4084991454
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1078631881
Short name T443
Test name
Test status
Simulation time 45901364 ps
CPU time 1.08 seconds
Started Jun 05 05:17:30 PM PDT 24
Finished Jun 05 05:17:32 PM PDT 24
Peak memory 195916 kb
Host smart-beffee40-b10d-48e8-bbd0-0935b2f81002
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078631881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1078631881
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2129218246
Short name T129
Test name
Test status
Simulation time 403105278 ps
CPU time 4.75 seconds
Started Jun 05 05:17:37 PM PDT 24
Finished Jun 05 05:17:42 PM PDT 24
Peak memory 197900 kb
Host smart-d34d72c0-a2c7-4ccf-ab13-3fcfb953eb80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129218246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2129218246
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3048183952
Short name T463
Test name
Test status
Simulation time 305333604 ps
CPU time 1.5 seconds
Started Jun 05 05:17:30 PM PDT 24
Finished Jun 05 05:17:32 PM PDT 24
Peak memory 196940 kb
Host smart-002db341-6e56-4e13-bfa2-af9e97a47625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048183952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3048183952
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3149107093
Short name T406
Test name
Test status
Simulation time 37135298 ps
CPU time 0.86 seconds
Started Jun 05 05:17:30 PM PDT 24
Finished Jun 05 05:17:31 PM PDT 24
Peak memory 195324 kb
Host smart-21ea0d07-3494-42a5-81f6-fabf139fb0d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149107093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3149107093
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2497406537
Short name T368
Test name
Test status
Simulation time 2363271585 ps
CPU time 56.5 seconds
Started Jun 05 05:17:36 PM PDT 24
Finished Jun 05 05:18:33 PM PDT 24
Peak memory 198184 kb
Host smart-5b1c3ffe-6d23-49d1-b5cb-7e97c536e565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497406537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2497406537
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2852046603
Short name T559
Test name
Test status
Simulation time 89797866502 ps
CPU time 307.3 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:22:52 PM PDT 24
Peak memory 206512 kb
Host smart-4c748c15-a18b-4853-b3e4-d4adfbbc2737
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2852046603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2852046603
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.189396386
Short name T378
Test name
Test status
Simulation time 32007347 ps
CPU time 0.6 seconds
Started Jun 05 05:17:47 PM PDT 24
Finished Jun 05 05:17:48 PM PDT 24
Peak memory 193960 kb
Host smart-8238c261-50c6-4261-8cd4-4951cd38be48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189396386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.189396386
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3452797221
Short name T715
Test name
Test status
Simulation time 29462868 ps
CPU time 0.9 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:17:45 PM PDT 24
Peak memory 196712 kb
Host smart-ffbd2f0e-f3b4-40a8-ac80-efb05b901388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452797221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3452797221
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.324279875
Short name T220
Test name
Test status
Simulation time 856487614 ps
CPU time 24.66 seconds
Started Jun 05 05:17:39 PM PDT 24
Finished Jun 05 05:18:04 PM PDT 24
Peak memory 196788 kb
Host smart-d656b87e-6aea-4009-bc0c-07a58508aa42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324279875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.324279875
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3205978209
Short name T341
Test name
Test status
Simulation time 71262270 ps
CPU time 1.05 seconds
Started Jun 05 05:17:38 PM PDT 24
Finished Jun 05 05:17:39 PM PDT 24
Peak memory 196656 kb
Host smart-d676e4a2-7a06-4c92-ab9a-c6243c746827
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205978209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3205978209
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.114699625
Short name T545
Test name
Test status
Simulation time 97549329 ps
CPU time 1 seconds
Started Jun 05 05:17:38 PM PDT 24
Finished Jun 05 05:17:40 PM PDT 24
Peak memory 196144 kb
Host smart-84e0371e-24dd-467d-98ad-be62d98f981f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114699625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.114699625
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.105520732
Short name T76
Test name
Test status
Simulation time 568365223 ps
CPU time 3.18 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:17:48 PM PDT 24
Peak memory 198168 kb
Host smart-688180f2-5a16-49ef-b040-6c926e4f2e95
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105520732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.105520732
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1284288884
Short name T701
Test name
Test status
Simulation time 334120445 ps
CPU time 2.94 seconds
Started Jun 05 05:17:39 PM PDT 24
Finished Jun 05 05:17:43 PM PDT 24
Peak memory 196640 kb
Host smart-b1036f97-2935-48aa-88ea-0b1e9710eb7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284288884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1284288884
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3957264042
Short name T149
Test name
Test status
Simulation time 16525537 ps
CPU time 0.74 seconds
Started Jun 05 05:17:37 PM PDT 24
Finished Jun 05 05:17:38 PM PDT 24
Peak memory 195420 kb
Host smart-a67a548f-77b7-454d-af30-01eaeb9e03df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957264042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3957264042
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1136204751
Short name T506
Test name
Test status
Simulation time 22845607 ps
CPU time 0.8 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:17:45 PM PDT 24
Peak memory 195672 kb
Host smart-5a480aa8-4f4a-4e68-8c14-a593380f0c17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136204751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1136204751
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.750217357
Short name T564
Test name
Test status
Simulation time 469010854 ps
CPU time 5.44 seconds
Started Jun 05 05:17:37 PM PDT 24
Finished Jun 05 05:17:42 PM PDT 24
Peak memory 197992 kb
Host smart-b0dbbe91-b94f-4dc3-a778-eadc8ef97a80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750217357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.750217357
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2334734694
Short name T280
Test name
Test status
Simulation time 75673669 ps
CPU time 0.88 seconds
Started Jun 05 05:17:39 PM PDT 24
Finished Jun 05 05:17:40 PM PDT 24
Peak memory 197176 kb
Host smart-04306193-5141-49c2-a866-fa75341e9585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334734694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2334734694
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2632169994
Short name T136
Test name
Test status
Simulation time 56795247 ps
CPU time 0.99 seconds
Started Jun 05 05:17:36 PM PDT 24
Finished Jun 05 05:17:37 PM PDT 24
Peak memory 195760 kb
Host smart-cabc7336-87b1-46cb-ac3f-bc5bbc5f0d6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632169994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2632169994
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3081767300
Short name T8
Test name
Test status
Simulation time 61799500764 ps
CPU time 147.98 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:20:13 PM PDT 24
Peak memory 198172 kb
Host smart-074bfa2e-6cb5-4908-8033-da3da1e4934c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081767300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3081767300
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2521062746
Short name T309
Test name
Test status
Simulation time 12805435 ps
CPU time 0.57 seconds
Started Jun 05 05:17:54 PM PDT 24
Finished Jun 05 05:17:55 PM PDT 24
Peak memory 194840 kb
Host smart-af068769-41ee-47f1-a579-8ea00f5643f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521062746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2521062746
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.923142011
Short name T407
Test name
Test status
Simulation time 36251214 ps
CPU time 0.76 seconds
Started Jun 05 05:17:45 PM PDT 24
Finished Jun 05 05:17:47 PM PDT 24
Peak memory 195304 kb
Host smart-cb3d9cdc-e2b6-429e-aaa6-91fc25e74344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923142011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.923142011
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.4125549148
Short name T121
Test name
Test status
Simulation time 328912299 ps
CPU time 9.09 seconds
Started Jun 05 05:17:45 PM PDT 24
Finished Jun 05 05:17:55 PM PDT 24
Peak memory 195532 kb
Host smart-4b023fef-9263-48ae-9d30-dac364152ce3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125549148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.4125549148
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2964583053
Short name T77
Test name
Test status
Simulation time 178096469 ps
CPU time 1 seconds
Started Jun 05 05:17:54 PM PDT 24
Finished Jun 05 05:17:56 PM PDT 24
Peak memory 196504 kb
Host smart-07b2b6c6-9906-438a-aa35-3069ecfab733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964583053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2964583053
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3132382802
Short name T204
Test name
Test status
Simulation time 37650220 ps
CPU time 1.06 seconds
Started Jun 05 05:17:46 PM PDT 24
Finished Jun 05 05:17:47 PM PDT 24
Peak memory 196148 kb
Host smart-86df818c-48e3-4511-8109-7e713b4343de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132382802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3132382802
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2584628454
Short name T627
Test name
Test status
Simulation time 340111544 ps
CPU time 3.51 seconds
Started Jun 05 05:17:46 PM PDT 24
Finished Jun 05 05:17:50 PM PDT 24
Peak memory 198032 kb
Host smart-4fc08033-13d6-4039-a990-bbbda609cb39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584628454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2584628454
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.42651018
Short name T205
Test name
Test status
Simulation time 57479410 ps
CPU time 1.95 seconds
Started Jun 05 05:17:43 PM PDT 24
Finished Jun 05 05:17:45 PM PDT 24
Peak memory 195908 kb
Host smart-19e35128-2535-43d7-9c87-771ce6db8c5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42651018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.42651018
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.982687788
Short name T494
Test name
Test status
Simulation time 104331481 ps
CPU time 1.05 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:17:46 PM PDT 24
Peak memory 196132 kb
Host smart-1378f78f-da1b-4dea-bf37-07758ef33edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982687788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.982687788
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.804707541
Short name T504
Test name
Test status
Simulation time 83956344 ps
CPU time 0.98 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:17:46 PM PDT 24
Peak memory 195876 kb
Host smart-5d4a8190-e497-4057-91ed-36e42fbf0afe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804707541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.804707541
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2961037176
Short name T55
Test name
Test status
Simulation time 380160723 ps
CPU time 4.83 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:17:49 PM PDT 24
Peak memory 197096 kb
Host smart-1975d1a0-1dae-4933-80bb-3fba4ef3fc2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961037176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2961037176
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3288549540
Short name T234
Test name
Test status
Simulation time 225401985 ps
CPU time 1.14 seconds
Started Jun 05 05:17:47 PM PDT 24
Finished Jun 05 05:17:48 PM PDT 24
Peak memory 196300 kb
Host smart-ed7b9b43-7723-4006-872d-a44f8cb6b873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288549540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3288549540
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2155993657
Short name T581
Test name
Test status
Simulation time 211188891 ps
CPU time 0.98 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:17:46 PM PDT 24
Peak memory 196508 kb
Host smart-4702be58-27c7-49f7-8f4b-5cfe32e7635a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155993657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2155993657
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2915005848
Short name T574
Test name
Test status
Simulation time 14270493865 ps
CPU time 89.05 seconds
Started Jun 05 05:17:52 PM PDT 24
Finished Jun 05 05:19:22 PM PDT 24
Peak memory 198208 kb
Host smart-6889fc83-0679-47b6-9a00-f5e3e9e6b7ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915005848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2915005848
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2466114643
Short name T32
Test name
Test status
Simulation time 190044617375 ps
CPU time 789.45 seconds
Started Jun 05 05:17:52 PM PDT 24
Finished Jun 05 05:31:02 PM PDT 24
Peak memory 198292 kb
Host smart-bd6827ea-6b3e-444c-8b83-60d88fc1e81b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2466114643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2466114643
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3555472727
Short name T624
Test name
Test status
Simulation time 50552291 ps
CPU time 0.57 seconds
Started Jun 05 05:17:59 PM PDT 24
Finished Jun 05 05:18:01 PM PDT 24
Peak memory 194164 kb
Host smart-a937996c-1917-4ac2-8dc8-3db3d87b151a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555472727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3555472727
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2918070
Short name T294
Test name
Test status
Simulation time 97389084 ps
CPU time 0.67 seconds
Started Jun 05 05:17:53 PM PDT 24
Finished Jun 05 05:17:54 PM PDT 24
Peak memory 194264 kb
Host smart-ccaf7571-bb5e-48e5-ba75-242430daf319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2918070
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1688825782
Short name T497
Test name
Test status
Simulation time 283047819 ps
CPU time 4.3 seconds
Started Jun 05 05:17:54 PM PDT 24
Finished Jun 05 05:17:58 PM PDT 24
Peak memory 195916 kb
Host smart-9a694022-5801-4065-8607-8c4131ecd6bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688825782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1688825782
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3430683053
Short name T510
Test name
Test status
Simulation time 189400093 ps
CPU time 0.82 seconds
Started Jun 05 05:18:00 PM PDT 24
Finished Jun 05 05:18:01 PM PDT 24
Peak memory 196060 kb
Host smart-dc884528-313f-446f-b577-1d78df1805b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430683053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3430683053
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1454302608
Short name T703
Test name
Test status
Simulation time 129838849 ps
CPU time 1.02 seconds
Started Jun 05 05:17:52 PM PDT 24
Finished Jun 05 05:17:54 PM PDT 24
Peak memory 196924 kb
Host smart-d1cc90f7-83b3-44b6-bd56-a66b5de94037
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454302608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1454302608
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1002661305
Short name T614
Test name
Test status
Simulation time 32065136 ps
CPU time 1.41 seconds
Started Jun 05 05:17:51 PM PDT 24
Finished Jun 05 05:17:53 PM PDT 24
Peak memory 198020 kb
Host smart-b7c869ab-dcb2-499a-b6b1-8981256c8f0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002661305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1002661305
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3960509802
Short name T28
Test name
Test status
Simulation time 722534937 ps
CPU time 2.67 seconds
Started Jun 05 05:17:56 PM PDT 24
Finished Jun 05 05:17:59 PM PDT 24
Peak memory 196848 kb
Host smart-072db8c3-e0e3-4628-adeb-be622dedb786
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960509802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3960509802
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1084052190
Short name T569
Test name
Test status
Simulation time 220731215 ps
CPU time 1.3 seconds
Started Jun 05 05:17:50 PM PDT 24
Finished Jun 05 05:17:51 PM PDT 24
Peak memory 198140 kb
Host smart-09a3d2ec-6042-400c-bee7-3fda26d54627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084052190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1084052190
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3898871903
Short name T246
Test name
Test status
Simulation time 153342782 ps
CPU time 1.16 seconds
Started Jun 05 05:17:50 PM PDT 24
Finished Jun 05 05:17:52 PM PDT 24
Peak memory 195892 kb
Host smart-f03dba4f-e641-4e0d-9957-560fb6483fa8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898871903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3898871903
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1956505347
Short name T692
Test name
Test status
Simulation time 360177642 ps
CPU time 3.75 seconds
Started Jun 05 05:18:00 PM PDT 24
Finished Jun 05 05:18:04 PM PDT 24
Peak memory 197964 kb
Host smart-5f3e8a76-5b77-464a-a25d-1c2197b01ee0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956505347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1956505347
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1306227932
Short name T124
Test name
Test status
Simulation time 246277212 ps
CPU time 1.11 seconds
Started Jun 05 05:17:53 PM PDT 24
Finished Jun 05 05:17:54 PM PDT 24
Peak memory 195592 kb
Host smart-b84542b5-49c6-4bf8-ab3e-ecd843415383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306227932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1306227932
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.4287320761
Short name T684
Test name
Test status
Simulation time 191061491 ps
CPU time 1.31 seconds
Started Jun 05 05:17:51 PM PDT 24
Finished Jun 05 05:17:53 PM PDT 24
Peak memory 196836 kb
Host smart-dfb73bf0-1bd6-41ff-ba57-a65a9d1422b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287320761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.4287320761
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2685019639
Short name T125
Test name
Test status
Simulation time 10492592803 ps
CPU time 40.1 seconds
Started Jun 05 05:17:59 PM PDT 24
Finished Jun 05 05:18:40 PM PDT 24
Peak memory 198236 kb
Host smart-490e031e-862d-444c-8148-8602116f390f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685019639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2685019639
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2979111865
Short name T318
Test name
Test status
Simulation time 11687076 ps
CPU time 0.56 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:14:11 PM PDT 24
Peak memory 193480 kb
Host smart-ebc3f750-adea-4289-b755-07f54e31753a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979111865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2979111865
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2910030664
Short name T434
Test name
Test status
Simulation time 81044303 ps
CPU time 0.86 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:14:11 PM PDT 24
Peak memory 195940 kb
Host smart-96d1323a-1d40-4fb8-a6ea-366ef74a5ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910030664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2910030664
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2415815751
Short name T201
Test name
Test status
Simulation time 500763905 ps
CPU time 12.86 seconds
Started Jun 05 05:14:08 PM PDT 24
Finished Jun 05 05:14:21 PM PDT 24
Peak memory 195580 kb
Host smart-11a02fbc-a32f-445e-affd-6781be40820c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415815751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2415815751
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2024369654
Short name T685
Test name
Test status
Simulation time 168732787 ps
CPU time 0.7 seconds
Started Jun 05 05:14:15 PM PDT 24
Finished Jun 05 05:14:17 PM PDT 24
Peak memory 194796 kb
Host smart-44944fc9-8f24-47d2-a676-2238b5a00315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024369654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2024369654
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.37686922
Short name T495
Test name
Test status
Simulation time 36687040 ps
CPU time 0.74 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:14:12 PM PDT 24
Peak memory 195436 kb
Host smart-d1328882-01cd-4d3d-9181-a16f35c06e36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37686922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.37686922
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.335726647
Short name T79
Test name
Test status
Simulation time 573024273 ps
CPU time 3.36 seconds
Started Jun 05 05:14:11 PM PDT 24
Finished Jun 05 05:14:15 PM PDT 24
Peak memory 196536 kb
Host smart-5e9e2414-fc64-42c0-aa58-3a1116623e70
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335726647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.335726647
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.240071514
Short name T339
Test name
Test status
Simulation time 677187928 ps
CPU time 3.23 seconds
Started Jun 05 05:14:13 PM PDT 24
Finished Jun 05 05:14:17 PM PDT 24
Peak memory 198076 kb
Host smart-f139e08f-912c-4254-837a-8848fbbff5d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240071514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.240071514
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2033394208
Short name T501
Test name
Test status
Simulation time 32504535 ps
CPU time 0.85 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:14:11 PM PDT 24
Peak memory 195592 kb
Host smart-cf6b2576-6bd2-40ac-9e03-662720b9927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033394208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2033394208
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.542664097
Short name T186
Test name
Test status
Simulation time 281513253 ps
CPU time 1.36 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:14:12 PM PDT 24
Peak memory 196820 kb
Host smart-40247959-fc3f-4a8b-8e2a-746fe4f14591
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542664097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.542664097
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2021445510
Short name T166
Test name
Test status
Simulation time 789049528 ps
CPU time 3.76 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:14:14 PM PDT 24
Peak memory 198044 kb
Host smart-71dd864e-4393-41e1-b3b6-8c782cfc954f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021445510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2021445510
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1810077497
Short name T409
Test name
Test status
Simulation time 224820051 ps
CPU time 1.31 seconds
Started Jun 05 05:14:09 PM PDT 24
Finished Jun 05 05:14:11 PM PDT 24
Peak memory 196436 kb
Host smart-419e4aa6-a1dc-48d1-9b2c-fe10b4ee001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810077497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1810077497
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1925442494
Short name T589
Test name
Test status
Simulation time 74449072 ps
CPU time 1.15 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:14:12 PM PDT 24
Peak memory 196584 kb
Host smart-984797e7-f3a8-4b96-83ab-04985fb2a69f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925442494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1925442494
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.4207905712
Short name T649
Test name
Test status
Simulation time 15264208638 ps
CPU time 162.51 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:16:53 PM PDT 24
Peak memory 198232 kb
Host smart-ef6cbade-4ac2-4e8c-846a-99e8bff422ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207905712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.4207905712
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3133115427
Short name T656
Test name
Test status
Simulation time 22260834938 ps
CPU time 648.96 seconds
Started Jun 05 05:14:11 PM PDT 24
Finished Jun 05 05:25:01 PM PDT 24
Peak memory 198260 kb
Host smart-25cbfad0-591b-48bf-ac9f-d5597e09e94e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3133115427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3133115427
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.158459452
Short name T346
Test name
Test status
Simulation time 77169330 ps
CPU time 0.53 seconds
Started Jun 05 05:14:12 PM PDT 24
Finished Jun 05 05:14:14 PM PDT 24
Peak memory 194636 kb
Host smart-5a9d4b05-86db-49e0-be72-dc82129a3f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158459452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.158459452
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3572579024
Short name T417
Test name
Test status
Simulation time 116838302 ps
CPU time 0.84 seconds
Started Jun 05 05:14:10 PM PDT 24
Finished Jun 05 05:14:12 PM PDT 24
Peak memory 196056 kb
Host smart-2ee78d71-0521-47f1-bba9-7e3d990b963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572579024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3572579024
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2925492455
Short name T498
Test name
Test status
Simulation time 1091883039 ps
CPU time 3.93 seconds
Started Jun 05 05:14:11 PM PDT 24
Finished Jun 05 05:14:16 PM PDT 24
Peak memory 196780 kb
Host smart-38cf2cec-a58c-4e72-84bc-949d8434e50e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925492455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2925492455
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3233412057
Short name T330
Test name
Test status
Simulation time 73842270 ps
CPU time 1.09 seconds
Started Jun 05 05:14:16 PM PDT 24
Finished Jun 05 05:14:18 PM PDT 24
Peak memory 196716 kb
Host smart-dacd5f81-71b0-40ae-990d-7a7f4e3cf52c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233412057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3233412057
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2437547077
Short name T418
Test name
Test status
Simulation time 108557899 ps
CPU time 0.96 seconds
Started Jun 05 05:14:15 PM PDT 24
Finished Jun 05 05:14:17 PM PDT 24
Peak memory 196060 kb
Host smart-61ea3e90-d776-477e-8ead-f61c73366b31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437547077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2437547077
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.861352654
Short name T361
Test name
Test status
Simulation time 140161230 ps
CPU time 2.29 seconds
Started Jun 05 05:14:11 PM PDT 24
Finished Jun 05 05:14:14 PM PDT 24
Peak memory 196428 kb
Host smart-6053b93e-4bcf-43ef-b316-e4a39b4e50ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861352654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.861352654
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2708245473
Short name T524
Test name
Test status
Simulation time 184720309 ps
CPU time 3.15 seconds
Started Jun 05 05:14:13 PM PDT 24
Finished Jun 05 05:14:17 PM PDT 24
Peak memory 198120 kb
Host smart-c1115c03-c26b-4733-9794-0e4f98682688
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708245473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2708245473
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3396506173
Short name T646
Test name
Test status
Simulation time 188237760 ps
CPU time 1.09 seconds
Started Jun 05 05:14:14 PM PDT 24
Finished Jun 05 05:14:16 PM PDT 24
Peak memory 195832 kb
Host smart-ee8abbc4-7db0-48f5-a5b9-1645587254a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396506173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3396506173
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3297320150
Short name T399
Test name
Test status
Simulation time 58258996 ps
CPU time 0.92 seconds
Started Jun 05 05:14:14 PM PDT 24
Finished Jun 05 05:14:16 PM PDT 24
Peak memory 196068 kb
Host smart-d1c4718e-af7e-46d1-b5a5-91c56b5c27b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297320150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3297320150
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3622151640
Short name T362
Test name
Test status
Simulation time 1784089452 ps
CPU time 4.95 seconds
Started Jun 05 05:14:11 PM PDT 24
Finished Jun 05 05:14:16 PM PDT 24
Peak memory 198044 kb
Host smart-a51243c0-f454-4b5e-a02c-189f1f7334f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622151640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3622151640
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1452633258
Short name T199
Test name
Test status
Simulation time 56191389 ps
CPU time 1.03 seconds
Started Jun 05 05:14:14 PM PDT 24
Finished Jun 05 05:14:16 PM PDT 24
Peak memory 195572 kb
Host smart-fa035dad-09a9-437b-b57d-7260c0073276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452633258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1452633258
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2503269396
Short name T26
Test name
Test status
Simulation time 228537974 ps
CPU time 0.99 seconds
Started Jun 05 05:14:12 PM PDT 24
Finished Jun 05 05:14:14 PM PDT 24
Peak memory 195880 kb
Host smart-10f7ddbd-a32f-4b73-a461-7976032379fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503269396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2503269396
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3087017734
Short name T698
Test name
Test status
Simulation time 7812537281 ps
CPU time 117.47 seconds
Started Jun 05 05:14:12 PM PDT 24
Finished Jun 05 05:16:10 PM PDT 24
Peak memory 198188 kb
Host smart-9d2871b7-eb0d-49af-aeda-025b4f67d080
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087017734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3087017734
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2388364078
Short name T324
Test name
Test status
Simulation time 15284181 ps
CPU time 0.58 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:21 PM PDT 24
Peak memory 194604 kb
Host smart-27d3b819-f39a-41f7-92b3-098892938ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388364078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2388364078
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2539402044
Short name T259
Test name
Test status
Simulation time 67955825 ps
CPU time 0.71 seconds
Started Jun 05 05:14:19 PM PDT 24
Finished Jun 05 05:14:21 PM PDT 24
Peak memory 195412 kb
Host smart-b87e0352-c6a2-4a6d-a080-f40264a28782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539402044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2539402044
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.393651715
Short name T599
Test name
Test status
Simulation time 525341183 ps
CPU time 26.43 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:48 PM PDT 24
Peak memory 197000 kb
Host smart-414b4689-e8a5-41a7-a66f-bc0ef2edd393
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393651715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.393651715
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.4134422782
Short name T661
Test name
Test status
Simulation time 48855198 ps
CPU time 0.83 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:22 PM PDT 24
Peak memory 196812 kb
Host smart-67cb3f1c-0d0d-4805-86ff-4130d6227b1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134422782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.4134422782
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.784891766
Short name T155
Test name
Test status
Simulation time 227158642 ps
CPU time 0.97 seconds
Started Jun 05 05:14:18 PM PDT 24
Finished Jun 05 05:14:20 PM PDT 24
Peak memory 195908 kb
Host smart-59cbb956-804f-4c9c-a8ae-15a6bc41e228
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784891766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.784891766
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3395574490
Short name T207
Test name
Test status
Simulation time 74411202 ps
CPU time 1.28 seconds
Started Jun 05 05:14:19 PM PDT 24
Finished Jun 05 05:14:21 PM PDT 24
Peak memory 196416 kb
Host smart-c0b49c0e-665c-4ff4-b9bb-fe0222739a4c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395574490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3395574490
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2668083033
Short name T61
Test name
Test status
Simulation time 53113687 ps
CPU time 0.87 seconds
Started Jun 05 05:14:21 PM PDT 24
Finished Jun 05 05:14:23 PM PDT 24
Peak memory 194464 kb
Host smart-8b932f06-7993-4070-8f2e-8aefb75100be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668083033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2668083033
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1990916437
Short name T500
Test name
Test status
Simulation time 100144736 ps
CPU time 0.93 seconds
Started Jun 05 05:14:14 PM PDT 24
Finished Jun 05 05:14:16 PM PDT 24
Peak memory 196096 kb
Host smart-498a2cc2-8985-4f42-a0c7-d237630af49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990916437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1990916437
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.422412501
Short name T131
Test name
Test status
Simulation time 176312207 ps
CPU time 1.21 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:22 PM PDT 24
Peak memory 196824 kb
Host smart-37053ada-6c11-470e-85c7-7acc44f6c7fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422412501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.422412501
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.137613019
Short name T665
Test name
Test status
Simulation time 508676194 ps
CPU time 2.46 seconds
Started Jun 05 05:14:16 PM PDT 24
Finished Jun 05 05:14:19 PM PDT 24
Peak memory 198100 kb
Host smart-2835f2c2-7927-4eb4-bae5-59f25539894a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137613019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.137613019
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2602366637
Short name T86
Test name
Test status
Simulation time 118828196 ps
CPU time 0.96 seconds
Started Jun 05 05:14:15 PM PDT 24
Finished Jun 05 05:14:17 PM PDT 24
Peak memory 196432 kb
Host smart-20b5387f-0bb7-4edc-a7e0-8dff65d48fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602366637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2602366637
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3112411043
Short name T579
Test name
Test status
Simulation time 492985088 ps
CPU time 1.36 seconds
Started Jun 05 05:14:14 PM PDT 24
Finished Jun 05 05:14:16 PM PDT 24
Peak memory 196976 kb
Host smart-b4ab4343-e86b-4517-b49c-cb779c9cd52b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112411043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3112411043
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.806604258
Short name T575
Test name
Test status
Simulation time 28716388754 ps
CPU time 123.14 seconds
Started Jun 05 05:14:19 PM PDT 24
Finished Jun 05 05:16:23 PM PDT 24
Peak memory 198204 kb
Host smart-14b5c1c7-0253-4390-99c5-664863ddd99b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806604258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.806604258
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1888500743
Short name T608
Test name
Test status
Simulation time 14450317 ps
CPU time 0.59 seconds
Started Jun 05 05:14:19 PM PDT 24
Finished Jun 05 05:14:21 PM PDT 24
Peak memory 193968 kb
Host smart-7400831f-627d-4965-beb9-32e863eb6294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888500743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1888500743
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.561071331
Short name T435
Test name
Test status
Simulation time 37366922 ps
CPU time 0.9 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:22 PM PDT 24
Peak memory 196528 kb
Host smart-7f3d41f1-ca38-457c-83f5-773c84f60115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561071331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.561071331
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2262645418
Short name T522
Test name
Test status
Simulation time 482318168 ps
CPU time 7.03 seconds
Started Jun 05 05:14:21 PM PDT 24
Finished Jun 05 05:14:29 PM PDT 24
Peak memory 197004 kb
Host smart-8b11c57b-09d5-413f-86ea-53b445fe3589
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262645418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2262645418
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.4097181149
Short name T188
Test name
Test status
Simulation time 66974611 ps
CPU time 1.01 seconds
Started Jun 05 05:14:21 PM PDT 24
Finished Jun 05 05:14:23 PM PDT 24
Peak memory 196500 kb
Host smart-156df0c9-b384-4fc9-a383-a5d5b24ac7ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097181149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.4097181149
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1566078392
Short name T202
Test name
Test status
Simulation time 36200091 ps
CPU time 0.81 seconds
Started Jun 05 05:14:18 PM PDT 24
Finished Jun 05 05:14:20 PM PDT 24
Peak memory 195644 kb
Host smart-63d985db-6d1d-48d1-8dba-910f105e7940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566078392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1566078392
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.4220233311
Short name T140
Test name
Test status
Simulation time 525213779 ps
CPU time 2.14 seconds
Started Jun 05 05:14:18 PM PDT 24
Finished Jun 05 05:14:21 PM PDT 24
Peak memory 198068 kb
Host smart-51e075f9-38d6-4806-9ebe-bea371c7b6b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220233311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.4220233311
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2625088343
Short name T408
Test name
Test status
Simulation time 243343141 ps
CPU time 1.95 seconds
Started Jun 05 05:14:21 PM PDT 24
Finished Jun 05 05:14:24 PM PDT 24
Peak memory 197236 kb
Host smart-ff8d1ead-4e47-483e-b36f-62aa76a18154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625088343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2625088343
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1941830373
Short name T347
Test name
Test status
Simulation time 20710567 ps
CPU time 0.89 seconds
Started Jun 05 05:14:16 PM PDT 24
Finished Jun 05 05:14:18 PM PDT 24
Peak memory 196756 kb
Host smart-2251cc7b-27c2-4ef3-8b08-5af774a2971a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941830373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1941830373
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3090067868
Short name T248
Test name
Test status
Simulation time 275969111 ps
CPU time 1.44 seconds
Started Jun 05 05:14:21 PM PDT 24
Finished Jun 05 05:14:23 PM PDT 24
Peak memory 195868 kb
Host smart-53219ab8-2c40-4864-a413-ecf0b4ee41f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090067868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3090067868
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1760185933
Short name T245
Test name
Test status
Simulation time 598115538 ps
CPU time 4.93 seconds
Started Jun 05 05:14:18 PM PDT 24
Finished Jun 05 05:14:24 PM PDT 24
Peak memory 197884 kb
Host smart-5f180dc2-85b9-400a-a76b-473e7f023b25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760185933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1760185933
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.486286169
Short name T704
Test name
Test status
Simulation time 332099093 ps
CPU time 1.47 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:23 PM PDT 24
Peak memory 196840 kb
Host smart-9bfbdf2b-9286-4bba-8f43-4b4a5e4bed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486286169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.486286169
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1086959743
Short name T444
Test name
Test status
Simulation time 252890639 ps
CPU time 1.1 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:22 PM PDT 24
Peak memory 195544 kb
Host smart-98490b09-a4ee-42a7-b11f-f42e39bd86d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086959743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1086959743
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.987808111
Short name T415
Test name
Test status
Simulation time 16400654572 ps
CPU time 82.05 seconds
Started Jun 05 05:14:21 PM PDT 24
Finished Jun 05 05:15:44 PM PDT 24
Peak memory 198176 kb
Host smart-54cd68d9-3737-4379-a99a-984141eca013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987808111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.987808111
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.4065140797
Short name T215
Test name
Test status
Simulation time 12898777 ps
CPU time 0.57 seconds
Started Jun 05 05:14:26 PM PDT 24
Finished Jun 05 05:14:27 PM PDT 24
Peak memory 194604 kb
Host smart-99343985-3f0d-48dc-8bf4-12a5dc39d8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065140797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.4065140797
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2303035052
Short name T333
Test name
Test status
Simulation time 99034057 ps
CPU time 0.9 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:22 PM PDT 24
Peak memory 195832 kb
Host smart-c5879c69-d500-4a21-9a40-38d2d3e3dfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303035052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2303035052
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1954135873
Short name T430
Test name
Test status
Simulation time 1584248777 ps
CPU time 22.56 seconds
Started Jun 05 05:14:26 PM PDT 24
Finished Jun 05 05:14:49 PM PDT 24
Peak memory 196956 kb
Host smart-e025a601-000b-4d72-8ee0-fec3c7b0fcb2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954135873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1954135873
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1618894950
Short name T58
Test name
Test status
Simulation time 129025611 ps
CPU time 1.03 seconds
Started Jun 05 05:14:25 PM PDT 24
Finished Jun 05 05:14:26 PM PDT 24
Peak memory 196676 kb
Host smart-f6c20493-8b7d-4d27-b135-49b18f846e8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618894950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1618894950
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1367001270
Short name T540
Test name
Test status
Simulation time 145733660 ps
CPU time 1.18 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:23 PM PDT 24
Peak memory 196708 kb
Host smart-0ba99ced-997d-4041-ad30-443f45fbd220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367001270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1367001270
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.847830432
Short name T385
Test name
Test status
Simulation time 54452367 ps
CPU time 2.38 seconds
Started Jun 05 05:14:17 PM PDT 24
Finished Jun 05 05:14:20 PM PDT 24
Peak memory 198320 kb
Host smart-0f99ff0c-13c0-4078-9eb6-b41bd238f59c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847830432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.847830432
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1603903042
Short name T662
Test name
Test status
Simulation time 661014849 ps
CPU time 1.48 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:22 PM PDT 24
Peak memory 197336 kb
Host smart-3ba05d19-1be9-4a47-af01-b7939bb3588f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603903042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1603903042
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.379937665
Short name T176
Test name
Test status
Simulation time 41387485 ps
CPU time 1.12 seconds
Started Jun 05 05:14:19 PM PDT 24
Finished Jun 05 05:14:21 PM PDT 24
Peak memory 195812 kb
Host smart-bda1b770-d20a-4ea0-8ff4-dbf665075180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379937665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.379937665
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.693781177
Short name T314
Test name
Test status
Simulation time 70003185 ps
CPU time 1.24 seconds
Started Jun 05 05:14:18 PM PDT 24
Finished Jun 05 05:14:21 PM PDT 24
Peak memory 197092 kb
Host smart-b66c970e-c515-4cf6-942f-9d311a6bf6c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693781177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.693781177
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3207271668
Short name T433
Test name
Test status
Simulation time 295349491 ps
CPU time 2.05 seconds
Started Jun 05 05:14:29 PM PDT 24
Finished Jun 05 05:14:31 PM PDT 24
Peak memory 197992 kb
Host smart-15c3d334-f301-4500-88d5-bf992c08e1e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207271668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3207271668
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1370664943
Short name T285
Test name
Test status
Simulation time 61632030 ps
CPU time 0.79 seconds
Started Jun 05 05:14:20 PM PDT 24
Finished Jun 05 05:14:22 PM PDT 24
Peak memory 195276 kb
Host smart-3fdc432b-7315-46e0-94ce-6094d6f22295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370664943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1370664943
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.776629879
Short name T610
Test name
Test status
Simulation time 26515759 ps
CPU time 0.76 seconds
Started Jun 05 05:14:17 PM PDT 24
Finished Jun 05 05:14:19 PM PDT 24
Peak memory 194996 kb
Host smart-e2fa466a-073c-4946-8aaa-ed07e4d319e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776629879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.776629879
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3283859557
Short name T87
Test name
Test status
Simulation time 2796161777 ps
CPU time 62.55 seconds
Started Jun 05 05:14:28 PM PDT 24
Finished Jun 05 05:15:31 PM PDT 24
Peak memory 198228 kb
Host smart-efd1fa7f-826e-40de-aac4-3b5461aeb3b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283859557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3283859557
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3879461411
Short name T865
Test name
Test status
Simulation time 522123120 ps
CPU time 1.18 seconds
Started Jun 05 04:20:10 PM PDT 24
Finished Jun 05 04:20:13 PM PDT 24
Peak memory 197020 kb
Host smart-7957c926-0423-4323-a3ef-70bf904afb73
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3879461411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3879461411
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.607365146
Short name T903
Test name
Test status
Simulation time 151296411 ps
CPU time 0.85 seconds
Started Jun 05 04:20:13 PM PDT 24
Finished Jun 05 04:20:15 PM PDT 24
Peak memory 196812 kb
Host smart-99c04dc4-c92e-492c-b4ee-5e8fed7c7d88
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607365146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.607365146
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2536600716
Short name T927
Test name
Test status
Simulation time 165714592 ps
CPU time 1.24 seconds
Started Jun 05 04:20:09 PM PDT 24
Finished Jun 05 04:20:11 PM PDT 24
Peak memory 197168 kb
Host smart-ec31d77d-f922-4156-9bf9-34d0b2059db9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2536600716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2536600716
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3556768756
Short name T866
Test name
Test status
Simulation time 201084305 ps
CPU time 1.02 seconds
Started Jun 05 04:20:14 PM PDT 24
Finished Jun 05 04:20:16 PM PDT 24
Peak memory 198248 kb
Host smart-8dbe9c02-641c-426a-9887-c63d23c96ff8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556768756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3556768756
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2705688659
Short name T859
Test name
Test status
Simulation time 151533888 ps
CPU time 1.28 seconds
Started Jun 05 04:20:10 PM PDT 24
Finished Jun 05 04:20:12 PM PDT 24
Peak memory 196692 kb
Host smart-efca3a97-0732-4b17-a2cd-32c1e7b731d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2705688659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2705688659
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.305236785
Short name T888
Test name
Test status
Simulation time 31907532 ps
CPU time 0.92 seconds
Started Jun 05 04:20:11 PM PDT 24
Finished Jun 05 04:20:13 PM PDT 24
Peak memory 196608 kb
Host smart-7454a1ae-bc1c-4f39-9fb4-c0cacd02ae0c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305236785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.305236785
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2173336609
Short name T889
Test name
Test status
Simulation time 644106861 ps
CPU time 0.99 seconds
Started Jun 05 04:20:11 PM PDT 24
Finished Jun 05 04:20:13 PM PDT 24
Peak memory 197680 kb
Host smart-7581b720-bc77-4f6d-94b7-b86a73a0317c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2173336609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2173336609
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.897761132
Short name T934
Test name
Test status
Simulation time 86380710 ps
CPU time 1.01 seconds
Started Jun 05 04:20:13 PM PDT 24
Finished Jun 05 04:20:15 PM PDT 24
Peak memory 196816 kb
Host smart-cf4d7d27-ed6c-4ce9-b0f7-f8a43ffff5f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897761132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.897761132
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2576931689
Short name T860
Test name
Test status
Simulation time 292718894 ps
CPU time 1.2 seconds
Started Jun 05 04:20:15 PM PDT 24
Finished Jun 05 04:20:17 PM PDT 24
Peak memory 195260 kb
Host smart-86e883fd-2147-4dd1-8eed-c05728e6cea4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2576931689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2576931689
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.356992613
Short name T864
Test name
Test status
Simulation time 758623030 ps
CPU time 0.97 seconds
Started Jun 05 04:20:10 PM PDT 24
Finished Jun 05 04:20:11 PM PDT 24
Peak memory 196792 kb
Host smart-ecffed30-af5b-4c15-bbe4-a40572a7ea7c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356992613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.356992613
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.498540480
Short name T938
Test name
Test status
Simulation time 218247515 ps
CPU time 1.21 seconds
Started Jun 05 04:20:12 PM PDT 24
Finished Jun 05 04:20:14 PM PDT 24
Peak memory 197068 kb
Host smart-939bfe00-7211-4cad-a45d-8d8b5d6aa389
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=498540480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.498540480
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4061246858
Short name T907
Test name
Test status
Simulation time 47207812 ps
CPU time 1.19 seconds
Started Jun 05 04:20:09 PM PDT 24
Finished Jun 05 04:20:11 PM PDT 24
Peak memory 196960 kb
Host smart-45605fc3-beda-49c5-a842-3bf075df5ea2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061246858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4061246858
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4094180922
Short name T845
Test name
Test status
Simulation time 57711801 ps
CPU time 1.09 seconds
Started Jun 05 04:20:15 PM PDT 24
Finished Jun 05 04:20:17 PM PDT 24
Peak memory 196592 kb
Host smart-19ed6e39-a544-47e9-940b-03a0a33c88ee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4094180922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4094180922
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1132820222
Short name T902
Test name
Test status
Simulation time 78789606 ps
CPU time 0.78 seconds
Started Jun 05 04:20:13 PM PDT 24
Finished Jun 05 04:20:14 PM PDT 24
Peak memory 196416 kb
Host smart-c812c61d-21d9-434b-8c54-f0b9a12399e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132820222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1132820222
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1057630128
Short name T867
Test name
Test status
Simulation time 144870053 ps
CPU time 1.14 seconds
Started Jun 05 04:20:09 PM PDT 24
Finished Jun 05 04:20:10 PM PDT 24
Peak memory 196200 kb
Host smart-7e581d22-4356-4d79-9ecb-d8e62e2ed429
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1057630128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1057630128
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1118786859
Short name T873
Test name
Test status
Simulation time 140375048 ps
CPU time 1.04 seconds
Started Jun 05 04:20:15 PM PDT 24
Finished Jun 05 04:20:16 PM PDT 24
Peak memory 196152 kb
Host smart-799fd6e9-97cc-46c9-b70a-2507cb0fe072
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118786859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1118786859
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3107907142
Short name T933
Test name
Test status
Simulation time 26384888 ps
CPU time 0.82 seconds
Started Jun 05 04:20:11 PM PDT 24
Finished Jun 05 04:20:13 PM PDT 24
Peak memory 195524 kb
Host smart-97393ef2-2a77-448e-9a91-c04a1e5ebde5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3107907142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3107907142
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.553050965
Short name T935
Test name
Test status
Simulation time 53235177 ps
CPU time 1.11 seconds
Started Jun 05 04:20:10 PM PDT 24
Finished Jun 05 04:20:13 PM PDT 24
Peak memory 195984 kb
Host smart-a3f211c7-b040-47f8-a983-2b9667d12a94
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553050965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.553050965
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4098880012
Short name T855
Test name
Test status
Simulation time 148720519 ps
CPU time 1.38 seconds
Started Jun 05 04:20:14 PM PDT 24
Finished Jun 05 04:20:16 PM PDT 24
Peak memory 196880 kb
Host smart-ed62379c-40fe-422e-89e0-97c818137fc2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4098880012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.4098880012
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3244177373
Short name T869
Test name
Test status
Simulation time 1016153987 ps
CPU time 1.43 seconds
Started Jun 05 04:20:08 PM PDT 24
Finished Jun 05 04:20:10 PM PDT 24
Peak memory 196940 kb
Host smart-00ebe504-0749-4dc3-9d6f-41bcfc6af38f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244177373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3244177373
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3270628841
Short name T924
Test name
Test status
Simulation time 225292106 ps
CPU time 1.07 seconds
Started Jun 05 04:20:15 PM PDT 24
Finished Jun 05 04:20:17 PM PDT 24
Peak memory 196324 kb
Host smart-ef798158-d98e-4f2a-a3bc-eb2ff5104c68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3270628841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3270628841
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.721800215
Short name T918
Test name
Test status
Simulation time 83913661 ps
CPU time 0.91 seconds
Started Jun 05 04:20:15 PM PDT 24
Finished Jun 05 04:20:17 PM PDT 24
Peak memory 198180 kb
Host smart-c72bb5e6-dd57-41ed-8194-17bb4e7e0a0d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721800215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.721800215
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3320826395
Short name T899
Test name
Test status
Simulation time 57195739 ps
CPU time 1.07 seconds
Started Jun 05 04:20:26 PM PDT 24
Finished Jun 05 04:20:28 PM PDT 24
Peak memory 196928 kb
Host smart-da287427-354d-462f-a9f1-aa1cf13ce7f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3320826395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3320826395
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3633605399
Short name T928
Test name
Test status
Simulation time 69498009 ps
CPU time 1.24 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 198232 kb
Host smart-58909e8a-d1b2-43c1-b8ad-00def2ca6dc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633605399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3633605399
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.280247114
Short name T872
Test name
Test status
Simulation time 39539713 ps
CPU time 1.05 seconds
Started Jun 05 04:20:13 PM PDT 24
Finished Jun 05 04:20:15 PM PDT 24
Peak memory 196800 kb
Host smart-f1aa70b3-3c59-4068-b959-7feccc402c2c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=280247114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.280247114
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2125857219
Short name T914
Test name
Test status
Simulation time 325576356 ps
CPU time 1.22 seconds
Started Jun 05 04:20:13 PM PDT 24
Finished Jun 05 04:20:15 PM PDT 24
Peak memory 197000 kb
Host smart-03c74254-146f-4a5b-a579-389dab6a98e3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125857219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2125857219
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.678581933
Short name T905
Test name
Test status
Simulation time 118584612 ps
CPU time 1.13 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 196904 kb
Host smart-11e3a344-d214-409a-a103-b41905a38762
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=678581933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.678581933
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2138142681
Short name T842
Test name
Test status
Simulation time 356987796 ps
CPU time 0.93 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:22 PM PDT 24
Peak memory 196816 kb
Host smart-71756a19-7d1c-4113-8f65-ce469f5c609a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138142681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2138142681
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3107798903
Short name T941
Test name
Test status
Simulation time 95128439 ps
CPU time 1.34 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:24 PM PDT 24
Peak memory 196660 kb
Host smart-9c542c88-4090-4bf7-b61f-29ba73d2c7ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3107798903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3107798903
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1506561402
Short name T898
Test name
Test status
Simulation time 52536126 ps
CPU time 0.81 seconds
Started Jun 05 04:20:20 PM PDT 24
Finished Jun 05 04:20:22 PM PDT 24
Peak memory 195744 kb
Host smart-74c458ce-a8da-4c36-abee-a773ce4085b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506561402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1506561402
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3968522472
Short name T917
Test name
Test status
Simulation time 190432615 ps
CPU time 0.85 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:27 PM PDT 24
Peak memory 195756 kb
Host smart-e535b23d-dd94-4dca-b141-037bdaee65fd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3968522472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3968522472
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3396037146
Short name T879
Test name
Test status
Simulation time 180257102 ps
CPU time 1.3 seconds
Started Jun 05 04:20:20 PM PDT 24
Finished Jun 05 04:20:22 PM PDT 24
Peak memory 197220 kb
Host smart-b72e8403-50d2-4e66-b15e-5c829adb921e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396037146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3396037146
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.919742524
Short name T929
Test name
Test status
Simulation time 169835502 ps
CPU time 1.26 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:25 PM PDT 24
Peak memory 198196 kb
Host smart-3c25f594-0cbf-4f2b-b573-f0a83de52a7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=919742524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.919742524
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.323612527
Short name T861
Test name
Test status
Simulation time 221935702 ps
CPU time 1.24 seconds
Started Jun 05 04:20:22 PM PDT 24
Finished Jun 05 04:20:24 PM PDT 24
Peak memory 198204 kb
Host smart-5d856302-eb4a-4209-96cb-555037dfcc98
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323612527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.323612527
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2640891031
Short name T900
Test name
Test status
Simulation time 271484526 ps
CPU time 1.25 seconds
Started Jun 05 04:20:22 PM PDT 24
Finished Jun 05 04:20:25 PM PDT 24
Peak memory 195812 kb
Host smart-ce68a6bf-313f-4689-8f78-ff2d985604d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2640891031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2640891031
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2426996089
Short name T890
Test name
Test status
Simulation time 110452514 ps
CPU time 1.15 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 196808 kb
Host smart-276a657f-1faf-475e-89e4-64f34b0b757c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426996089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2426996089
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3729116367
Short name T852
Test name
Test status
Simulation time 146963968 ps
CPU time 1.36 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 196572 kb
Host smart-4289f224-0825-4d3c-9215-59be9609f7a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3729116367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3729116367
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1971960300
Short name T846
Test name
Test status
Simulation time 216288557 ps
CPU time 0.98 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 197008 kb
Host smart-ae35a472-049c-4265-b534-9065981d58e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971960300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1971960300
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2007114897
Short name T850
Test name
Test status
Simulation time 60001535 ps
CPU time 1.06 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 198228 kb
Host smart-72842354-940b-4118-96b3-3125c26496dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2007114897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2007114897
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2275110560
Short name T847
Test name
Test status
Simulation time 227981688 ps
CPU time 1.28 seconds
Started Jun 05 04:20:22 PM PDT 24
Finished Jun 05 04:20:24 PM PDT 24
Peak memory 198300 kb
Host smart-a6e0fd41-3348-438b-9779-566930190e69
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275110560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2275110560
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.957731718
Short name T854
Test name
Test status
Simulation time 55434883 ps
CPU time 1.47 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:27 PM PDT 24
Peak memory 197116 kb
Host smart-76fa4607-eaee-4a8b-beec-7c3fe59c94ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=957731718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.957731718
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.649344099
Short name T884
Test name
Test status
Simulation time 211436485 ps
CPU time 0.97 seconds
Started Jun 05 04:20:22 PM PDT 24
Finished Jun 05 04:20:24 PM PDT 24
Peak memory 197508 kb
Host smart-9879c04a-673b-46a8-9607-b013beefd0f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649344099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.649344099
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3829714565
Short name T897
Test name
Test status
Simulation time 111121119 ps
CPU time 1.11 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 196744 kb
Host smart-03168ff0-ff55-4a9e-8b68-b237248de3eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3829714565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3829714565
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2122141908
Short name T856
Test name
Test status
Simulation time 100068240 ps
CPU time 1.41 seconds
Started Jun 05 04:20:22 PM PDT 24
Finished Jun 05 04:20:25 PM PDT 24
Peak memory 198216 kb
Host smart-195193c3-857c-49c5-be65-39d46e6a8863
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122141908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2122141908
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1046533732
Short name T871
Test name
Test status
Simulation time 188276730 ps
CPU time 1.49 seconds
Started Jun 05 04:20:25 PM PDT 24
Finished Jun 05 04:20:27 PM PDT 24
Peak memory 196864 kb
Host smart-619fc8e6-ee12-439e-827e-c35c5b6df250
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1046533732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1046533732
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1729670376
Short name T921
Test name
Test status
Simulation time 75060947 ps
CPU time 1.3 seconds
Started Jun 05 04:20:27 PM PDT 24
Finished Jun 05 04:20:29 PM PDT 24
Peak memory 195912 kb
Host smart-d266121f-e3b4-47ef-8e41-324a3bf76b7c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729670376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1729670376
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2556347386
Short name T870
Test name
Test status
Simulation time 109256836 ps
CPU time 0.98 seconds
Started Jun 05 04:20:15 PM PDT 24
Finished Jun 05 04:20:16 PM PDT 24
Peak memory 196768 kb
Host smart-75e54949-293d-4b2e-914d-a1430d7f4211
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2556347386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2556347386
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1480841645
Short name T919
Test name
Test status
Simulation time 225814239 ps
CPU time 0.83 seconds
Started Jun 05 04:20:10 PM PDT 24
Finished Jun 05 04:20:13 PM PDT 24
Peak memory 195564 kb
Host smart-dd11cc7e-f0eb-46fa-9803-e404eb5c06c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480841645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1480841645
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1805377497
Short name T892
Test name
Test status
Simulation time 154468102 ps
CPU time 1.45 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 197004 kb
Host smart-2ee8e948-5535-4288-8de2-71a6e5f00a6c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1805377497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1805377497
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.61343006
Short name T925
Test name
Test status
Simulation time 181124657 ps
CPU time 1.21 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 198244 kb
Host smart-395858c9-c59b-47d0-8a82-8b8831e2c5f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61343006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.61343006
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2867618293
Short name T894
Test name
Test status
Simulation time 37282638 ps
CPU time 1.18 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 197216 kb
Host smart-0e0c0289-c4f2-4d4f-a724-2fffc05447e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2867618293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2867618293
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2664891149
Short name T896
Test name
Test status
Simulation time 65663475 ps
CPU time 1.24 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 198272 kb
Host smart-414f9273-33eb-4d3b-ac98-96871d06c808
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664891149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2664891149
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.156951084
Short name T923
Test name
Test status
Simulation time 292630775 ps
CPU time 1.46 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:24 PM PDT 24
Peak memory 198208 kb
Host smart-80b24227-eb12-4ff9-8aec-e5ba293fcc24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=156951084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.156951084
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2759021654
Short name T844
Test name
Test status
Simulation time 102187819 ps
CPU time 1.37 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 198276 kb
Host smart-d018df1f-1860-4dd3-9e02-0144543f68cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759021654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2759021654
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2723278354
Short name T862
Test name
Test status
Simulation time 45926809 ps
CPU time 1.02 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 198352 kb
Host smart-e648534d-c223-49e4-8db0-aca9ed177a14
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2723278354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2723278354
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.521432638
Short name T885
Test name
Test status
Simulation time 270844349 ps
CPU time 1.19 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 198244 kb
Host smart-9863f618-8d76-4446-90f9-7a97773e90b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521432638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.521432638
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3860186062
Short name T911
Test name
Test status
Simulation time 194345472 ps
CPU time 1.49 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:27 PM PDT 24
Peak memory 196840 kb
Host smart-548aeadf-e492-4d2d-8274-0b9728cffe0b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3860186062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3860186062
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3263662827
Short name T868
Test name
Test status
Simulation time 54573535 ps
CPU time 1.39 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 198236 kb
Host smart-9e9b98d3-7231-4533-bf51-8cf99d9b6865
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263662827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3263662827
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3785210002
Short name T882
Test name
Test status
Simulation time 93714499 ps
CPU time 1.05 seconds
Started Jun 05 04:20:20 PM PDT 24
Finished Jun 05 04:20:22 PM PDT 24
Peak memory 196800 kb
Host smart-30e1eddc-5af4-4955-8449-eaf9a7524888
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3785210002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3785210002
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2985730503
Short name T920
Test name
Test status
Simulation time 198048265 ps
CPU time 1.21 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 197024 kb
Host smart-7ade842e-737e-4431-b20c-074b14328200
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985730503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2985730503
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2214599561
Short name T878
Test name
Test status
Simulation time 74293954 ps
CPU time 1.18 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:25 PM PDT 24
Peak memory 195848 kb
Host smart-38b8a01d-6db1-4b12-afef-a6fde96d5ddd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2214599561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2214599561
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.362222082
Short name T904
Test name
Test status
Simulation time 951076305 ps
CPU time 1.24 seconds
Started Jun 05 04:20:19 PM PDT 24
Finished Jun 05 04:20:21 PM PDT 24
Peak memory 198252 kb
Host smart-8fbda5de-696d-4120-8480-22d4f8d32915
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362222082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.362222082
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2637641713
Short name T909
Test name
Test status
Simulation time 438887204 ps
CPU time 0.91 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 195712 kb
Host smart-35d3fb72-c74f-49f5-a0bc-8c410488620a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2637641713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2637641713
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.918220817
Short name T916
Test name
Test status
Simulation time 137516026 ps
CPU time 0.86 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:27 PM PDT 24
Peak memory 196524 kb
Host smart-13349e6e-c4a8-41b2-b3d6-af9e2c93da40
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918220817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.918220817
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1023110965
Short name T913
Test name
Test status
Simulation time 143460910 ps
CPU time 1.37 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 197128 kb
Host smart-ed765ab5-e0ce-4783-9332-c0bb40e4c1f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1023110965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1023110965
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3640874379
Short name T906
Test name
Test status
Simulation time 50365592 ps
CPU time 1.43 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 197008 kb
Host smart-468bc41f-13be-460d-b0e2-ccbaa7c85d2e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640874379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3640874379
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.684327851
Short name T901
Test name
Test status
Simulation time 69877952 ps
CPU time 1.08 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 196764 kb
Host smart-0a31034e-280a-414a-b932-e2ff02375d1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=684327851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.684327851
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2020476006
Short name T910
Test name
Test status
Simulation time 93872559 ps
CPU time 1.4 seconds
Started Jun 05 04:20:22 PM PDT 24
Finished Jun 05 04:20:25 PM PDT 24
Peak memory 195936 kb
Host smart-8ac6f048-6b6e-4715-ae2a-b374ab38f4c5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020476006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2020476006
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2179418259
Short name T875
Test name
Test status
Simulation time 1397230293 ps
CPU time 1.33 seconds
Started Jun 05 04:20:08 PM PDT 24
Finished Jun 05 04:20:10 PM PDT 24
Peak memory 197168 kb
Host smart-eead0917-684b-444c-a7af-3d05ff95e7ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2179418259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2179418259
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3431879812
Short name T853
Test name
Test status
Simulation time 261155408 ps
CPU time 1.3 seconds
Started Jun 05 04:20:10 PM PDT 24
Finished Jun 05 04:20:12 PM PDT 24
Peak memory 197212 kb
Host smart-14efa332-a37d-4f45-b595-e1fbe4536871
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431879812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3431879812
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4185739944
Short name T930
Test name
Test status
Simulation time 397159676 ps
CPU time 1.07 seconds
Started Jun 05 04:20:24 PM PDT 24
Finished Jun 05 04:20:27 PM PDT 24
Peak memory 196916 kb
Host smart-1a0d7ce3-c3ea-44df-8c1f-e613053f8fab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4185739944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.4185739944
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3701641848
Short name T891
Test name
Test status
Simulation time 154948264 ps
CPU time 0.95 seconds
Started Jun 05 04:20:22 PM PDT 24
Finished Jun 05 04:20:24 PM PDT 24
Peak memory 196820 kb
Host smart-c48dd1be-ec1b-4b0b-b04a-73b8c850ff9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701641848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3701641848
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2419800720
Short name T863
Test name
Test status
Simulation time 295964187 ps
CPU time 0.88 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:25 PM PDT 24
Peak memory 198128 kb
Host smart-f3a79d2b-9eb6-464f-8456-92673afbb2ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2419800720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2419800720
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3770724816
Short name T937
Test name
Test status
Simulation time 25509636 ps
CPU time 0.75 seconds
Started Jun 05 04:20:22 PM PDT 24
Finished Jun 05 04:20:24 PM PDT 24
Peak memory 196304 kb
Host smart-cb61c347-0592-4054-b481-0563fd6af136
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770724816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3770724816
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.790266805
Short name T881
Test name
Test status
Simulation time 149761248 ps
CPU time 1.24 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 198204 kb
Host smart-3e01eaf2-80bf-4787-a325-ac06b65dd80d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=790266805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.790266805
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3972128757
Short name T895
Test name
Test status
Simulation time 97322709 ps
CPU time 1.31 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 197256 kb
Host smart-a7b9bd07-bb9d-4b13-b094-1c35e216afaa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972128757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3972128757
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3896345978
Short name T940
Test name
Test status
Simulation time 130895862 ps
CPU time 1.12 seconds
Started Jun 05 04:20:21 PM PDT 24
Finished Jun 05 04:20:22 PM PDT 24
Peak memory 196012 kb
Host smart-bfb23661-f51d-427f-843f-234404d5bee3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3896345978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3896345978
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4172328803
Short name T883
Test name
Test status
Simulation time 203186851 ps
CPU time 1.14 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:25 PM PDT 24
Peak memory 196884 kb
Host smart-732efd0e-0761-40ef-af3f-5421905c250d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172328803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4172328803
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2436667099
Short name T932
Test name
Test status
Simulation time 1075385843 ps
CPU time 1.01 seconds
Started Jun 05 04:20:23 PM PDT 24
Finished Jun 05 04:20:25 PM PDT 24
Peak memory 195956 kb
Host smart-184a3fe2-13ae-4c9a-a380-e82b87e8d92b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2436667099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2436667099
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.844248230
Short name T877
Test name
Test status
Simulation time 196433786 ps
CPU time 1.14 seconds
Started Jun 05 04:20:25 PM PDT 24
Finished Jun 05 04:20:28 PM PDT 24
Peak memory 196764 kb
Host smart-8f471abf-f36e-4bac-a317-60801b48c198
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844248230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.844248230
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2048968124
Short name T848
Test name
Test status
Simulation time 62047465 ps
CPU time 0.77 seconds
Started Jun 05 04:20:25 PM PDT 24
Finished Jun 05 04:20:27 PM PDT 24
Peak memory 195652 kb
Host smart-1a0939d5-7883-4ed9-ba85-3265752f5a6f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2048968124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2048968124
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1292862619
Short name T857
Test name
Test status
Simulation time 76748731 ps
CPU time 0.92 seconds
Started Jun 05 04:20:26 PM PDT 24
Finished Jun 05 04:20:28 PM PDT 24
Peak memory 195824 kb
Host smart-4b55554a-8c12-45b9-a101-063017572e77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292862619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1292862619
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2868175581
Short name T912
Test name
Test status
Simulation time 500549029 ps
CPU time 1.5 seconds
Started Jun 05 04:20:26 PM PDT 24
Finished Jun 05 04:20:28 PM PDT 24
Peak memory 198116 kb
Host smart-8192cb91-deef-49c5-a1e0-210ff4d623f1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2868175581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2868175581
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2730757449
Short name T858
Test name
Test status
Simulation time 143893538 ps
CPU time 1.15 seconds
Started Jun 05 04:20:26 PM PDT 24
Finished Jun 05 04:20:28 PM PDT 24
Peak memory 198152 kb
Host smart-db7eba0e-3eed-4309-8da1-cff944c2188d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730757449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2730757449
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1339985143
Short name T876
Test name
Test status
Simulation time 29533995 ps
CPU time 0.91 seconds
Started Jun 05 04:20:32 PM PDT 24
Finished Jun 05 04:20:34 PM PDT 24
Peak memory 196504 kb
Host smart-b47b082d-f66d-4648-824b-8cd1539695f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1339985143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1339985143
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3977690278
Short name T880
Test name
Test status
Simulation time 129742963 ps
CPU time 1.23 seconds
Started Jun 05 04:20:32 PM PDT 24
Finished Jun 05 04:20:34 PM PDT 24
Peak memory 196788 kb
Host smart-7dec629f-51fc-4d37-b6d4-af9c57f9eebc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977690278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3977690278
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.639094403
Short name T922
Test name
Test status
Simulation time 57459731 ps
CPU time 1.06 seconds
Started Jun 05 04:20:34 PM PDT 24
Finished Jun 05 04:20:36 PM PDT 24
Peak memory 197028 kb
Host smart-68de8b2d-34ee-4436-ba61-43b8ade02262
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=639094403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.639094403
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3436639448
Short name T851
Test name
Test status
Simulation time 218920677 ps
CPU time 1.15 seconds
Started Jun 05 04:20:31 PM PDT 24
Finished Jun 05 04:20:34 PM PDT 24
Peak memory 196068 kb
Host smart-452ad9df-44a6-495d-b108-cafa62fded71
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436639448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3436639448
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1546057406
Short name T936
Test name
Test status
Simulation time 110606031 ps
CPU time 1.6 seconds
Started Jun 05 04:20:35 PM PDT 24
Finished Jun 05 04:20:37 PM PDT 24
Peak memory 196812 kb
Host smart-1b0a4a05-2e9a-481c-9fd6-edab51b79bbd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1546057406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1546057406
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.494748195
Short name T893
Test name
Test status
Simulation time 145246116 ps
CPU time 1.2 seconds
Started Jun 05 04:20:31 PM PDT 24
Finished Jun 05 04:20:32 PM PDT 24
Peak memory 196756 kb
Host smart-a3201169-2364-4dcd-b207-a18c33914c1a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494748195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.494748195
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1462430700
Short name T887
Test name
Test status
Simulation time 98815801 ps
CPU time 0.93 seconds
Started Jun 05 04:20:10 PM PDT 24
Finished Jun 05 04:20:13 PM PDT 24
Peak memory 196772 kb
Host smart-7af8a265-48e6-421c-8278-629cb3abfa67
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1462430700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1462430700
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.59875944
Short name T939
Test name
Test status
Simulation time 146321012 ps
CPU time 1.31 seconds
Started Jun 05 04:20:14 PM PDT 24
Finished Jun 05 04:20:16 PM PDT 24
Peak memory 195944 kb
Host smart-4c607606-c41b-47f0-b9d1-06ff0221b42f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59875944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.59875944
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3065185300
Short name T886
Test name
Test status
Simulation time 45478247 ps
CPU time 0.96 seconds
Started Jun 05 04:20:11 PM PDT 24
Finished Jun 05 04:20:13 PM PDT 24
Peak memory 196544 kb
Host smart-d2f61a2d-7591-47af-88e2-39a13b887b3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3065185300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3065185300
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2778981216
Short name T849
Test name
Test status
Simulation time 151262365 ps
CPU time 1.36 seconds
Started Jun 05 04:20:12 PM PDT 24
Finished Jun 05 04:20:14 PM PDT 24
Peak memory 198204 kb
Host smart-847ff0da-9a16-4371-baef-e6b6fd8195ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778981216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2778981216
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1301483871
Short name T915
Test name
Test status
Simulation time 119829100 ps
CPU time 1.05 seconds
Started Jun 05 04:20:15 PM PDT 24
Finished Jun 05 04:20:17 PM PDT 24
Peak memory 195860 kb
Host smart-ece54b4a-f97d-40f8-b896-b4598b5dffed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1301483871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1301483871
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2087206808
Short name T926
Test name
Test status
Simulation time 295915926 ps
CPU time 1.3 seconds
Started Jun 05 04:20:10 PM PDT 24
Finished Jun 05 04:20:12 PM PDT 24
Peak memory 198264 kb
Host smart-bde3f340-c38c-407c-854a-58b316890165
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087206808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2087206808
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3960271093
Short name T874
Test name
Test status
Simulation time 45520201 ps
CPU time 1.32 seconds
Started Jun 05 04:20:12 PM PDT 24
Finished Jun 05 04:20:14 PM PDT 24
Peak memory 197164 kb
Host smart-56d2736f-4098-441a-8193-826409aaa193
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3960271093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3960271093
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.291288955
Short name T931
Test name
Test status
Simulation time 49511070 ps
CPU time 0.8 seconds
Started Jun 05 04:20:15 PM PDT 24
Finished Jun 05 04:20:16 PM PDT 24
Peak memory 195608 kb
Host smart-36c61098-f336-4a42-b021-87f10082192d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291288955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.291288955
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1431112213
Short name T843
Test name
Test status
Simulation time 276422675 ps
CPU time 0.93 seconds
Started Jun 05 04:20:14 PM PDT 24
Finished Jun 05 04:20:16 PM PDT 24
Peak memory 196776 kb
Host smart-8ac0ea90-cfaf-4fa5-a7a9-70e6b1b941f1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1431112213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1431112213
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3990792064
Short name T908
Test name
Test status
Simulation time 52075283 ps
CPU time 1.04 seconds
Started Jun 05 04:20:10 PM PDT 24
Finished Jun 05 04:20:13 PM PDT 24
Peak memory 196944 kb
Host smart-e30effa1-56c2-4a56-a406-7db45a4e2030
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990792064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3990792064
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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