Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3956986	1			T19	34		T22	1		T23	249
all_pins[1]	3956986	1			T19	34		T22	1		T23	249
all_pins[2]	3956986	1			T19	34		T22	1		T23	249
all_pins[3]	3956986	1			T19	34		T22	1		T23	249
all_pins[4]	3956986	1			T19	34		T22	1		T23	249
all_pins[5]	3956986	1			T19	34		T22	1		T23	249
all_pins[6]	3956986	1			T19	34		T22	1		T23	249
all_pins[7]	3956986	1			T19	34		T22	1		T23	249
all_pins[8]	3956986	1			T19	34		T22	1		T23	249
all_pins[9]	3956986	1			T19	34		T22	1		T23	249
all_pins[10]	3956986	1			T19	34		T22	1		T23	249
all_pins[11]	3956986	1			T19	34		T22	1		T23	249
all_pins[12]	3956986	1			T19	34		T22	1		T23	249
all_pins[13]	3956986	1			T19	34		T22	1		T23	249
all_pins[14]	3956986	1			T19	34		T22	1		T23	249
all_pins[15]	3956986	1			T19	34		T22	1		T23	249
all_pins[16]	3956986	1			T19	34		T22	1		T23	249
all_pins[17]	3956986	1			T19	34		T22	1		T23	249
all_pins[18]	3956986	1			T19	34		T22	1		T23	249
all_pins[19]	3956986	1			T19	34		T22	1		T23	249
all_pins[20]	3956986	1			T19	34		T22	1		T23	249
all_pins[21]	3956986	1			T19	34		T22	1		T23	249
all_pins[22]	3956986	1			T19	34		T22	1		T23	249
all_pins[23]	3956986	1			T19	34		T22	1		T23	249
all_pins[24]	3956986	1			T19	34		T22	1		T23	249
all_pins[25]	3956986	1			T19	34		T22	1		T23	249
all_pins[26]	3956986	1			T19	34		T22	1		T23	249
all_pins[27]	3956986	1			T19	34		T22	1		T23	249
all_pins[28]	3956986	1			T19	34		T22	1		T23	249
all_pins[29]	3956986	1			T19	34		T22	1		T23	249
all_pins[30]	3956986	1			T19	34		T22	1		T23	249
all_pins[31]	3956986	1			T19	34		T22	1		T23	249

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	78645591	1			T19	943		T22	32		T23	4902
values[0x1]	47977961	1			T19	145		T23	3066		T1	236537
transitions[0x0=>0x1]	28736462	1			T19	100		T23	1840		T1	142363
transitions[0x1=>0x0]	28736312	1			T19	100		T23	1839		T1	142363

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2459415	1			T19	33		T22	1		T23	182
all_pins[0]	values[0x1]	1497571	1			T19	1		T23	67		T1	7309
all_pins[0]	transitions[0x0=>0x1]	928833	1			T19	1		T23	39		T1	4454
all_pins[0]	transitions[0x1=>0x0]	929471	1			T19	2		T23	78		T1	4696
all_pins[1]	values[0x0]	2465909	1			T19	27		T22	1		T23	165
all_pins[1]	values[0x1]	1491077	1			T19	7		T23	84		T1	7448
all_pins[1]	transitions[0x0=>0x1]	892360	1			T19	7		T23	58		T1	4306
all_pins[1]	transitions[0x1=>0x0]	898854	1			T19	1		T23	41		T1	4167
all_pins[2]	values[0x0]	2455103	1			T19	31		T22	1		T23	181
all_pins[2]	values[0x1]	1501883	1			T19	3		T23	68		T1	7564
all_pins[2]	transitions[0x0=>0x1]	904200	1			T19	3		T23	54		T1	4400
all_pins[2]	transitions[0x1=>0x0]	893394	1			T19	7		T23	70		T1	4284
all_pins[3]	values[0x0]	2455480	1			T19	27		T22	1		T23	155
all_pins[3]	values[0x1]	1501506	1			T19	7		T23	94		T1	7443
all_pins[3]	transitions[0x0=>0x1]	897866	1			T19	7		T23	67		T1	4482
all_pins[3]	transitions[0x1=>0x0]	898243	1			T19	3		T23	41		T1	4603
all_pins[4]	values[0x0]	2454345	1			T19	25		T22	1		T23	155
all_pins[4]	values[0x1]	1502641	1			T19	9		T23	94		T1	7087
all_pins[4]	transitions[0x0=>0x1]	899728	1			T19	3		T23	47		T1	4142
all_pins[4]	transitions[0x1=>0x0]	898593	1			T19	1		T23	47		T1	4498
all_pins[5]	values[0x0]	2460474	1			T19	26		T22	1		T23	163
all_pins[5]	values[0x1]	1496512	1			T19	8		T23	86		T1	7214
all_pins[5]	transitions[0x0=>0x1]	893576	1			T23	46		T1	4523		T11	15
all_pins[5]	transitions[0x1=>0x0]	899705	1			T19	1		T23	54		T1	4396
all_pins[6]	values[0x0]	2462213	1			T19	22		T22	1		T23	152
all_pins[6]	values[0x1]	1494773	1			T19	12		T23	97		T1	7019
all_pins[6]	transitions[0x0=>0x1]	897707	1			T19	6		T23	60		T1	4290
all_pins[6]	transitions[0x1=>0x0]	899446	1			T19	2		T23	49		T1	4485
all_pins[7]	values[0x0]	2456632	1			T19	28		T22	1		T23	138
all_pins[7]	values[0x1]	1500354	1			T19	6		T23	111		T1	7910
all_pins[7]	transitions[0x0=>0x1]	898030	1			T19	2		T23	63		T1	4958
all_pins[7]	transitions[0x1=>0x0]	892449	1			T19	8		T23	49		T1	4067
all_pins[8]	values[0x0]	2454109	1			T19	34		T22	1		T23	153
all_pins[8]	values[0x1]	1502877	1			T23	96		T1	7730		T11	26
all_pins[8]	transitions[0x0=>0x1]	899790	1			T23	65		T1	4467		T11	10
all_pins[8]	transitions[0x1=>0x0]	897267	1			T19	6		T23	80		T1	4647
all_pins[9]	values[0x0]	2454064	1			T19	26		T22	1		T23	147
all_pins[9]	values[0x1]	1502922	1			T19	8		T23	102		T1	7050
all_pins[9]	transitions[0x0=>0x1]	895785	1			T19	8		T23	71		T1	4201
all_pins[9]	transitions[0x1=>0x0]	895740	1			T23	65		T1	4881		T11	12
all_pins[10]	values[0x0]	2457062	1			T19	29		T22	1		T23	152
all_pins[10]	values[0x1]	1499924	1			T19	5		T23	97		T1	7749
all_pins[10]	transitions[0x0=>0x1]	896180	1			T19	1		T23	54		T1	4741
all_pins[10]	transitions[0x1=>0x0]	899178	1			T19	4		T23	59		T1	4042
all_pins[11]	values[0x0]	2452413	1			T19	32		T22	1		T23	170
all_pins[11]	values[0x1]	1504573	1			T19	2		T23	79		T1	7548
all_pins[11]	transitions[0x0=>0x1]	897972	1			T19	2		T23	34		T1	4429
all_pins[11]	transitions[0x1=>0x0]	893323	1			T19	5		T23	52		T1	4630
all_pins[12]	values[0x0]	2459019	1			T19	31		T22	1		T23	153
all_pins[12]	values[0x1]	1497967	1			T19	3		T23	96		T1	7104
all_pins[12]	transitions[0x0=>0x1]	894530	1			T19	3		T23	56		T1	4437
all_pins[12]	transitions[0x1=>0x0]	901136	1			T19	2		T23	39		T1	4881
all_pins[13]	values[0x0]	2457137	1			T19	31		T22	1		T23	130
all_pins[13]	values[0x1]	1499849	1			T19	3		T23	119		T1	7364
all_pins[13]	transitions[0x0=>0x1]	895469	1			T19	2		T23	68		T1	4556
all_pins[13]	transitions[0x1=>0x0]	893587	1			T19	2		T23	45		T1	4296
all_pins[14]	values[0x0]	2462648	1			T19	31		T22	1		T23	144
all_pins[14]	values[0x1]	1494338	1			T19	3		T23	105		T1	7270
all_pins[14]	transitions[0x0=>0x1]	893850	1			T23	47		T1	4460		T11	15
all_pins[14]	transitions[0x1=>0x0]	899361	1			T23	61		T1	4554		T11	7
all_pins[15]	values[0x0]	2456587	1			T19	25		T22	1		T23	140
all_pins[15]	values[0x1]	1500399	1			T19	9		T23	109		T1	7391
all_pins[15]	transitions[0x0=>0x1]	900320	1			T19	7		T23	63		T1	4495
all_pins[15]	transitions[0x1=>0x0]	894259	1			T19	1		T23	59		T1	4374
all_pins[16]	values[0x0]	2454210	1			T19	32		T22	1		T23	176
all_pins[16]	values[0x1]	1502776	1			T19	2		T23	73		T1	7553
all_pins[16]	transitions[0x0=>0x1]	897097	1			T19	1		T23	35		T1	4320
all_pins[16]	transitions[0x1=>0x0]	894720	1			T19	8		T23	71		T1	4158
all_pins[17]	values[0x0]	2466001	1			T19	26		T22	1		T23	166
all_pins[17]	values[0x1]	1490985	1			T19	8		T23	83		T1	7491
all_pins[17]	transitions[0x0=>0x1]	889781	1			T19	7		T23	72		T1	4560
all_pins[17]	transitions[0x1=>0x0]	901572	1			T19	1		T23	62		T1	4622
all_pins[18]	values[0x0]	2460628	1			T19	31		T22	1		T23	144
all_pins[18]	values[0x1]	1496358	1			T19	3		T23	105		T1	7458
all_pins[18]	transitions[0x0=>0x1]	900673	1			T19	2		T23	82		T1	4400
all_pins[18]	transitions[0x1=>0x0]	895300	1			T19	7		T23	60		T1	4433
all_pins[19]	values[0x0]	2457389	1			T19	29		T22	1		T23	144
all_pins[19]	values[0x1]	1499597	1			T19	5		T23	105		T1	7424
all_pins[19]	transitions[0x0=>0x1]	897873	1			T19	5		T23	55		T1	4386
all_pins[19]	transitions[0x1=>0x0]	894634	1			T19	3		T23	55		T1	4420
all_pins[20]	values[0x0]	2456307	1			T19	31		T22	1		T23	135
all_pins[20]	values[0x1]	1500679	1			T19	3		T23	114		T1	7459
all_pins[20]	transitions[0x0=>0x1]	899240	1			T19	2		T23	65		T1	4531
all_pins[20]	transitions[0x1=>0x0]	898158	1			T19	4		T23	56		T1	4496
all_pins[21]	values[0x0]	2459470	1			T19	33		T22	1		T23	131
all_pins[21]	values[0x1]	1497516	1			T19	1		T23	118		T1	6957
all_pins[21]	transitions[0x0=>0x1]	897774	1			T19	1		T23	57		T1	4145
all_pins[21]	transitions[0x1=>0x0]	900937	1			T19	3		T23	53		T1	4647
all_pins[22]	values[0x0]	2459705	1			T19	31		T22	1		T23	136
all_pins[22]	values[0x1]	1497281	1			T19	3		T23	113		T1	7443
all_pins[22]	transitions[0x0=>0x1]	894534	1			T19	3		T23	51		T1	4693
all_pins[22]	transitions[0x1=>0x0]	894769	1			T19	1		T23	56		T1	4207
all_pins[23]	values[0x0]	2457404	1			T19	33		T22	1		T23	159
all_pins[23]	values[0x1]	1499582	1			T19	1		T23	90		T1	7436
all_pins[23]	transitions[0x0=>0x1]	895648	1			T19	1		T23	38		T1	4459
all_pins[23]	transitions[0x1=>0x0]	893347	1			T19	3		T23	61		T1	4466
all_pins[24]	values[0x0]	2456312	1			T19	32		T22	1		T23	167
all_pins[24]	values[0x1]	1500674	1			T19	2		T23	82		T1	7520
all_pins[24]	transitions[0x0=>0x1]	898109	1			T19	2		T23	58		T1	4520
all_pins[24]	transitions[0x1=>0x0]	897017	1			T19	1		T23	66		T1	4436
all_pins[25]	values[0x0]	2465965	1			T19	33		T22	1		T23	160
all_pins[25]	values[0x1]	1491021	1			T19	1		T23	89		T1	7355
all_pins[25]	transitions[0x0=>0x1]	890277	1			T23	70		T1	4250		T11	13
all_pins[25]	transitions[0x1=>0x0]	899930	1			T19	1		T23	63		T1	4415
all_pins[26]	values[0x0]	2455664	1			T19	28		T22	1		T23	155
all_pins[26]	values[0x1]	1501322	1			T19	6		T23	94		T1	7155
all_pins[26]	transitions[0x0=>0x1]	901058	1			T19	6		T23	53		T1	4354
all_pins[26]	transitions[0x1=>0x0]	890757	1			T19	1		T23	48		T1	4554
all_pins[27]	values[0x0]	2454100	1			T19	25		T22	1		T23	174
all_pins[27]	values[0x1]	1502886	1			T19	9		T23	75		T1	7405
all_pins[27]	transitions[0x0=>0x1]	899001	1			T19	5		T23	49		T1	4545
all_pins[27]	transitions[0x1=>0x0]	897437	1			T19	2		T23	68		T1	4295
all_pins[28]	values[0x0]	2447395	1			T19	34		T22	1		T23	143
all_pins[28]	values[0x1]	1509591	1			T23	106		T1	7283		T11	23
all_pins[28]	transitions[0x0=>0x1]	903751	1			T23	76		T1	4353		T11	10
all_pins[28]	transitions[0x1=>0x0]	897046	1			T19	9		T23	45		T1	4475
all_pins[29]	values[0x0]	2455940	1			T19	34		T22	1		T23	153
all_pins[29]	values[0x1]	1501046	1			T23	96		T1	7220		T11	41
all_pins[29]	transitions[0x0=>0x1]	893366	1			T23	56		T1	4373		T11	31
all_pins[29]	transitions[0x1=>0x0]	901911	1			T23	66		T1	4436		T11	13
all_pins[30]	values[0x0]	2457864	1			T19	21		T22	1		T23	137
all_pins[30]	values[0x1]	1499122	1			T19	13		T23	112		T1	7627
all_pins[30]	transitions[0x0=>0x1]	895449	1			T19	13		T23	69		T1	4623
all_pins[30]	transitions[0x1=>0x0]	897373	1			T23	53		T1	4216		T11	24
all_pins[31]	values[0x0]	2458627	1			T19	32		T22	1		T23	142
all_pins[31]	values[0x1]	1498359	1			T19	2		T23	107		T1	7551
all_pins[31]	transitions[0x0=>0x1]	896635	1			T23	62		T1	4510		T11	12
all_pins[31]	transitions[0x1=>0x0]	897398	1			T19	11		T23	67		T1	4586