Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[1]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[2]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[3]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[4]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[5]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[6]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[7]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[8]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[9]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[10]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[11]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[12]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[13]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[14]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[15]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[16]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[17]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[18]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[19]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[20]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[21]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[22]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[23]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[24]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[25]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[26]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[27]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[28]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[29]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[30]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[31]	13363292	1			T19	99		T22	393		T23	173

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250419576

1

T19

1570

T22

10158

T23

2720

auto[1]

177205768

1

T19

1598

T22

2418

T23

2816

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343828073

1

T19

2873

T22

9447

T23

5536

auto[1]

83797271

1

T19

295

T22

3129

T24

671

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319356289

1

T19

2428

T22

6389

T23

5536

auto[1]

108269055

1

T19

740

T22

6187

T24

3722

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4906253	1			T19	15		T22	153		T23	91
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3744978	1			T19	60		T22	18		T23	82
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1322520	1			T22	39		T24	6		T25	25
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1598931	1			T19	10		T22	155		T24	94
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	482410	1			T19	12		T22	8		T24	29
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1308200	1			T19	2		T22	20		T24	28
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4914121	1			T19	56		T22	132		T23	99
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3755235	1			T19	27		T22	14		T23	74
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1319874	1			T22	42		T24	34		T25	32
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1596609	1			T19	4		T22	103		T25	71
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	479078	1			T19	2		T22	20		T25	15
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1298375	1			T19	10		T22	82		T25	40
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4915283	1			T19	18		T22	128		T23	75
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3749294	1			T19	42		T22	13		T23	98
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1320111	1			T19	13		T22	36		T24	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1596171	1			T19	5		T22	148		T24	76
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	478882	1			T19	8		T22	11		T24	21
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1303551	1			T19	13		T22	57		T24	5
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4899363	1			T19	33		T22	133		T23	72
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3759154	1			T19	51		T22	7		T23	101
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1317836	1			T22	69		T24	6		T25	28
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1601746	1			T22	142		T24	117		T25	64
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	480479	1			T19	8		T22	13		T24	34
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1304714	1			T19	7		T22	29		T24	22
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4903473	1			T19	31		T22	113		T23	104
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3755732	1			T19	22		T22	8		T23	69
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1324798	1			T19	5		T22	50		T24	15
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1593105	1			T19	15		T22	155		T24	50
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	478839	1			T19	10		T22	18		T24	14
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1307345	1			T19	16		T22	49		T24	3
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4904573	1			T19	40		T22	159		T23	94
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3754109	1			T19	29		T22	15		T23	79
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1312762	1			T22	33		T24	13		T25	31
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1601185	1			T19	12		T22	124		T24	95
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	482941	1			T19	13		T22	8		T24	28
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1307722	1			T19	5		T22	54		T24	8
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4899773	1			T19	51		T22	124		T23	81
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3756612	1			T19	23		T22	16		T23	92
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1321802	1			T19	8		T22	61		T25	25
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1599434	1			T19	12		T22	142		T24	114
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	480283	1			T19	3		T22	17		T24	34
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1305388	1			T19	2		T22	33		T24	4
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4916841	1			T19	22		T22	152		T23	83
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3749266	1			T19	48		T22	19		T23	90
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1316237	1			T19	4		T22	90		T24	29
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1601505	1			T19	10		T22	90		T24	44
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	476333	1			T19	10		T22	8		T24	12
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1303110	1			T19	5		T22	34		T24	2
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4908153	1			T19	38		T22	85		T23	74
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3748769	1			T19	28		T22	5		T23	99
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1316518	1			T19	4		T22	48		T24	12
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1601744	1			T19	5		T22	172		T24	65
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	479699	1			T19	7		T22	20		T24	21
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1308409	1			T19	17		T22	63		T24	10
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4918093	1			T19	32		T22	67		T23	84
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3742752	1			T19	26		T22	3		T23	89
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1320484	1			T19	4		T22	49		T24	12
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1598054	1			T19	20		T22	179		T24	59
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	479482	1			T19	9		T22	27		T24	16
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1304427	1			T19	8		T22	68		T24	8
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4912961	1			T19	32		T22	155		T23	79
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3749698	1			T19	45		T22	29		T23	94
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1312586	1			T22	80		T24	10		T25	28
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1600378	1			T19	18		T22	83		T24	65
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	480551	1			T19	1		T22	8		T24	14
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1307118	1			T19	3		T22	38		T24	11
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4902812	1			T19	45		T22	114		T23	97
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3755230	1			T19	17		T22	14		T23	76
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1317185	1			T22	66		T24	18		T25	29
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1599075	1			T19	11		T22	122		T24	88
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	481142	1			T19	17		T22	9		T24	22
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1307848	1			T19	9		T22	68		T24	10
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4909448	1			T19	42		T22	179		T23	84
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3752331	1			T19	34		T22	13		T23	89
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1314298	1			T22	60		T24	25		T25	20
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1602686	1			T19	9		T22	110		T24	42
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	481391	1			T19	6		T22	13		T24	17
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1303138	1			T19	8		T22	18		T24	10
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4903944	1			T19	29		T22	89		T23	79
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3759251	1			T19	46		T22	15		T23	94
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1318264	1			T22	46		T24	4		T25	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1596813	1			T19	8		T22	166		T24	82
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	479775	1			T19	2		T22	17		T24	20
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1305245	1			T19	14		T22	60		T24	6
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4896949	1			T19	46		T22	131		T23	68
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3762998	1			T19	28		T22	10		T23	105
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1314678	1			T19	4		T22	44		T24	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1600900	1			T19	15		T22	147		T24	112
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	482139	1			T19	5		T22	15		T24	18
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1305628	1			T19	1		T22	46		T24	16
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4902788	1			T19	23		T22	163		T23	76
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3753973	1			T19	47		T22	8		T23	97
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1318426	1			T22	27		T24	30		T25	23
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1602615	1			T19	14		T22	108		T24	58
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	476387	1			T19	10		T22	16		T24	21
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1309103	1			T19	5		T22	71		T24	4
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4907412	1			T19	57		T22	187		T23	80
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3757192	1			T19	19		T22	15		T23	93
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1312693	1			T19	6		T22	37		T24	8
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1600344	1			T19	15		T22	114		T24	121
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	481860	1			T19	2		T22	7		T24	25
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1303791	1			T22	33		T24	16		T25	47
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4908388	1			T19	42		T22	141		T23	85
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3760027	1			T19	32		T22	18		T23	88
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1309585	1			T19	10		T22	46		T25	18
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1603138	1			T19	10		T22	148		T24	182
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	479669	1			T19	5		T22	9		T24	34
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1302485	1			T22	31		T24	20		T25	30
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4916718	1			T19	39		T22	126		T23	97
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3756896	1			T19	33		T22	15		T23	76
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1313832	1			T22	57		T24	12		T25	27
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1596995	1			T19	1		T22	142		T24	45
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	479439	1			T19	5		T22	21		T24	5
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1299412	1			T19	21		T22	32		T24	2
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4921529	1			T19	47		T22	189		T23	82
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3750957	1			T19	28		T22	23		T23	91
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1315574	1			T19	10		T22	47		T24	12
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1598265	1			T19	10		T22	89		T24	42
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	479666	1			T19	1		T22	9		T24	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1297301	1			T19	3		T22	36		T24	2
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4921968	1			T19	19		T22	148		T23	88
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3746248	1			T19	47		T22	20		T23	85
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1313840	1			T22	50		T24	12		T25	18
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1598181	1			T19	11		T22	124		T24	114
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	481514	1			T19	10		T22	12		T24	21
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1301541	1			T19	12		T22	39		T24	8
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4904479	1			T19	50		T22	146		T23	75
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3757446	1			T19	39		T22	16		T23	98
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1316220	1			T22	50		T25	13		T1	7612
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1601540	1			T19	2		T22	116		T24	130
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	480112	1			T19	6		T22	8		T24	29
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1303495	1			T19	2		T22	57		T24	10
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4915778	1			T19	28		T22	135		T23	94
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3754913	1			T19	50		T22	16		T23	79
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1310841	1			T22	65		T24	12		T25	32
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1600963	1			T19	4		T22	128		T24	141
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	481584	1			T19	6		T22	11		T24	25
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1299213	1			T19	11		T22	38		T24	8
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4907351	1			T19	34		T22	129		T23	85
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3761082	1			T19	38		T22	19		T23	88
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1308899	1			T19	1		T22	30		T24	10
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1604000	1			T19	15		T22	139		T24	112
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	480765	1			T19	10		T22	12		T24	31
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1301195	1			T19	1		T22	64		T24	15
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4920416	1			T19	30		T22	128		T23	93
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3746839	1			T19	51		T22	11		T23	80
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1307336	1			T22	43		T24	14		T25	18
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1607455	1			T22	163		T24	106		T25	89
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	479967	1			T19	7		T22	17		T24	19
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1301279	1			T19	11		T22	31		T24	12
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4908175	1			T19	26		T22	98		T23	89
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3760012	1			T19	47		T22	12		T23	84
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1313711	1			T22	69		T24	15		T25	26
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1600113	1			T19	24		T22	132		T24	97
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	482175	1			T19	2		T22	16		T24	16
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1299106	1			T22	66		T24	14		T25	22
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4921246	1			T19	28		T22	146		T23	91
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3753534	1			T19	53		T22	8		T23	82
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1312152	1			T19	2		T22	48		T25	30
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1595732	1			T19	11		T22	140		T24	128
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	480652	1			T19	3		T22	16		T24	19
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1299976	1			T19	2		T22	35		T24	12
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4911658	1			T19	43		T22	166		T23	87
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3760969	1			T19	26		T22	20		T23	86
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1316396	1			T19	4		T22	43		T24	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1596127	1			T19	26		T22	95		T24	51
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	480617	1			T22	11		T24	11		T25	7
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1297525	1			T22	58		T24	11		T25	29
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4912789	1			T19	43		T22	89		T23	85
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3754954	1			T19	22		T22	6		T23	88
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1309806	1			T19	6		T22	29		T24	6
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1601365	1			T19	15		T22	185		T24	61
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	479199	1			T19	11		T22	16		T24	10
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1305179	1			T19	2		T22	68		T24	2
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4910936	1			T19	23		T22	166		T23	81
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3756671	1			T19	55		T22	16		T23	92
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1316347	1			T19	9		T22	46		T24	12
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1600882	1			T19	1		T22	111		T24	106
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	477136	1			T19	6		T22	17		T24	24
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1301320	1			T19	5		T22	37		T24	10
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4908624	1			T19	43		T22	101		T23	81
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3759958	1			T19	36		T22	20		T23	92
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1312119	1			T19	2		T22	25		T24	14
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1603255	1			T19	12		T22	167		T24	81
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	480416	1			T19	4		T22	8		T24	16
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1298920	1			T19	2		T22	72		T24	4
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4913797	1			T19	41		T22	156		T23	87
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3749391	1			T19	41		T22	17		T23	86
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1315996	1			T22	77		T24	11		T25	35
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1600452	1			T19	7		T22	89		T24	107
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	481170	1			T19	4		T22	14		T24	29
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1302486	1			T19	6		T22	40		T24	2

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal