Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[1]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[2]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[3]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[4]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[5]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[6]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[7]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[8]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[9]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[10]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[11]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[12]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[13]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[14]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[15]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[16]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[17]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[18]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[19]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[20]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[21]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[22]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[23]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[24]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[25]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[26]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[27]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[28]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[29]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[30]	13363292	1			T19	99		T22	393		T23	173
bins_for_gpio_bits[31]	13363292	1			T19	99		T22	393		T23	173

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250419576

1

T19

1570

T22

10158

T23

2720

auto[1]

177205768

1

T19

1598

T22

2418

T23

2816

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250412624

1

T19

1570

T22

10152

T23

2720

auto[1]

177212720

1

T19

1598

T22

2424

T23

2816

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7591736	1			T19	25		T22	341		T23	91
bins_for_gpio_bits[0]	auto[0]	auto[1]	235777	1			T22	6		T24	7		T25	10
bins_for_gpio_bits[0]	auto[1]	auto[0]	235968	1			T22	6		T24	7		T25	10
bins_for_gpio_bits[0]	auto[1]	auto[1]	5299811	1			T19	74		T22	40		T23	82
bins_for_gpio_bits[1]	auto[0]	auto[0]	7594980	1			T19	60		T22	263		T23	99
bins_for_gpio_bits[1]	auto[0]	auto[1]	235439	1			T22	14		T25	6		T1	1458
bins_for_gpio_bits[1]	auto[1]	auto[0]	235624	1			T22	14		T25	6		T1	1455
bins_for_gpio_bits[1]	auto[1]	auto[1]	5297249	1			T19	39		T22	102		T23	74
bins_for_gpio_bits[2]	auto[0]	auto[0]	7596053	1			T19	36		T22	304		T23	75
bins_for_gpio_bits[2]	auto[0]	auto[1]	235249	1			T22	7		T24	1		T25	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	235512	1			T22	8		T24	1		T25	8
bins_for_gpio_bits[2]	auto[1]	auto[1]	5296478	1			T19	63		T22	74		T23	98
bins_for_gpio_bits[3]	auto[0]	auto[0]	7583030	1			T19	33		T22	336		T23	72
bins_for_gpio_bits[3]	auto[0]	auto[1]	235702	1			T22	8		T24	6		T25	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	235915	1			T22	8		T24	6		T25	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	5308645	1			T19	66		T22	41		T23	101
bins_for_gpio_bits[4]	auto[0]	auto[0]	7584798	1			T19	51		T22	307		T23	104
bins_for_gpio_bits[4]	auto[0]	auto[1]	236375	1			T22	11		T24	1		T25	9
bins_for_gpio_bits[4]	auto[1]	auto[0]	236578	1			T22	11		T24	1		T25	9
bins_for_gpio_bits[4]	auto[1]	auto[1]	5305541	1			T19	48		T22	64		T23	69
bins_for_gpio_bits[5]	auto[0]	auto[0]	7582859	1			T19	52		T22	306		T23	94
bins_for_gpio_bits[5]	auto[0]	auto[1]	235484	1			T22	9		T24	3		T25	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	235661	1			T22	10		T24	3		T25	8
bins_for_gpio_bits[5]	auto[1]	auto[1]	5309288	1			T19	47		T22	68		T23	79
bins_for_gpio_bits[6]	auto[0]	auto[0]	7584598	1			T19	71		T22	319		T23	81
bins_for_gpio_bits[6]	auto[0]	auto[1]	236234	1			T22	8		T24	2		T25	6
bins_for_gpio_bits[6]	auto[1]	auto[0]	236411	1			T22	8		T24	2		T25	6
bins_for_gpio_bits[6]	auto[1]	auto[1]	5306049	1			T19	28		T22	58		T23	92
bins_for_gpio_bits[7]	auto[0]	auto[0]	7599217	1			T19	36		T22	325		T23	83
bins_for_gpio_bits[7]	auto[0]	auto[1]	235143	1			T22	7		T24	1		T25	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	235366	1			T22	7		T24	1		T25	4
bins_for_gpio_bits[7]	auto[1]	auto[1]	5293566	1			T19	63		T22	54		T23	90
bins_for_gpio_bits[8]	auto[0]	auto[0]	7590094	1			T19	47		T22	295		T23	74
bins_for_gpio_bits[8]	auto[0]	auto[1]	236131	1			T22	10		T24	4		T25	5
bins_for_gpio_bits[8]	auto[1]	auto[0]	236321	1			T22	10		T24	4		T25	5
bins_for_gpio_bits[8]	auto[1]	auto[1]	5300746	1			T19	52		T22	78		T23	99
bins_for_gpio_bits[9]	auto[0]	auto[0]	7601148	1			T19	56		T22	281		T23	84
bins_for_gpio_bits[9]	auto[0]	auto[1]	235219	1			T22	14		T24	2		T25	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	235483	1			T22	14		T24	2		T25	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	5291442	1			T19	43		T22	84		T23	89
bins_for_gpio_bits[10]	auto[0]	auto[0]	7590067	1			T19	50		T22	312		T23	79
bins_for_gpio_bits[10]	auto[0]	auto[1]	235671	1			T22	6		T24	3		T25	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	235858	1			T22	6		T24	3		T25	4
bins_for_gpio_bits[10]	auto[1]	auto[1]	5301696	1			T19	49		T22	69		T23	94
bins_for_gpio_bits[11]	auto[0]	auto[0]	7583149	1			T19	56		T22	290		T23	97
bins_for_gpio_bits[11]	auto[0]	auto[1]	235702	1			T22	12		T24	4		T25	3
bins_for_gpio_bits[11]	auto[1]	auto[0]	235923	1			T22	12		T24	4		T25	3
bins_for_gpio_bits[11]	auto[1]	auto[1]	5308518	1			T19	43		T22	79		T23	76
bins_for_gpio_bits[12]	auto[0]	auto[0]	7590593	1			T19	51		T22	345		T23	84
bins_for_gpio_bits[12]	auto[0]	auto[1]	235628	1			T22	4		T24	3		T25	7
bins_for_gpio_bits[12]	auto[1]	auto[0]	235839	1			T22	4		T24	3		T25	7
bins_for_gpio_bits[12]	auto[1]	auto[1]	5301232	1			T19	48		T22	40		T23	89
bins_for_gpio_bits[13]	auto[0]	auto[0]	7582963	1			T19	37		T22	292		T23	79
bins_for_gpio_bits[13]	auto[0]	auto[1]	235861	1			T22	8		T24	2		T25	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	236058	1			T22	9		T24	2		T25	4
bins_for_gpio_bits[13]	auto[1]	auto[1]	5308410	1			T19	62		T22	84		T23	94
bins_for_gpio_bits[14]	auto[0]	auto[0]	7576608	1			T19	65		T22	313		T23	68
bins_for_gpio_bits[14]	auto[0]	auto[1]	235711	1			T22	9		T24	3		T25	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	235919	1			T22	9		T24	3		T25	4
bins_for_gpio_bits[14]	auto[1]	auto[1]	5315054	1			T19	34		T22	62		T23	105
bins_for_gpio_bits[15]	auto[0]	auto[0]	7587421	1			T19	37		T22	287		T23	76
bins_for_gpio_bits[15]	auto[0]	auto[1]	236182	1			T22	11		T24	2		T25	6
bins_for_gpio_bits[15]	auto[1]	auto[0]	236408	1			T22	11		T24	2		T25	6
bins_for_gpio_bits[15]	auto[1]	auto[1]	5303281	1			T19	62		T22	84		T23	97
bins_for_gpio_bits[16]	auto[0]	auto[0]	7584494	1			T19	78		T22	331		T23	80
bins_for_gpio_bits[16]	auto[0]	auto[1]	235720	1			T22	7		T24	5		T25	8
bins_for_gpio_bits[16]	auto[1]	auto[0]	235955	1			T22	7		T24	5		T25	8
bins_for_gpio_bits[16]	auto[1]	auto[1]	5307123	1			T19	21		T22	48		T23	93
bins_for_gpio_bits[17]	auto[0]	auto[0]	7585104	1			T19	62		T22	328		T23	85
bins_for_gpio_bits[17]	auto[0]	auto[1]	235790	1			T22	7		T24	4		T25	5
bins_for_gpio_bits[17]	auto[1]	auto[0]	236007	1			T22	7		T24	4		T25	5
bins_for_gpio_bits[17]	auto[1]	auto[1]	5306391	1			T19	37		T22	51		T23	88
bins_for_gpio_bits[18]	auto[0]	auto[0]	7591782	1			T19	40		T22	317		T23	97
bins_for_gpio_bits[18]	auto[0]	auto[1]	235513	1			T22	8		T24	1		T25	5
bins_for_gpio_bits[18]	auto[1]	auto[0]	235763	1			T22	8		T24	1		T25	5
bins_for_gpio_bits[18]	auto[1]	auto[1]	5300234	1			T19	59		T22	60		T23	76
bins_for_gpio_bits[19]	auto[0]	auto[0]	7599212	1			T19	67		T22	319		T23	82
bins_for_gpio_bits[19]	auto[0]	auto[1]	235930	1			T22	6		T24	1		T25	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	236156	1			T22	6		T24	1		T25	3
bins_for_gpio_bits[19]	auto[1]	auto[1]	5291994	1			T19	32		T22	62		T23	91
bins_for_gpio_bits[20]	auto[0]	auto[0]	7598862	1			T19	30		T22	316		T23	88
bins_for_gpio_bits[20]	auto[0]	auto[1]	234937	1			T22	6		T24	3		T25	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	235127	1			T22	6		T24	3		T25	5
bins_for_gpio_bits[20]	auto[1]	auto[1]	5294366	1			T19	69		T22	65		T23	85
bins_for_gpio_bits[21]	auto[0]	auto[0]	7586309	1			T19	52		T22	304		T23	75
bins_for_gpio_bits[21]	auto[0]	auto[1]	235708	1			T22	8		T24	4		T25	6
bins_for_gpio_bits[21]	auto[1]	auto[0]	235930	1			T22	8		T24	4		T25	6
bins_for_gpio_bits[21]	auto[1]	auto[1]	5305345	1			T19	47		T22	73		T23	98
bins_for_gpio_bits[22]	auto[0]	auto[0]	7592123	1			T19	32		T22	322		T23	94
bins_for_gpio_bits[22]	auto[0]	auto[1]	235237	1			T22	6		T24	3		T25	1
bins_for_gpio_bits[22]	auto[1]	auto[0]	235459	1			T22	6		T24	3		T25	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	5300473	1			T19	67		T22	59		T23	79
bins_for_gpio_bits[23]	auto[0]	auto[0]	7584411	1			T19	50		T22	287		T23	85
bins_for_gpio_bits[23]	auto[0]	auto[1]	235610	1			T22	11		T24	4		T25	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	235839	1			T22	11		T24	4		T25	4
bins_for_gpio_bits[23]	auto[1]	auto[1]	5307432	1			T19	49		T22	84		T23	88
bins_for_gpio_bits[24]	auto[0]	auto[0]	7599118	1			T19	30		T22	327		T23	93
bins_for_gpio_bits[24]	auto[0]	auto[1]	235876	1			T22	6		T24	4		T25	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	236089	1			T22	7		T24	4		T25	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	5292209	1			T19	69		T22	53		T23	80
bins_for_gpio_bits[25]	auto[0]	auto[0]	7585915	1			T19	50		T22	288		T23	89
bins_for_gpio_bits[25]	auto[0]	auto[1]	235863	1			T22	11		T24	5		T25	3
bins_for_gpio_bits[25]	auto[1]	auto[0]	236084	1			T22	11		T24	5		T25	3
bins_for_gpio_bits[25]	auto[1]	auto[1]	5305430	1			T19	49		T22	83		T23	84
bins_for_gpio_bits[26]	auto[0]	auto[0]	7593352	1			T19	41		T22	327		T23	91
bins_for_gpio_bits[26]	auto[0]	auto[1]	235577	1			T22	6		T24	4		T25	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	235778	1			T22	7		T24	4		T25	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	5298585	1			T19	58		T22	53		T23	82
bins_for_gpio_bits[27]	auto[0]	auto[0]	7588609	1			T19	73		T22	296		T23	87
bins_for_gpio_bits[27]	auto[0]	auto[1]	235336	1			T22	8		T24	3		T25	7
bins_for_gpio_bits[27]	auto[1]	auto[0]	235572	1			T22	8		T24	3		T25	7
bins_for_gpio_bits[27]	auto[1]	auto[1]	5303775	1			T19	26		T22	81		T23	86
bins_for_gpio_bits[28]	auto[0]	auto[0]	7587698	1			T19	64		T22	289		T23	85
bins_for_gpio_bits[28]	auto[0]	auto[1]	236026	1			T22	13		T24	1		T25	6
bins_for_gpio_bits[28]	auto[1]	auto[0]	236262	1			T22	14		T24	1		T25	6
bins_for_gpio_bits[28]	auto[1]	auto[1]	5303306	1			T19	35		T22	77		T23	88
bins_for_gpio_bits[29]	auto[0]	auto[0]	7592379	1			T19	33		T22	317		T23	81
bins_for_gpio_bits[29]	auto[0]	auto[1]	235563	1			T22	6		T24	2		T25	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	235786	1			T22	6		T24	2		T25	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	5299564	1			T19	66		T22	64		T23	92
bins_for_gpio_bits[30]	auto[0]	auto[0]	7588030	1			T19	57		T22	279		T23	81
bins_for_gpio_bits[30]	auto[0]	auto[1]	235713	1			T22	14		T24	2		T25	4
bins_for_gpio_bits[30]	auto[1]	auto[0]	235968	1			T22	14		T24	2		T25	4
bins_for_gpio_bits[30]	auto[1]	auto[1]	5303581	1			T19	42		T22	86		T23	92
bins_for_gpio_bits[31]	auto[0]	auto[0]	7594015	1			T19	48		T22	316		T23	87
bins_for_gpio_bits[31]	auto[0]	auto[1]	235990	1			T22	6		T24	1		T25	2
bins_for_gpio_bits[31]	auto[1]	auto[0]	236230	1			T22	6		T24	1		T25	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	5297057	1			T19	51		T22	65		T23	86