Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7909454 |
1 |
|
|
T19 |
45 |
|
T22 |
203 |
|
T23 |
211 |
| auto[1] |
5605667 |
1 |
|
|
T19 |
15 |
|
T23 |
172 |
|
T1 |
28384 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12796933 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
368 |
| auto[1] |
718188 |
1 |
|
|
T19 |
1 |
|
T23 |
15 |
|
T1 |
3325 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7907111 |
1 |
|
|
T19 |
53 |
|
T22 |
203 |
|
T23 |
198 |
| auto[1] |
5608010 |
1 |
|
|
T19 |
7 |
|
T23 |
185 |
|
T1 |
26394 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2463365 |
1 |
|
|
T19 |
6 |
|
T23 |
106 |
|
T1 |
11351 |
| auto[1] |
auto[0] |
auto[1] |
363167 |
1 |
|
|
T19 |
1 |
|
T23 |
9 |
|
T1 |
1624 |
| auto[1] |
auto[1] |
auto[0] |
2426457 |
1 |
|
|
T23 |
64 |
|
T1 |
11718 |
|
T2 |
7 |
| auto[1] |
auto[1] |
auto[1] |
355021 |
1 |
|
|
T23 |
6 |
|
T1 |
1701 |
|
T12 |
1717 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7942849 |
1 |
|
|
T19 |
27 |
|
T22 |
203 |
|
T23 |
154 |
| auto[1] |
5572272 |
1 |
|
|
T19 |
33 |
|
T23 |
229 |
|
T1 |
27988 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12797256 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
371 |
| auto[1] |
717865 |
1 |
|
|
T23 |
12 |
|
T1 |
3533 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910185 |
1 |
|
|
T19 |
35 |
|
T22 |
203 |
|
T23 |
198 |
| auto[1] |
5604936 |
1 |
|
|
T19 |
25 |
|
T23 |
185 |
|
T1 |
27707 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2455496 |
1 |
|
|
T19 |
7 |
|
T23 |
70 |
|
T1 |
12206 |
| auto[1] |
auto[0] |
auto[1] |
360833 |
1 |
|
|
T23 |
6 |
|
T1 |
1767 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2431575 |
1 |
|
|
T19 |
18 |
|
T23 |
103 |
|
T1 |
11968 |
| auto[1] |
auto[1] |
auto[1] |
357032 |
1 |
|
|
T23 |
6 |
|
T1 |
1766 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7919911 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
203 |
| auto[1] |
5595210 |
1 |
|
|
T19 |
13 |
|
T23 |
180 |
|
T1 |
30565 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12797039 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
370 |
| auto[1] |
718082 |
1 |
|
|
T19 |
1 |
|
T23 |
13 |
|
T1 |
3549 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910939 |
1 |
|
|
T19 |
26 |
|
T22 |
203 |
|
T23 |
176 |
| auto[1] |
5604182 |
1 |
|
|
T19 |
34 |
|
T23 |
207 |
|
T1 |
28084 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2439911 |
1 |
|
|
T19 |
22 |
|
T23 |
106 |
|
T1 |
10712 |
| auto[1] |
auto[0] |
auto[1] |
358071 |
1 |
|
|
T19 |
1 |
|
T23 |
6 |
|
T1 |
1489 |
| auto[1] |
auto[1] |
auto[0] |
2446189 |
1 |
|
|
T19 |
11 |
|
T23 |
88 |
|
T1 |
13823 |
| auto[1] |
auto[1] |
auto[1] |
360011 |
1 |
|
|
T23 |
7 |
|
T1 |
2060 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889568 |
1 |
|
|
T19 |
48 |
|
T22 |
203 |
|
T23 |
193 |
| auto[1] |
5625553 |
1 |
|
|
T19 |
12 |
|
T23 |
190 |
|
T1 |
27408 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12801820 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
373 |
| auto[1] |
713301 |
1 |
|
|
T19 |
1 |
|
T23 |
10 |
|
T1 |
3556 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7937792 |
1 |
|
|
T19 |
35 |
|
T22 |
203 |
|
T23 |
201 |
| auto[1] |
5577329 |
1 |
|
|
T19 |
25 |
|
T23 |
182 |
|
T1 |
27750 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2424036 |
1 |
|
|
T19 |
20 |
|
T23 |
82 |
|
T1 |
11771 |
| auto[1] |
auto[0] |
auto[1] |
354097 |
1 |
|
|
T19 |
1 |
|
T23 |
6 |
|
T1 |
1722 |
| auto[1] |
auto[1] |
auto[0] |
2439992 |
1 |
|
|
T19 |
4 |
|
T23 |
90 |
|
T1 |
12423 |
| auto[1] |
auto[1] |
auto[1] |
359204 |
1 |
|
|
T23 |
4 |
|
T1 |
1834 |
|
T12 |
1639 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7914310 |
1 |
|
|
T19 |
37 |
|
T22 |
203 |
|
T23 |
176 |
| auto[1] |
5600811 |
1 |
|
|
T19 |
23 |
|
T23 |
207 |
|
T1 |
27482 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12798324 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
371 |
| auto[1] |
716797 |
1 |
|
|
T23 |
12 |
|
T1 |
3964 |
|
T12 |
4146 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7917897 |
1 |
|
|
T19 |
54 |
|
T22 |
203 |
|
T23 |
182 |
| auto[1] |
5597224 |
1 |
|
|
T19 |
6 |
|
T23 |
201 |
|
T1 |
30110 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2444808 |
1 |
|
|
T19 |
2 |
|
T23 |
110 |
|
T1 |
13820 |
| auto[1] |
auto[0] |
auto[1] |
358893 |
1 |
|
|
T23 |
6 |
|
T1 |
2126 |
|
T12 |
2146 |
| auto[1] |
auto[1] |
auto[0] |
2435619 |
1 |
|
|
T19 |
4 |
|
T23 |
79 |
|
T1 |
12326 |
| auto[1] |
auto[1] |
auto[1] |
357904 |
1 |
|
|
T23 |
6 |
|
T1 |
1838 |
|
T12 |
2000 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7928669 |
1 |
|
|
T19 |
42 |
|
T22 |
203 |
|
T23 |
164 |
| auto[1] |
5586452 |
1 |
|
|
T19 |
18 |
|
T23 |
219 |
|
T1 |
27813 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12803398 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
375 |
| auto[1] |
711723 |
1 |
|
|
T23 |
8 |
|
T1 |
3486 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7954978 |
1 |
|
|
T19 |
38 |
|
T22 |
203 |
|
T23 |
246 |
| auto[1] |
5560143 |
1 |
|
|
T19 |
22 |
|
T23 |
137 |
|
T1 |
27244 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2419282 |
1 |
|
|
T19 |
14 |
|
T23 |
59 |
|
T1 |
12030 |
| auto[1] |
auto[0] |
auto[1] |
354128 |
1 |
|
|
T23 |
5 |
|
T1 |
1753 |
|
T12 |
1877 |
| auto[1] |
auto[1] |
auto[0] |
2429138 |
1 |
|
|
T19 |
8 |
|
T23 |
70 |
|
T1 |
11728 |
| auto[1] |
auto[1] |
auto[1] |
357595 |
1 |
|
|
T23 |
3 |
|
T1 |
1733 |
|
T2 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7925937 |
1 |
|
|
T19 |
48 |
|
T22 |
203 |
|
T23 |
178 |
| auto[1] |
5589184 |
1 |
|
|
T19 |
12 |
|
T23 |
205 |
|
T1 |
28000 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12804062 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
373 |
| auto[1] |
711059 |
1 |
|
|
T23 |
10 |
|
T1 |
3520 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7959229 |
1 |
|
|
T19 |
57 |
|
T22 |
203 |
|
T23 |
197 |
| auto[1] |
5555892 |
1 |
|
|
T19 |
3 |
|
T23 |
186 |
|
T1 |
27389 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2427221 |
1 |
|
|
T23 |
71 |
|
T1 |
12598 |
|
T2 |
28 |
| auto[1] |
auto[0] |
auto[1] |
356452 |
1 |
|
|
T23 |
4 |
|
T1 |
1881 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2417612 |
1 |
|
|
T19 |
3 |
|
T23 |
105 |
|
T1 |
11271 |
| auto[1] |
auto[1] |
auto[1] |
354607 |
1 |
|
|
T23 |
6 |
|
T1 |
1639 |
|
T12 |
1601 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902781 |
1 |
|
|
T19 |
37 |
|
T22 |
203 |
|
T23 |
146 |
| auto[1] |
5612340 |
1 |
|
|
T19 |
23 |
|
T23 |
237 |
|
T1 |
28405 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12799715 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
372 |
| auto[1] |
715406 |
1 |
|
|
T23 |
11 |
|
T1 |
3734 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7914599 |
1 |
|
|
T19 |
46 |
|
T22 |
203 |
|
T23 |
186 |
| auto[1] |
5600522 |
1 |
|
|
T19 |
14 |
|
T23 |
197 |
|
T1 |
28352 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2443020 |
1 |
|
|
T19 |
11 |
|
T23 |
70 |
|
T1 |
12815 |
| auto[1] |
auto[0] |
auto[1] |
358506 |
1 |
|
|
T23 |
3 |
|
T1 |
2065 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2442096 |
1 |
|
|
T19 |
3 |
|
T23 |
116 |
|
T1 |
11803 |
| auto[1] |
auto[1] |
auto[1] |
356900 |
1 |
|
|
T23 |
8 |
|
T1 |
1669 |
|
T12 |
1771 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7901317 |
1 |
|
|
T19 |
52 |
|
T22 |
203 |
|
T23 |
215 |
| auto[1] |
5613804 |
1 |
|
|
T19 |
8 |
|
T23 |
168 |
|
T1 |
28940 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12800354 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
371 |
| auto[1] |
714767 |
1 |
|
|
T19 |
1 |
|
T23 |
12 |
|
T1 |
3685 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7935008 |
1 |
|
|
T19 |
35 |
|
T22 |
203 |
|
T23 |
224 |
| auto[1] |
5580113 |
1 |
|
|
T19 |
25 |
|
T23 |
159 |
|
T1 |
28507 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2414274 |
1 |
|
|
T19 |
22 |
|
T23 |
70 |
|
T1 |
12096 |
| auto[1] |
auto[0] |
auto[1] |
354710 |
1 |
|
|
T19 |
1 |
|
T23 |
4 |
|
T1 |
1787 |
| auto[1] |
auto[1] |
auto[0] |
2451072 |
1 |
|
|
T19 |
2 |
|
T23 |
77 |
|
T1 |
12726 |
| auto[1] |
auto[1] |
auto[1] |
360057 |
1 |
|
|
T23 |
8 |
|
T1 |
1898 |
|
T12 |
1883 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7952105 |
1 |
|
|
T19 |
34 |
|
T22 |
203 |
|
T23 |
227 |
| auto[1] |
5563016 |
1 |
|
|
T19 |
26 |
|
T23 |
156 |
|
T1 |
26744 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12799742 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
370 |
| auto[1] |
715379 |
1 |
|
|
T19 |
1 |
|
T23 |
13 |
|
T1 |
3576 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7915869 |
1 |
|
|
T19 |
43 |
|
T22 |
203 |
|
T23 |
164 |
| auto[1] |
5599252 |
1 |
|
|
T19 |
17 |
|
T23 |
219 |
|
T1 |
28494 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2467753 |
1 |
|
|
T19 |
12 |
|
T23 |
136 |
|
T1 |
13264 |
| auto[1] |
auto[0] |
auto[1] |
361186 |
1 |
|
|
T19 |
1 |
|
T23 |
9 |
|
T1 |
1908 |
| auto[1] |
auto[1] |
auto[0] |
2416120 |
1 |
|
|
T19 |
4 |
|
T23 |
70 |
|
T1 |
11654 |
| auto[1] |
auto[1] |
auto[1] |
354193 |
1 |
|
|
T23 |
4 |
|
T1 |
1668 |
|
T12 |
2245 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912793 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
178 |
| auto[1] |
5602328 |
1 |
|
|
T19 |
13 |
|
T23 |
205 |
|
T1 |
28352 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12800537 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
376 |
| auto[1] |
714584 |
1 |
|
|
T23 |
7 |
|
T1 |
3756 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7927168 |
1 |
|
|
T19 |
57 |
|
T22 |
203 |
|
T23 |
222 |
| auto[1] |
5587953 |
1 |
|
|
T19 |
3 |
|
T23 |
161 |
|
T1 |
28774 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2431831 |
1 |
|
|
T23 |
94 |
|
T1 |
11868 |
|
T2 |
27 |
| auto[1] |
auto[0] |
auto[1] |
356954 |
1 |
|
|
T23 |
7 |
|
T1 |
1677 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2441538 |
1 |
|
|
T19 |
3 |
|
T23 |
60 |
|
T1 |
13150 |
| auto[1] |
auto[1] |
auto[1] |
357630 |
1 |
|
|
T1 |
2079 |
|
T12 |
1791 |
|
T15 |
101 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7908442 |
1 |
|
|
T19 |
46 |
|
T22 |
203 |
|
T23 |
197 |
| auto[1] |
5606679 |
1 |
|
|
T19 |
14 |
|
T23 |
186 |
|
T1 |
27774 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12789481 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
373 |
| auto[1] |
725640 |
1 |
|
|
T19 |
1 |
|
T23 |
10 |
|
T1 |
3959 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863444 |
1 |
|
|
T19 |
38 |
|
T22 |
203 |
|
T23 |
180 |
| auto[1] |
5651677 |
1 |
|
|
T19 |
22 |
|
T23 |
203 |
|
T1 |
30076 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2466505 |
1 |
|
|
T19 |
16 |
|
T23 |
116 |
|
T1 |
13866 |
| auto[1] |
auto[0] |
auto[1] |
363324 |
1 |
|
|
T19 |
1 |
|
T23 |
8 |
|
T1 |
2109 |
| auto[1] |
auto[1] |
auto[0] |
2459532 |
1 |
|
|
T19 |
5 |
|
T23 |
77 |
|
T1 |
12251 |
| auto[1] |
auto[1] |
auto[1] |
362316 |
1 |
|
|
T23 |
2 |
|
T1 |
1850 |
|
T12 |
1708 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7880394 |
1 |
|
|
T19 |
48 |
|
T22 |
203 |
|
T23 |
255 |
| auto[1] |
5634727 |
1 |
|
|
T19 |
12 |
|
T23 |
128 |
|
T1 |
28899 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12796163 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
370 |
| auto[1] |
718958 |
1 |
|
|
T23 |
13 |
|
T1 |
3649 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7894086 |
1 |
|
|
T19 |
50 |
|
T22 |
203 |
|
T23 |
141 |
| auto[1] |
5621035 |
1 |
|
|
T19 |
10 |
|
T23 |
242 |
|
T1 |
28642 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2446963 |
1 |
|
|
T19 |
10 |
|
T23 |
144 |
|
T1 |
12481 |
| auto[1] |
auto[0] |
auto[1] |
359086 |
1 |
|
|
T23 |
10 |
|
T1 |
1866 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2455114 |
1 |
|
|
T23 |
85 |
|
T1 |
12512 |
|
T2 |
21 |
| auto[1] |
auto[1] |
auto[1] |
359872 |
1 |
|
|
T23 |
3 |
|
T1 |
1783 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904648 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
150 |
| auto[1] |
5610473 |
1 |
|
|
T19 |
13 |
|
T23 |
233 |
|
T1 |
29499 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12793790 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
371 |
| auto[1] |
721331 |
1 |
|
|
T19 |
1 |
|
T23 |
12 |
|
T1 |
3509 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7879295 |
1 |
|
|
T19 |
40 |
|
T22 |
203 |
|
T23 |
187 |
| auto[1] |
5635826 |
1 |
|
|
T19 |
20 |
|
T23 |
196 |
|
T1 |
27472 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2447387 |
1 |
|
|
T19 |
15 |
|
T23 |
62 |
|
T1 |
12199 |
| auto[1] |
auto[0] |
auto[1] |
360410 |
1 |
|
|
T19 |
1 |
|
T23 |
4 |
|
T1 |
1843 |
| auto[1] |
auto[1] |
auto[0] |
2467108 |
1 |
|
|
T19 |
4 |
|
T23 |
122 |
|
T1 |
11764 |
| auto[1] |
auto[1] |
auto[1] |
360921 |
1 |
|
|
T23 |
8 |
|
T1 |
1666 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906481 |
1 |
|
|
T19 |
43 |
|
T22 |
203 |
|
T23 |
165 |
| auto[1] |
5608640 |
1 |
|
|
T19 |
17 |
|
T23 |
218 |
|
T1 |
27279 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12800568 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
379 |
| auto[1] |
714553 |
1 |
|
|
T19 |
1 |
|
T23 |
4 |
|
T1 |
3478 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7932169 |
1 |
|
|
T19 |
24 |
|
T22 |
203 |
|
T23 |
254 |
| auto[1] |
5582952 |
1 |
|
|
T19 |
36 |
|
T23 |
129 |
|
T1 |
27609 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2429584 |
1 |
|
|
T19 |
24 |
|
T23 |
56 |
|
T1 |
12478 |
| auto[1] |
auto[0] |
auto[1] |
356567 |
1 |
|
|
T19 |
1 |
|
T23 |
1 |
|
T1 |
1821 |
| auto[1] |
auto[1] |
auto[0] |
2438815 |
1 |
|
|
T19 |
11 |
|
T23 |
69 |
|
T1 |
11653 |
| auto[1] |
auto[1] |
auto[1] |
357986 |
1 |
|
|
T23 |
3 |
|
T1 |
1657 |
|
T12 |
1743 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7903526 |
1 |
|
|
T19 |
38 |
|
T22 |
203 |
|
T23 |
153 |
| auto[1] |
5611595 |
1 |
|
|
T19 |
22 |
|
T23 |
230 |
|
T1 |
28225 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12796838 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
374 |
| auto[1] |
718283 |
1 |
|
|
T19 |
1 |
|
T23 |
9 |
|
T1 |
3603 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7905847 |
1 |
|
|
T19 |
31 |
|
T22 |
203 |
|
T23 |
197 |
| auto[1] |
5609274 |
1 |
|
|
T19 |
29 |
|
T23 |
186 |
|
T1 |
27656 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2447134 |
1 |
|
|
T19 |
20 |
|
T23 |
79 |
|
T1 |
11971 |
| auto[1] |
auto[0] |
auto[1] |
359553 |
1 |
|
|
T19 |
1 |
|
T23 |
4 |
|
T1 |
1809 |
| auto[1] |
auto[1] |
auto[0] |
2443857 |
1 |
|
|
T19 |
8 |
|
T23 |
98 |
|
T1 |
12082 |
| auto[1] |
auto[1] |
auto[1] |
358730 |
1 |
|
|
T23 |
5 |
|
T1 |
1794 |
|
T12 |
2038 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7897385 |
1 |
|
|
T19 |
46 |
|
T22 |
203 |
|
T23 |
188 |
| auto[1] |
5617736 |
1 |
|
|
T19 |
14 |
|
T23 |
195 |
|
T1 |
28336 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12792854 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
372 |
| auto[1] |
722267 |
1 |
|
|
T23 |
11 |
|
T1 |
3697 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7891995 |
1 |
|
|
T19 |
38 |
|
T22 |
203 |
|
T23 |
229 |
| auto[1] |
5623126 |
1 |
|
|
T19 |
22 |
|
T23 |
154 |
|
T1 |
28704 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2451827 |
1 |
|
|
T19 |
18 |
|
T23 |
89 |
|
T1 |
12216 |
| auto[1] |
auto[0] |
auto[1] |
361343 |
1 |
|
|
T23 |
6 |
|
T1 |
1795 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2449032 |
1 |
|
|
T19 |
4 |
|
T23 |
54 |
|
T1 |
12791 |
| auto[1] |
auto[1] |
auto[1] |
360924 |
1 |
|
|
T23 |
5 |
|
T1 |
1902 |
|
T12 |
1739 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7886842 |
1 |
|
|
T19 |
51 |
|
T22 |
203 |
|
T23 |
176 |
| auto[1] |
5628279 |
1 |
|
|
T19 |
9 |
|
T23 |
207 |
|
T1 |
28269 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12797091 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
375 |
| auto[1] |
718030 |
1 |
|
|
T23 |
8 |
|
T1 |
3601 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7898874 |
1 |
|
|
T19 |
43 |
|
T22 |
203 |
|
T23 |
217 |
| auto[1] |
5616247 |
1 |
|
|
T19 |
17 |
|
T23 |
166 |
|
T1 |
28216 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2450930 |
1 |
|
|
T19 |
13 |
|
T23 |
77 |
|
T1 |
12027 |
| auto[1] |
auto[0] |
auto[1] |
360337 |
1 |
|
|
T23 |
3 |
|
T1 |
1787 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2447287 |
1 |
|
|
T19 |
4 |
|
T23 |
81 |
|
T1 |
12588 |
| auto[1] |
auto[1] |
auto[1] |
357693 |
1 |
|
|
T23 |
5 |
|
T1 |
1814 |
|
T12 |
2123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912912 |
1 |
|
|
T19 |
44 |
|
T22 |
203 |
|
T23 |
231 |
| auto[1] |
5602209 |
1 |
|
|
T19 |
16 |
|
T23 |
152 |
|
T1 |
28290 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12794196 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
373 |
| auto[1] |
720925 |
1 |
|
|
T23 |
10 |
|
T1 |
3786 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7894272 |
1 |
|
|
T19 |
48 |
|
T22 |
203 |
|
T23 |
198 |
| auto[1] |
5620849 |
1 |
|
|
T19 |
12 |
|
T23 |
185 |
|
T1 |
28848 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2446032 |
1 |
|
|
T19 |
8 |
|
T23 |
120 |
|
T1 |
12950 |
| auto[1] |
auto[0] |
auto[1] |
359147 |
1 |
|
|
T23 |
7 |
|
T1 |
1945 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2453892 |
1 |
|
|
T19 |
4 |
|
T23 |
55 |
|
T1 |
12112 |
| auto[1] |
auto[1] |
auto[1] |
361778 |
1 |
|
|
T23 |
3 |
|
T1 |
1841 |
|
T12 |
1961 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910462 |
1 |
|
|
T19 |
39 |
|
T22 |
203 |
|
T23 |
188 |
| auto[1] |
5604659 |
1 |
|
|
T19 |
21 |
|
T23 |
195 |
|
T1 |
27062 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12797244 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
372 |
| auto[1] |
717877 |
1 |
|
|
T19 |
1 |
|
T23 |
11 |
|
T1 |
3896 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906412 |
1 |
|
|
T19 |
42 |
|
T22 |
203 |
|
T23 |
175 |
| auto[1] |
5608709 |
1 |
|
|
T19 |
18 |
|
T23 |
208 |
|
T1 |
30367 |