Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7914175 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
188 |
| auto[1] |
5600946 |
1 |
|
|
T19 |
13 |
|
T23 |
195 |
|
T1 |
27213 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12797203 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
367 |
| auto[1] |
717918 |
1 |
|
|
T19 |
1 |
|
T23 |
16 |
|
T1 |
3633 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912144 |
1 |
|
|
T19 |
34 |
|
T22 |
203 |
|
T23 |
158 |
| auto[1] |
5602977 |
1 |
|
|
T19 |
26 |
|
T23 |
225 |
|
T1 |
28147 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2454573 |
1 |
|
|
T19 |
25 |
|
T23 |
110 |
|
T1 |
12732 |
| auto[1] |
auto[0] |
auto[1] |
361950 |
1 |
|
|
T19 |
1 |
|
T23 |
10 |
|
T1 |
1934 |
| auto[1] |
auto[1] |
auto[0] |
2430486 |
1 |
|
|
T23 |
99 |
|
T1 |
11782 |
|
T2 |
5 |
| auto[1] |
auto[1] |
auto[1] |
355968 |
1 |
|
|
T23 |
6 |
|
T1 |
1699 |
|
T12 |
1823 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |