Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7908471 |
1 |
|
|
T19 |
30 |
|
T22 |
203 |
|
T23 |
193 |
| auto[1] |
5606650 |
1 |
|
|
T19 |
30 |
|
T23 |
190 |
|
T1 |
27768 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12790356 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
373 |
| auto[1] |
724765 |
1 |
|
|
T19 |
1 |
|
T23 |
10 |
|
T1 |
3750 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7864063 |
1 |
|
|
T19 |
49 |
|
T22 |
203 |
|
T23 |
151 |
| auto[1] |
5651058 |
1 |
|
|
T19 |
11 |
|
T23 |
232 |
|
T1 |
29223 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2461293 |
1 |
|
|
T19 |
2 |
|
T23 |
126 |
|
T1 |
12674 |
| auto[1] |
auto[0] |
auto[1] |
362030 |
1 |
|
|
T23 |
7 |
|
T1 |
1885 |
|
T12 |
1680 |
| auto[1] |
auto[1] |
auto[0] |
2465000 |
1 |
|
|
T19 |
8 |
|
T23 |
96 |
|
T1 |
12799 |
| auto[1] |
auto[1] |
auto[1] |
362735 |
1 |
|
|
T19 |
1 |
|
T23 |
3 |
|
T1 |
1865 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |