Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7923647 |
1 |
|
|
T19 |
38 |
|
T22 |
203 |
|
T23 |
148 |
| auto[1] |
5591474 |
1 |
|
|
T19 |
22 |
|
T23 |
235 |
|
T1 |
28951 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12796970 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
370 |
| auto[1] |
718151 |
1 |
|
|
T23 |
13 |
|
T1 |
3662 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7914079 |
1 |
|
|
T19 |
58 |
|
T22 |
203 |
|
T23 |
180 |
| auto[1] |
5601042 |
1 |
|
|
T19 |
2 |
|
T23 |
203 |
|
T1 |
28740 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2451026 |
1 |
|
|
T19 |
2 |
|
T23 |
63 |
|
T1 |
12337 |
| auto[1] |
auto[0] |
auto[1] |
360351 |
1 |
|
|
T23 |
3 |
|
T1 |
1775 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2431865 |
1 |
|
|
T23 |
127 |
|
T1 |
12741 |
|
T2 |
11 |
| auto[1] |
auto[1] |
auto[1] |
357800 |
1 |
|
|
T23 |
10 |
|
T1 |
1887 |
|
T12 |
1914 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |