Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7882442 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
214 |
| auto[1] |
5632679 |
1 |
|
|
T19 |
13 |
|
T23 |
169 |
|
T1 |
29627 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12792510 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
363 |
| auto[1] |
722611 |
1 |
|
|
T23 |
20 |
|
T1 |
3532 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7876569 |
1 |
|
|
T19 |
49 |
|
T22 |
203 |
|
T23 |
139 |
| auto[1] |
5638552 |
1 |
|
|
T19 |
11 |
|
T23 |
244 |
|
T1 |
27540 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2437972 |
1 |
|
|
T19 |
11 |
|
T23 |
143 |
|
T1 |
12217 |
| auto[1] |
auto[0] |
auto[1] |
357926 |
1 |
|
|
T23 |
15 |
|
T1 |
1836 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2477969 |
1 |
|
|
T23 |
81 |
|
T1 |
11791 |
|
T2 |
17 |
| auto[1] |
auto[1] |
auto[1] |
364685 |
1 |
|
|
T23 |
5 |
|
T1 |
1696 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |