Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7893004 |
1 |
|
|
T19 |
41 |
|
T22 |
203 |
|
T23 |
178 |
| auto[1] |
5622117 |
1 |
|
|
T19 |
19 |
|
T23 |
205 |
|
T1 |
26564 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12800644 |
1 |
|
|
T19 |
59 |
|
T22 |
203 |
|
T23 |
373 |
| auto[1] |
714477 |
1 |
|
|
T19 |
1 |
|
T23 |
10 |
|
T1 |
3595 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7928561 |
1 |
|
|
T19 |
35 |
|
T22 |
203 |
|
T23 |
160 |
| auto[1] |
5586560 |
1 |
|
|
T19 |
25 |
|
T23 |
223 |
|
T1 |
27954 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2434787 |
1 |
|
|
T19 |
19 |
|
T23 |
89 |
|
T1 |
12887 |
| auto[1] |
auto[0] |
auto[1] |
356454 |
1 |
|
|
T19 |
1 |
|
T23 |
5 |
|
T1 |
1929 |
| auto[1] |
auto[1] |
auto[0] |
2437296 |
1 |
|
|
T19 |
5 |
|
T23 |
124 |
|
T1 |
11472 |
| auto[1] |
auto[1] |
auto[1] |
358023 |
1 |
|
|
T23 |
5 |
|
T1 |
1666 |
|
T12 |
1735 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |