Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7909454 |
1 |
|
|
T19 |
45 |
|
T22 |
203 |
|
T23 |
211 |
| auto[1] |
5605667 |
1 |
|
|
T19 |
15 |
|
T23 |
172 |
|
T1 |
28384 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11166449 |
1 |
|
|
T19 |
57 |
|
T22 |
203 |
|
T23 |
333 |
| auto[1] |
2348672 |
1 |
|
|
T19 |
3 |
|
T23 |
50 |
|
T1 |
17826 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7918267 |
1 |
|
|
T19 |
54 |
|
T22 |
203 |
|
T23 |
213 |
| auto[1] |
5596854 |
1 |
|
|
T19 |
6 |
|
T23 |
170 |
|
T1 |
29005 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1625474 |
1 |
|
|
T19 |
3 |
|
T23 |
60 |
|
T1 |
5386 |
| auto[1] |
auto[0] |
auto[1] |
1177523 |
1 |
|
|
T19 |
3 |
|
T23 |
20 |
|
T1 |
8746 |
| auto[1] |
auto[1] |
auto[0] |
1622708 |
1 |
|
|
T23 |
60 |
|
T1 |
5793 |
|
T2 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1171149 |
1 |
|
|
T23 |
30 |
|
T1 |
9080 |
|
T2 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |