Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7942849 |
1 |
|
|
T19 |
27 |
|
T22 |
203 |
|
T23 |
154 |
| auto[1] |
5572272 |
1 |
|
|
T19 |
33 |
|
T23 |
229 |
|
T1 |
27988 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11179688 |
1 |
|
|
T19 |
56 |
|
T22 |
203 |
|
T23 |
273 |
| auto[1] |
2335433 |
1 |
|
|
T19 |
4 |
|
T23 |
110 |
|
T1 |
17714 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7941760 |
1 |
|
|
T19 |
49 |
|
T22 |
203 |
|
T23 |
173 |
| auto[1] |
5573361 |
1 |
|
|
T19 |
11 |
|
T23 |
210 |
|
T1 |
28832 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1637072 |
1 |
|
|
T23 |
44 |
|
T1 |
5424 |
|
T2 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1178741 |
1 |
|
|
T23 |
56 |
|
T1 |
9008 |
|
T2 |
13 |
| auto[1] |
auto[1] |
auto[0] |
1600856 |
1 |
|
|
T19 |
7 |
|
T23 |
56 |
|
T1 |
5694 |
| auto[1] |
auto[1] |
auto[1] |
1156692 |
1 |
|
|
T19 |
4 |
|
T23 |
54 |
|
T1 |
8706 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |