Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7919911 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
203 |
| auto[1] |
5595210 |
1 |
|
|
T19 |
13 |
|
T23 |
180 |
|
T1 |
30565 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11172515 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
236 |
| auto[1] |
2342606 |
1 |
|
|
T23 |
147 |
|
T1 |
16435 |
|
T2 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7920233 |
1 |
|
|
T19 |
53 |
|
T22 |
203 |
|
T23 |
167 |
| auto[1] |
5594888 |
1 |
|
|
T19 |
7 |
|
T23 |
216 |
|
T1 |
27094 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1625456 |
1 |
|
|
T19 |
7 |
|
T23 |
43 |
|
T1 |
4909 |
| auto[1] |
auto[0] |
auto[1] |
1175948 |
1 |
|
|
T23 |
91 |
|
T1 |
7612 |
|
T2 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1626826 |
1 |
|
|
T23 |
26 |
|
T1 |
5750 |
|
T12 |
7414 |
| auto[1] |
auto[1] |
auto[1] |
1166658 |
1 |
|
|
T23 |
56 |
|
T1 |
8823 |
|
T2 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |