Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889568 |
1 |
|
|
T19 |
48 |
|
T22 |
203 |
|
T23 |
193 |
| auto[1] |
5625553 |
1 |
|
|
T19 |
12 |
|
T23 |
190 |
|
T1 |
27408 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11160518 |
1 |
|
|
T19 |
54 |
|
T22 |
203 |
|
T23 |
337 |
| auto[1] |
2354603 |
1 |
|
|
T19 |
6 |
|
T23 |
46 |
|
T1 |
17689 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912944 |
1 |
|
|
T19 |
47 |
|
T22 |
203 |
|
T23 |
251 |
| auto[1] |
5602177 |
1 |
|
|
T19 |
13 |
|
T23 |
132 |
|
T1 |
28966 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1616960 |
1 |
|
|
T19 |
5 |
|
T23 |
48 |
|
T1 |
5602 |
| auto[1] |
auto[0] |
auto[1] |
1172798 |
1 |
|
|
T19 |
6 |
|
T23 |
15 |
|
T1 |
9053 |
| auto[1] |
auto[1] |
auto[0] |
1630614 |
1 |
|
|
T19 |
2 |
|
T23 |
38 |
|
T1 |
5675 |
| auto[1] |
auto[1] |
auto[1] |
1181805 |
1 |
|
|
T23 |
31 |
|
T1 |
8636 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |