Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7914310 |
1 |
|
|
T19 |
37 |
|
T22 |
203 |
|
T23 |
176 |
| auto[1] |
5600811 |
1 |
|
|
T19 |
23 |
|
T23 |
207 |
|
T1 |
27482 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11167426 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
308 |
| auto[1] |
2347695 |
1 |
|
|
T23 |
75 |
|
T1 |
18352 |
|
T2 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7923067 |
1 |
|
|
T19 |
54 |
|
T22 |
203 |
|
T23 |
216 |
| auto[1] |
5592054 |
1 |
|
|
T19 |
6 |
|
T23 |
167 |
|
T1 |
29497 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1631114 |
1 |
|
|
T19 |
2 |
|
T23 |
33 |
|
T1 |
5667 |
| auto[1] |
auto[0] |
auto[1] |
1175599 |
1 |
|
|
T23 |
21 |
|
T1 |
9226 |
|
T2 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1613245 |
1 |
|
|
T19 |
4 |
|
T23 |
59 |
|
T1 |
5478 |
| auto[1] |
auto[1] |
auto[1] |
1172096 |
1 |
|
|
T23 |
54 |
|
T1 |
9126 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |