Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7928669 |
1 |
|
|
T19 |
42 |
|
T22 |
203 |
|
T23 |
164 |
| auto[1] |
5586452 |
1 |
|
|
T19 |
18 |
|
T23 |
219 |
|
T1 |
27813 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11161793 |
1 |
|
|
T19 |
58 |
|
T22 |
203 |
|
T23 |
275 |
| auto[1] |
2353328 |
1 |
|
|
T19 |
2 |
|
T23 |
108 |
|
T1 |
18006 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7920707 |
1 |
|
|
T19 |
52 |
|
T22 |
203 |
|
T23 |
137 |
| auto[1] |
5594414 |
1 |
|
|
T19 |
8 |
|
T23 |
246 |
|
T1 |
29248 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1623665 |
1 |
|
|
T19 |
1 |
|
T23 |
63 |
|
T1 |
5421 |
| auto[1] |
auto[0] |
auto[1] |
1181109 |
1 |
|
|
T19 |
2 |
|
T23 |
49 |
|
T1 |
9000 |
| auto[1] |
auto[1] |
auto[0] |
1617421 |
1 |
|
|
T19 |
5 |
|
T23 |
75 |
|
T1 |
5821 |
| auto[1] |
auto[1] |
auto[1] |
1172219 |
1 |
|
|
T23 |
59 |
|
T1 |
9006 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |