Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7925937 |
1 |
|
|
T19 |
48 |
|
T22 |
203 |
|
T23 |
178 |
| auto[1] |
5589184 |
1 |
|
|
T19 |
12 |
|
T23 |
205 |
|
T1 |
28000 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11166871 |
1 |
|
|
T19 |
58 |
|
T22 |
203 |
|
T23 |
312 |
| auto[1] |
2348250 |
1 |
|
|
T19 |
2 |
|
T23 |
71 |
|
T1 |
17239 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7919198 |
1 |
|
|
T19 |
51 |
|
T22 |
203 |
|
T23 |
240 |
| auto[1] |
5595923 |
1 |
|
|
T19 |
9 |
|
T23 |
143 |
|
T1 |
28781 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1638287 |
1 |
|
|
T19 |
3 |
|
T23 |
23 |
|
T1 |
5531 |
| auto[1] |
auto[0] |
auto[1] |
1180082 |
1 |
|
|
T19 |
2 |
|
T23 |
23 |
|
T1 |
8735 |
| auto[1] |
auto[1] |
auto[0] |
1609386 |
1 |
|
|
T19 |
4 |
|
T23 |
49 |
|
T1 |
6011 |
| auto[1] |
auto[1] |
auto[1] |
1168168 |
1 |
|
|
T23 |
48 |
|
T1 |
8504 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |