Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902781 |
1 |
|
|
T19 |
37 |
|
T22 |
203 |
|
T23 |
146 |
| auto[1] |
5612340 |
1 |
|
|
T19 |
23 |
|
T23 |
237 |
|
T1 |
28405 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11159846 |
1 |
|
|
T19 |
53 |
|
T22 |
203 |
|
T23 |
239 |
| auto[1] |
2355275 |
1 |
|
|
T19 |
7 |
|
T23 |
144 |
|
T1 |
17248 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7903306 |
1 |
|
|
T19 |
49 |
|
T22 |
203 |
|
T23 |
198 |
| auto[1] |
5611815 |
1 |
|
|
T19 |
11 |
|
T23 |
185 |
|
T1 |
28479 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1620829 |
1 |
|
|
T23 |
20 |
|
T1 |
5534 |
|
T2 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1177175 |
1 |
|
|
T23 |
56 |
|
T1 |
8711 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1635711 |
1 |
|
|
T19 |
4 |
|
T23 |
21 |
|
T1 |
5697 |
| auto[1] |
auto[1] |
auto[1] |
1178100 |
1 |
|
|
T19 |
7 |
|
T23 |
88 |
|
T1 |
8537 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |