Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7952105 |
1 |
|
|
T19 |
34 |
|
T22 |
203 |
|
T23 |
227 |
| auto[1] |
5563016 |
1 |
|
|
T19 |
26 |
|
T23 |
156 |
|
T1 |
26744 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11172696 |
1 |
|
|
T19 |
60 |
|
T22 |
203 |
|
T23 |
315 |
| auto[1] |
2342425 |
1 |
|
|
T23 |
68 |
|
T1 |
18072 |
|
T2 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922543 |
1 |
|
|
T19 |
54 |
|
T22 |
203 |
|
T23 |
205 |
| auto[1] |
5592578 |
1 |
|
|
T19 |
6 |
|
T23 |
178 |
|
T1 |
29442 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1648170 |
1 |
|
|
T19 |
2 |
|
T23 |
49 |
|
T1 |
5661 |
| auto[1] |
auto[0] |
auto[1] |
1189540 |
1 |
|
|
T23 |
35 |
|
T1 |
9764 |
|
T2 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1601983 |
1 |
|
|
T19 |
4 |
|
T23 |
61 |
|
T1 |
5709 |
| auto[1] |
auto[1] |
auto[1] |
1152885 |
1 |
|
|
T23 |
33 |
|
T1 |
8308 |
|
T2 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |